Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405714
R. Yu, Y. Xu
A 4th-order bandpass ΣΔ modulator employing electromechanical filter as loop filter is proposed. The electromechanical loop filter has the advantages of low power consumption and accurate center frequency without the need for tuning. The proposed bandpass SigmaDelta modulator is implemented in a 0.35-μm SiGe BiCMOS technology and tested with a 110-MHz SAW filter. When sampled at 440 MHz, the prototype chip achieves 65-dB DR and 60-dB peak SNDR in a 1-MHz signal bandwidth.
{"title":"A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filter","authors":"R. Yu, Y. Xu","doi":"10.1109/CICC.2007.4405714","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405714","url":null,"abstract":"A 4th-order bandpass ΣΔ modulator employing electromechanical filter as loop filter is proposed. The electromechanical loop filter has the advantages of low power consumption and accurate center frequency without the need for tuning. The proposed bandpass SigmaDelta modulator is implemented in a 0.35-μm SiGe BiCMOS technology and tested with a 110-MHz SAW filter. When sampled at 440 MHz, the prototype chip achieves 65-dB DR and 60-dB peak SNDR in a 1-MHz signal bandwidth.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405821
Hua Wang, A. Hajimiri
This paper presents a 10-bit wideband Cartesian phase rotator with a novel linear digital VGA implemented in a 0.13 um CMOS process. The VGA topology is robust to device modeling uncertainties and PVT variations. The system provides 7.8 dB voltage gain with -3 dB bandwidth of 7.6 GHz. A maximum phase error of 2deg has been achieved for a phase shifting range of 360deg with 32 phase steps of 11.25deg. The capability to compensate for mismatched quadrature inputs is also demonstrated.
本文提出了一种采用0.13 um CMOS工艺实现的10位宽带笛卡尔相位旋转器，该旋转器具有新颖的线性数字VGA。VGA拓扑对器件建模不确定性和PVT变化具有鲁棒性。系统提供7.8 dB电压增益，-3 dB带宽为7.6 GHz。当相移范围为360°，32个相移步为11.25°时，最大相位误差为2°。补偿不匹配正交输入的能力也得到了证明。
{"title":"A Wideband CMOS Linear Digital Phase Rotator","authors":"Hua Wang, A. Hajimiri","doi":"10.1109/CICC.2007.4405821","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405821","url":null,"abstract":"This paper presents a 10-bit wideband Cartesian phase rotator with a novel linear digital VGA implemented in a 0.13 um CMOS process. The VGA topology is robust to device modeling uncertainties and PVT variations. The system provides 7.8 dB voltage gain with -3 dB bandwidth of 7.6 GHz. A maximum phase error of 2deg has been achieved for a phase shifting range of 360deg with 32 phase steps of 11.25deg. The capability to compensate for mismatched quadrature inputs is also demonstrated.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"40 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124612069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405796
L. Clark, M. Kabir, J. Knudsen
A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.
{"title":"A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity","authors":"L. Clark, M. Kabir, J. Knudsen","doi":"10.1109/CICC.2007.4405796","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405796","url":null,"abstract":"A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126478041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405833
D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare
The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
PA6T核心是该电源架构的无序超标量实现。功率效率是通过微架构、逻辑和电路优化实现的。该处理器采用65nm，三Vt，双氧化物8 M CMOS工艺制造。2ghz时最坏功耗为7w。
{"title":"A 2GHz, 7W (max) 64b PowerTM Microprocessor Core","authors":"D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare","doi":"10.1109/CICC.2007.4405833","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405833","url":null,"abstract":"The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131238228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405737
Yi-Bin Hsieh, Y. Kao
A new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the SigmaDelta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18 mum CMOS process. The clock of 1.5 GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10 KHz) and 35 ps-pp period jitter are achieved in this study. The size of chip area is 0.44times0.48 mm2. The power consumption is 27 mW.
{"title":"A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes","authors":"Yi-Bin Hsieh, Y. Kao","doi":"10.1109/CICC.2007.4405737","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405737","url":null,"abstract":"A new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the SigmaDelta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18 mum CMOS process. The clock of 1.5 GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10 KHz) and 35 ps-pp period jitter are achieved in this study. The size of chip area is 0.44times0.48 mm2. The power consumption is 27 mW.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133179433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405775
Deyi Pi, Byung-Kwan Chun, P. Heydari
A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.
提出了一种基于综合的电流模式逻辑(CML)缓冲器/放大器带宽增强技术，该技术的带宽增强比(BWER)为4.84，接近已证实的理论上限4.93。通过采用完整的逐步设计方法，所提出的技术可以应用于任何负载条件，其特征是负载电容与transconductor电池输出电容之间的比率。为了节省芯片面积，采用低阶无源网络设计了几种原型缓冲/放大电路。测试芯片采用0.18 μ m CMOS工艺制造，测量结果显示BWER为3.8。
{"title":"A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers","authors":"Deyi Pi, Byung-Kwan Chun, P. Heydari","doi":"10.1109/CICC.2007.4405775","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405775","url":null,"abstract":"A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"126 40","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114053241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405718
D. Duarte, G. Geannopoulos, U. Mughal, Keng L. Wong, G. Taylor
Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.
{"title":"Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process","authors":"D. Duarte, G. Geannopoulos, U. Mughal, Keng L. Wong, G. Taylor","doi":"10.1109/CICC.2007.4405718","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405718","url":null,"abstract":"Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122566356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405836
D. Markovic, Chen Chang, B. Richards, Hayden Kwok-Hay So, B. Nikolić, R. Brodersen
A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.
{"title":"ASIC Design and Verification in an FPGA Environment","authors":"D. Markovic, Chen Chang, B. Richards, Hayden Kwok-Hay So, B. Nikolić, R. Brodersen","doi":"10.1109/CICC.2007.4405836","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405836","url":null,"abstract":"A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405862
B. Peterson, K. Mayaram, T. Fiez
An automated process, requiring the fabrication of only a few simple test structures, can efficiently characterize a silicon substrate by extracting the process constants of a Z-parameter based macromodel. The resulting model is used to generate a resistive substrate network that can be used in noise coupling simulations. This process has been integrated into the Cadence DFII environment to provide a seamless substrate noise simulation package which alleviates the need for pre-characterized libraries.
{"title":"Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates","authors":"B. Peterson, K. Mayaram, T. Fiez","doi":"10.1109/CICC.2007.4405862","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405862","url":null,"abstract":"An automated process, requiring the fabrication of only a few simple test structures, can efficiently characterize a silicon substrate by extracting the process constants of a Z-parameter based macromodel. The resulting model is used to generate a resistive substrate network that can be used in noise coupling simulations. This process has been integrated into the Cadence DFII environment to provide a seamless substrate noise simulation package which alleviates the need for pre-characterized libraries.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405781
B. Parvais, S. Hu, M. Dehan, A. Mercha, S. Decoutere
A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.
{"title":"An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs","authors":"B. Parvais, S. Hu, M. Dehan, A. Mercha, S. Decoutere","doi":"10.1109/CICC.2007.4405781","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405781","url":null,"abstract":"A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115764805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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