Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405808
R. Topaloglu
Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that enables the exploitation of STI stress for performance improvement of standard cells and custom integrated circuits. We start with process simulation of a 65 nm STI technology, and generate mobility models for STI stress based on these simulations. Based on these models, we are able to perform STI stress-aware modeling and simulation using SPICE. We then present our optimization of STI stress in standard-cell and custom designs using active-layer (dummy) fill insertion to alter the STI widths. Circuit level experimental results are based on a miscellaneous ring oscillator, which is known to correlate well to silicon. Using a generic 65 nm cell library, we show that the STI-optimized designs provide up to 8% improvement in clock frequency. The frequency improvement through exploitation of STI stress comes at practically zero cost with respect to area and wire length.
{"title":"Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization","authors":"R. Topaloglu","doi":"10.1109/CICC.2007.4405808","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405808","url":null,"abstract":"Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that enables the exploitation of STI stress for performance improvement of standard cells and custom integrated circuits. We start with process simulation of a 65 nm STI technology, and generate mobility models for STI stress based on these simulations. Based on these models, we are able to perform STI stress-aware modeling and simulation using SPICE. We then present our optimization of STI stress in standard-cell and custom designs using active-layer (dummy) fill insertion to alter the STI widths. Circuit level experimental results are based on a miscellaneous ring oscillator, which is known to correlate well to silicon. Using a generic 65 nm cell library, we show that the STI-optimized designs provide up to 8% improvement in clock frequency. The frequency improvement through exploitation of STI stress comes at practically zero cost with respect to area and wire length.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405818
I. Elahi, K. Muhammad
We present a digital calibration technique for improving IIP2 by injecting DC offset at the mixer. Most receivers offer DC offset cancellation circuitry, and a targeted non-zero DC offset at mixer output is up-converted to RF carrier frequency due to poor reverse isolation of the mixer switch. By controlling amplitude of the injected DC, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis and measurement data for a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process are presented. Calibrated IIP2 of 50 dBm is reported at LNA input.
{"title":"On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless Receiver","authors":"I. Elahi, K. Muhammad","doi":"10.1109/CICC.2007.4405818","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405818","url":null,"abstract":"We present a digital calibration technique for improving IIP2 by injecting DC offset at the mixer. Most receivers offer DC offset cancellation circuitry, and a targeted non-zero DC offset at mixer output is up-converted to RF carrier frequency due to poor reverse isolation of the mixer switch. By controlling amplitude of the injected DC, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis and measurement data for a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process are presented. Calibrated IIP2 of 50 dBm is reported at LNA input.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134321680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405773
Ahmad Darabiha, A. C. Carusone, F. Kschischang
A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.
{"title":"A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS","authors":"Ahmad Darabiha, A. C. Carusone, F. Kschischang","doi":"10.1109/CICC.2007.4405773","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405773","url":null,"abstract":"A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405737
Yi-Bin Hsieh, Y. Kao
A new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the SigmaDelta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18 mum CMOS process. The clock of 1.5 GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10 KHz) and 35 ps-pp period jitter are achieved in this study. The size of chip area is 0.44times0.48 mm2. The power consumption is 27 mW.
{"title":"A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes","authors":"Yi-Bin Hsieh, Y. Kao","doi":"10.1109/CICC.2007.4405737","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405737","url":null,"abstract":"A new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the SigmaDelta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18 mum CMOS process. The clock of 1.5 GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10 KHz) and 35 ps-pp period jitter are achieved in this study. The size of chip area is 0.44times0.48 mm2. The power consumption is 27 mW.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133179433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405853
Sujiang Rong, H. Luong
A notch-peak cancellation concept is introduced in transformer-based LC tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18 μm CMOS process and operated at 1V supply, the QVCO prototype measures a stable dual-band operation from 3.27 GHz to 5.02 GHz and from 9.48 GHz to 11.36 GHz. At 4.2 GHz and 10 GHz, the QVCO measures phase noise at 1 MHz offset of -116.3 dBc/Hz and -112 dBc/Hz, and sideband rejection ratios (SBR) of 49 dB and 47 dB while drawing 6 mA and 10 mA, respectively. The QVCO occupies an active area of 0.88 mm2.
{"title":"A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOS","authors":"Sujiang Rong, H. Luong","doi":"10.1109/CICC.2007.4405853","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405853","url":null,"abstract":"A notch-peak cancellation concept is introduced in transformer-based LC tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18 μm CMOS process and operated at 1V supply, the QVCO prototype measures a stable dual-band operation from 3.27 GHz to 5.02 GHz and from 9.48 GHz to 11.36 GHz. At 4.2 GHz and 10 GHz, the QVCO measures phase noise at 1 MHz offset of -116.3 dBc/Hz and -112 dBc/Hz, and sideband rejection ratios (SBR) of 49 dB and 47 dB while drawing 6 mA and 10 mA, respectively. The QVCO occupies an active area of 0.88 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405775
Deyi Pi, Byung-Kwan Chun, P. Heydari
A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.
提出了一种基于综合的电流模式逻辑(CML)缓冲器/放大器带宽增强技术，该技术的带宽增强比(BWER)为4.84，接近已证实的理论上限4.93。通过采用完整的逐步设计方法，所提出的技术可以应用于任何负载条件，其特征是负载电容与transconductor电池输出电容之间的比率。为了节省芯片面积，采用低阶无源网络设计了几种原型缓冲/放大电路。测试芯片采用0.18 μ m CMOS工艺制造，测量结果显示BWER为3.8。
{"title":"A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers","authors":"Deyi Pi, Byung-Kwan Chun, P. Heydari","doi":"10.1109/CICC.2007.4405775","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405775","url":null,"abstract":"A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"126 40","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114053241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405718
D. Duarte, G. Geannopoulos, U. Mughal, Keng L. Wong, G. Taylor
Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.
{"title":"Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process","authors":"D. Duarte, G. Geannopoulos, U. Mughal, Keng L. Wong, G. Taylor","doi":"10.1109/CICC.2007.4405718","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405718","url":null,"abstract":"Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122566356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405836
D. Markovic, Chen Chang, B. Richards, Hayden Kwok-Hay So, B. Nikolić, R. Brodersen
A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.
{"title":"ASIC Design and Verification in an FPGA Environment","authors":"D. Markovic, Chen Chang, B. Richards, Hayden Kwok-Hay So, B. Nikolić, R. Brodersen","doi":"10.1109/CICC.2007.4405836","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405836","url":null,"abstract":"A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405862
B. Peterson, K. Mayaram, T. Fiez
An automated process, requiring the fabrication of only a few simple test structures, can efficiently characterize a silicon substrate by extracting the process constants of a Z-parameter based macromodel. The resulting model is used to generate a resistive substrate network that can be used in noise coupling simulations. This process has been integrated into the Cadence DFII environment to provide a seamless substrate noise simulation package which alleviates the need for pre-characterized libraries.
{"title":"Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates","authors":"B. Peterson, K. Mayaram, T. Fiez","doi":"10.1109/CICC.2007.4405862","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405862","url":null,"abstract":"An automated process, requiring the fabrication of only a few simple test structures, can efficiently characterize a silicon substrate by extracting the process constants of a Z-parameter based macromodel. The resulting model is used to generate a resistive substrate network that can be used in noise coupling simulations. This process has been integrated into the Cadence DFII environment to provide a seamless substrate noise simulation package which alleviates the need for pre-characterized libraries.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405781
B. Parvais, S. Hu, M. Dehan, A. Mercha, S. Decoutere
A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.
{"title":"An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs","authors":"B. Parvais, S. Hu, M. Dehan, A. Mercha, S. Decoutere","doi":"10.1109/CICC.2007.4405781","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405781","url":null,"abstract":"A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115764805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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