Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405854
S. Parikh, Glenn Gulak, P. Chow
An image sensor designed with standard 0.18 mum CMOS technology is used to construct a DNA microarray scanner. The detection limit of 4590 fluorophores/mum2 is compared with 4.49 fluorophores/mum2 of a commercial photomultiplier-tube-based microarray scanner. The performance gap can be reduced by improving optical coupling, mechanical alignment, laser power supply noise, improved circuit noise and an increase in the conversion gain. The CMOS sensor offers multiple-pixels for reduced scan time and an integrated analog-to-digital converter.
采用标准的0.18 μ m CMOS技术设计图像传感器，构建DNA微阵列扫描仪。将4590个荧光团/mum2的检测限与商用光电倍增管微阵列扫描仪的4.49个荧光团/mum2进行了比较。性能差距可以通过改善光耦合、机械对准、激光电源噪声、改善电路噪声和增加转换增益来减小。CMOS传感器提供多像素，以减少扫描时间和集成的模数转换器。
{"title":"A CMOS Image Sensor for DNA Microarrays","authors":"S. Parikh, Glenn Gulak, P. Chow","doi":"10.1109/CICC.2007.4405854","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405854","url":null,"abstract":"An image sensor designed with standard 0.18 mum CMOS technology is used to construct a DNA microarray scanner. The detection limit of 4590 fluorophores/mum2 is compared with 4.49 fluorophores/mum2 of a commercial photomultiplier-tube-based microarray scanner. The performance gap can be reduced by improving optical coupling, mechanical alignment, laser power supply noise, improved circuit noise and an increase in the conversion gain. The CMOS sensor offers multiple-pixels for reduced scan time and an integrated analog-to-digital converter.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405788
A. Safarian, Lei Zhou, P. Heydari
This paper presents a current-equalized distributed RF front-end for ultra-wideband (UWB) direct conversion receivers. The proposed distributed direct conversion RF front-end (DDC-RF) utilizes a current equalization technique to remove the systematic IQ phase and gain imbalances imposed by the intrinsic wideband characteristics of the distributed circuits. Fabricated in a 0.13 mum CMOS process, the proposed DDC-RF prototype achieves 12.1-13.4 dB gain and an average noise-figure (NF) of 6.8 dB across the UWB frequency band with 50 Omega wideband-matched termination. A programmable RF termination allows the DDC-RF to achieve higher gain of 16.5 dB and lower NF of 4.3 dB, while trading off with few decibels of mismatch at the RF input port. The measured IQ gain and phase imbalances are less than plusmn0.5 dB and plusmn2.5deg, respectively. The 2-stage DDC-RF consumes 8 mA from 1.8 V supply voltage, and occupies an area of 1.2 mm2.
{"title":"A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers","authors":"A. Safarian, Lei Zhou, P. Heydari","doi":"10.1109/CICC.2007.4405788","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405788","url":null,"abstract":"This paper presents a current-equalized distributed RF front-end for ultra-wideband (UWB) direct conversion receivers. The proposed distributed direct conversion RF front-end (DDC-RF) utilizes a current equalization technique to remove the systematic IQ phase and gain imbalances imposed by the intrinsic wideband characteristics of the distributed circuits. Fabricated in a 0.13 mum CMOS process, the proposed DDC-RF prototype achieves 12.1-13.4 dB gain and an average noise-figure (NF) of 6.8 dB across the UWB frequency band with 50 Omega wideband-matched termination. A programmable RF termination allows the DDC-RF to achieve higher gain of 16.5 dB and lower NF of 4.3 dB, while trading off with few decibels of mismatch at the RF input port. The measured IQ gain and phase imbalances are less than plusmn0.5 dB and plusmn2.5deg, respectively. The 2-stage DDC-RF consumes 8 mA from 1.8 V supply voltage, and occupies an area of 1.2 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405730
V. V. Kaenel, T. Takayanagi
Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.
{"title":"Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC","authors":"V. V. Kaenel, T. Takayanagi","doi":"10.1109/CICC.2007.4405730","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405730","url":null,"abstract":"Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122595057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405705
E. Ghafar-Zadeh, M. Sawan
In this paper, we put forward a CMOS-based capacitive interface circuit for lab-on-chip applications. This simple capacitive detector is implemented in the TSMC 0.18 CMOS process to which we incorporate microfluidic channels. In addition, we address the often-neglected challenges of microfluidic packaging for integrated biochemical sensors by proposing an efficient direct-write microfluidic packaging procedure. The simulation, fabrication and preliminary measurement results are also presented and discussed.
{"title":"A 0.18 μm CMOS Capacitive Detection Lab-on-Chip","authors":"E. Ghafar-Zadeh, M. Sawan","doi":"10.1109/CICC.2007.4405705","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405705","url":null,"abstract":"In this paper, we put forward a CMOS-based capacitive interface circuit for lab-on-chip applications. This simple capacitive detector is implemented in the TSMC 0.18 CMOS process to which we incorporate microfluidic channels. In addition, we address the often-neglected challenges of microfluidic packaging for integrated biochemical sensors by proposing an efficient direct-write microfluidic packaging procedure. The simulation, fabrication and preliminary measurement results are also presented and discussed.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114599491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405742
J. Li, Robert Leboeuf, M. Courcy, G. Manganaro
A 1.8 V 10 b 210 MS/s CMOS pipelined ADC in 0.18 um CMOS process is presented. The low power consumption at high sampling rate is achieved by using an opamp-sharing technique in 2.5 b/stage pipelined ADC architecture. The opamp settling behavior is well controlled through a regulated switch driving scheme. The clever arrangement of capacitor array renders superior SFDR for the same given systematic mismatch. With a 20 MHz input signal, the ADC achieves 85.9 dB SFDR and 9.57 ENOB at 210 MS/s. Better than 76 dB SFDR and 9.5 ENOB performance is maintained for input frequency up to 100 MHz. The ADC core power consumption is 140 mW at 1.8 V supply. The active die area of ADC core is 1.5 mm2.
提出了一种基于0.18 um CMOS工艺的1.8 V 10 b 210 MS/s CMOS流水线ADC。在2.5 b/级的流水线ADC架构中，采用opamp共享技术实现了高采样率下的低功耗。通过调节开关驱动方案可以很好地控制opamp的沉降行为。巧妙的电容阵列布置使得在相同系统失配情况下，SFDR性能优越。当输入信号为20 MHz时，该ADC在210 MS/s下可实现85.9 dB SFDR和9.57 ENOB。在高达100mhz的输入频率下，保持76 dB以上的SFDR和9.5的ENOB性能。在1.8 V电源下，ADC核心功耗为140 mW。ADC核心的有效模面积为1.5 mm2。
{"title":"A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration","authors":"J. Li, Robert Leboeuf, M. Courcy, G. Manganaro","doi":"10.1109/CICC.2007.4405742","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405742","url":null,"abstract":"A 1.8 V 10 b 210 MS/s CMOS pipelined ADC in 0.18 um CMOS process is presented. The low power consumption at high sampling rate is achieved by using an opamp-sharing technique in 2.5 b/stage pipelined ADC architecture. The opamp settling behavior is well controlled through a regulated switch driving scheme. The clever arrangement of capacitor array renders superior SFDR for the same given systematic mismatch. With a 20 MHz input signal, the ADC achieves 85.9 dB SFDR and 9.57 ENOB at 210 MS/s. Better than 76 dB SFDR and 9.5 ENOB performance is maintained for input frequency up to 100 MHz. The ADC core power consumption is 140 mW at 1.8 V supply. The active die area of ADC core is 1.5 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121924205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405843
B. Heydari, M. Bohsali, E. Adabi, A. Niknejad
A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P-1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.
{"title":"A 60 GHz Power Amplifier in 90nm CMOS Technology","authors":"B. Heydari, M. Bohsali, E. Adabi, A. Niknejad","doi":"10.1109/CICC.2007.4405843","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405843","url":null,"abstract":"A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P-1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128583108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405757
J. Holleman, B. Otis, C. Diorio
In this paper, we present a new class of charge pump capable of generating voltages 3.75 × greater than the supply in a single clock cycle. It occupies .005 mm2 in a 0.13 μm CMOS process and can operate with a supply voltage between 0.4 V and 1.2 V, or as low as 0.2 V with some pulse-shape distortion. Our charge pump can provide output voltages of up to 3.9 V with less than 10 nW of standby power dissipation.
{"title":"A compact pulse-based charge pump in 0.13 μm CMOS","authors":"J. Holleman, B. Otis, C. Diorio","doi":"10.1109/CICC.2007.4405757","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405757","url":null,"abstract":"In this paper, we present a new class of charge pump capable of generating voltages 3.75 × greater than the supply in a single clock cycle. It occupies .005 mm2 in a 0.13 μm CMOS process and can operate with a supply voltage between 0.4 V and 1.2 V, or as low as 0.2 V with some pulse-shape distortion. Our charge pump can provide output voltages of up to 3.9 V with less than 10 nW of standby power dissipation.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121433848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405726
Jeong-Il Kim, Daeik D. Kim, Jonghae Kim, Choongyeun Cho, B. Jung, D. Peroulis
This paper reports a new strip-patterned integrated inductor that actively engages metal filling rules leading to reduced manufacturing cost and process-induced uncertainties while simultaneously maintaining state-of-the-art performance. The strip-patterned inductor consists of parallel horse shoe-shape metal lines in the foot print of a single-line inductor. It observes back-end-of-line (BEOL) metal density rules by design, and it is not subject to a post-layout patterning to enforce metal density on a large piece of metal. As a result, better model-to-hardware correlation (MHC) is expected. The new inductor structure is backed by experimental and simulated results that demonstrate the design methodology in the presence of process uncertainties typically not known to the circuit designer.
{"title":"Integrated Inductor Actively Engaging Metal Filling Rules","authors":"Jeong-Il Kim, Daeik D. Kim, Jonghae Kim, Choongyeun Cho, B. Jung, D. Peroulis","doi":"10.1109/CICC.2007.4405726","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405726","url":null,"abstract":"This paper reports a new strip-patterned integrated inductor that actively engages metal filling rules leading to reduced manufacturing cost and process-induced uncertainties while simultaneously maintaining state-of-the-art performance. The strip-patterned inductor consists of parallel horse shoe-shape metal lines in the foot print of a single-line inductor. It observes back-end-of-line (BEOL) metal density rules by design, and it is not subject to a post-layout patterning to enforce metal density on a large piece of metal. As a result, better model-to-hardware correlation (MHC) is expected. The new inductor structure is backed by experimental and simulated results that demonstrate the design methodology in the presence of process uncertainties typically not known to the circuit designer.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405741
Ho-Young Lee, Tae-Hwan Oh, Hojin Park, Hae-Seung Lee, M. Spaeth, Jae-Whui Kim
A 14-b 30 MS/s CMOS pipelined ADC is presented. To facilitate digital calibration, a simple 1-b per stage architecture with redundancy is used. The ADC fully integrates digital self-calibration, which performs overall sequence by one flag signal. Implemented in a 90 nm digital CMOS process, the prototype ADC achieves 83.7 dB SFDR and 69.3 dB SNDR with calibration. Its active area is 0.75 mm2 including the on-chip calibration logic and the total power consumes 106 mW with 3.3 V and 1.0 V supply.
{"title":"A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration","authors":"Ho-Young Lee, Tae-Hwan Oh, Hojin Park, Hae-Seung Lee, M. Spaeth, Jae-Whui Kim","doi":"10.1109/CICC.2007.4405741","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405741","url":null,"abstract":"A 14-b 30 MS/s CMOS pipelined ADC is presented. To facilitate digital calibration, a simple 1-b per stage architecture with redundancy is used. The ADC fully integrates digital self-calibration, which performs overall sequence by one flag signal. Implemented in a 90 nm digital CMOS process, the prototype ADC achieves 83.7 dB SFDR and 69.3 dB SNDR with calibration. Its active area is 0.75 mm2 including the on-chip calibration logic and the total power consumes 106 mW with 3.3 V and 1.0 V supply.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114712354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405747
Ivan Bogue, M. Flynn
A digitally calibrated 8-bit folding ADC incorporating redundancy and reassignment is described. Small, redundant folder and comparator circuits generate 1024 available zero-crossings. An entirely self-contained calibration engine selects 255 zero-crossings from the available set. Unselected circuits are powered down. The calibration breaks the link between ADC performance and analog accuracy, allowing small transistors to be used in the signal path. Fabricated in 0.18 μm digital CMOS, the DNL of the uncalibrated ADC is 6.7 LSB and 0.8 LSB, before and after calibration, respectively. SFDR remains above 55 dB up to a sampling rate of 550 MS/s. The total die area is 1.2mm2.
{"title":"A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS","authors":"Ivan Bogue, M. Flynn","doi":"10.1109/CICC.2007.4405747","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405747","url":null,"abstract":"A digitally calibrated 8-bit folding ADC incorporating redundancy and reassignment is described. Small, redundant folder and comparator circuits generate 1024 available zero-crossings. An entirely self-contained calibration engine selects 255 zero-crossings from the available set. Unselected circuits are powered down. The calibration breaks the link between ADC performance and analog accuracy, allowing small transistors to be used in the signal path. Fabricated in 0.18 μm digital CMOS, the DNL of the uncalibrated ADC is 6.7 LSB and 0.8 LSB, before and after calibration, respectively. SFDR remains above 55 dB up to a sampling rate of 550 MS/s. The total die area is 1.2mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114758925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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