Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405780
J. Victory, Zeqin Zhu, Q. Zhou, Wei-Shan Wu, G. Gildenblat, Zhixin Yan, J. Cordovez, C. McAndrew, F. Anderson, J. Paasschens, R. V. Langevelde, P. Kolev, R. Cherne, C. Yao
A physically based scalable model for MOS Varactors is presented. The model includes a PSP-based analytical surface potential charge formulation, MOS varactor specific gate current models, and physical geometry and process parameter based parasitic modeling. Key device performances of capacitance and quality factor Q are validated over voltage, frequency, and geometry, for several technologies. The model, implemented in Verilog-A, provides robust and accurate RF simulation of MOS varactors. A VCO design application is detailed.
{"title":"PSP-Based Scalable MOS Varactor Model","authors":"J. Victory, Zeqin Zhu, Q. Zhou, Wei-Shan Wu, G. Gildenblat, Zhixin Yan, J. Cordovez, C. McAndrew, F. Anderson, J. Paasschens, R. V. Langevelde, P. Kolev, R. Cherne, C. Yao","doi":"10.1109/CICC.2007.4405780","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405780","url":null,"abstract":"A physically based scalable model for MOS Varactors is presented. The model includes a PSP-based analytical surface potential charge formulation, MOS varactor specific gate current models, and physical geometry and process parameter based parasitic modeling. Key device performances of capacitance and quality factor Q are validated over voltage, frequency, and geometry, for several technologies. The model, implemented in Verilog-A, provides robust and accurate RF simulation of MOS varactors. A VCO design application is detailed.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131786320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405732
T. Suttorp, U. Langmann
A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mum CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 times 0.39 mm2. The CDR fulfills the SONET/SDH jitter tolerance requirements at a 231-1 PRBS and a BER of < 10-12. Successful adaptive equalization of a 30 cm (12") and 76 cm (30") channel on standard FR4 substrate is also demonstrated.
{"title":"A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery","authors":"T. Suttorp, U. Langmann","doi":"10.1109/CICC.2007.4405732","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405732","url":null,"abstract":"A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mum CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 times 0.39 mm2. The CDR fulfills the SONET/SDH jitter tolerance requirements at a 231-1 PRBS and a BER of < 10-12. Successful adaptive equalization of a 30 cm (12\") and 76 cm (30\") channel on standard FR4 substrate is also demonstrated.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405818
I. Elahi, K. Muhammad
We present a digital calibration technique for improving IIP2 by injecting DC offset at the mixer. Most receivers offer DC offset cancellation circuitry, and a targeted non-zero DC offset at mixer output is up-converted to RF carrier frequency due to poor reverse isolation of the mixer switch. By controlling amplitude of the injected DC, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis and measurement data for a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process are presented. Calibrated IIP2 of 50 dBm is reported at LNA input.
{"title":"On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless Receiver","authors":"I. Elahi, K. Muhammad","doi":"10.1109/CICC.2007.4405818","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405818","url":null,"abstract":"We present a digital calibration technique for improving IIP2 by injecting DC offset at the mixer. Most receivers offer DC offset cancellation circuitry, and a targeted non-zero DC offset at mixer output is up-converted to RF carrier frequency due to poor reverse isolation of the mixer switch. By controlling amplitude of the injected DC, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis and measurement data for a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process are presented. Calibrated IIP2 of 50 dBm is reported at LNA input.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134321680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405808
R. Topaloglu
Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that enables the exploitation of STI stress for performance improvement of standard cells and custom integrated circuits. We start with process simulation of a 65 nm STI technology, and generate mobility models for STI stress based on these simulations. Based on these models, we are able to perform STI stress-aware modeling and simulation using SPICE. We then present our optimization of STI stress in standard-cell and custom designs using active-layer (dummy) fill insertion to alter the STI widths. Circuit level experimental results are based on a miscellaneous ring oscillator, which is known to correlate well to silicon. Using a generic 65 nm cell library, we show that the STI-optimized designs provide up to 8% improvement in clock frequency. The frequency improvement through exploitation of STI stress comes at practically zero cost with respect to area and wire length.
{"title":"Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization","authors":"R. Topaloglu","doi":"10.1109/CICC.2007.4405808","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405808","url":null,"abstract":"Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that enables the exploitation of STI stress for performance improvement of standard cells and custom integrated circuits. We start with process simulation of a 65 nm STI technology, and generate mobility models for STI stress based on these simulations. Based on these models, we are able to perform STI stress-aware modeling and simulation using SPICE. We then present our optimization of STI stress in standard-cell and custom designs using active-layer (dummy) fill insertion to alter the STI widths. Circuit level experimental results are based on a miscellaneous ring oscillator, which is known to correlate well to silicon. Using a generic 65 nm cell library, we show that the STI-optimized designs provide up to 8% improvement in clock frequency. The frequency improvement through exploitation of STI stress comes at practically zero cost with respect to area and wire length.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405853
Sujiang Rong, H. Luong
A notch-peak cancellation concept is introduced in transformer-based LC tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18 μm CMOS process and operated at 1V supply, the QVCO prototype measures a stable dual-band operation from 3.27 GHz to 5.02 GHz and from 9.48 GHz to 11.36 GHz. At 4.2 GHz and 10 GHz, the QVCO measures phase noise at 1 MHz offset of -116.3 dBc/Hz and -112 dBc/Hz, and sideband rejection ratios (SBR) of 49 dB and 47 dB while drawing 6 mA and 10 mA, respectively. The QVCO occupies an active area of 0.88 mm2.
{"title":"A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOS","authors":"Sujiang Rong, H. Luong","doi":"10.1109/CICC.2007.4405853","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405853","url":null,"abstract":"A notch-peak cancellation concept is introduced in transformer-based LC tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18 μm CMOS process and operated at 1V supply, the QVCO prototype measures a stable dual-band operation from 3.27 GHz to 5.02 GHz and from 9.48 GHz to 11.36 GHz. At 4.2 GHz and 10 GHz, the QVCO measures phase noise at 1 MHz offset of -116.3 dBc/Hz and -112 dBc/Hz, and sideband rejection ratios (SBR) of 49 dB and 47 dB while drawing 6 mA and 10 mA, respectively. The QVCO occupies an active area of 0.88 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405773
Ahmad Darabiha, A. C. Carusone, F. Kschischang
A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.
{"title":"A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS","authors":"Ahmad Darabiha, A. C. Carusone, F. Kschischang","doi":"10.1109/CICC.2007.4405773","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405773","url":null,"abstract":"A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405717
Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang
This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3 MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 mum CMOS process. The active area is 0.11 mm2. With a single 1.2-V power supply, measurement results show that the 55 dB gain, 15 MHz bandwidth limiter and the RSSI consume 1.9 mA. The FSK demodulator part consumes 300 muA.
本文介绍了一种低中频无线FSK接收机的低压低功率限幅器、RSSI和解调器设计。中频位于3mhz。FSK解调器是由一个与数字偏移抵消和修改相频检测技术相关联的延迟锁相环实现的。解调后的数据可以在1时钟延时下恢复。限幅器和RSSI电路均采用伪差分电路，以减小对电压净空的要求。每个增益单元都具有前馈失调抵消和共模稳定电路，可以确保其功能不受器件失配的影响。该芯片采用标准的0.18 μ m CMOS工艺。活动面积为0.11 mm2。在单个1.2 v电源的情况下，测量结果表明55db增益、15mhz带宽限制器和RSSI消耗1.9 mA。FSK解调器部分消耗300mua。
{"title":"A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver","authors":"Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang","doi":"10.1109/CICC.2007.4405717","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405717","url":null,"abstract":"This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3 MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 mum CMOS process. The active area is 0.11 mm2. With a single 1.2-V power supply, measurement results show that the 55 dB gain, 15 MHz bandwidth limiter and the RSSI consume 1.9 mA. The FSK demodulator part consumes 300 muA.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116225344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405761
Yu-Shiang Lin, D. Sylvester, D. Blaauw
In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.
{"title":"A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems","authors":"Yu-Shiang Lin, D. Sylvester, D. Blaauw","doi":"10.1109/CICC.2007.4405761","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405761","url":null,"abstract":"In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405675
Jiajing Wang, B. Calhoun
Canary bitcells act as online monitors in a feedback architecture to sense the proximity to the data retention voltage (DRV) for core SRAM bitcells during standby voltage scaling. This approach implements aggressive standby VDD scaling by tracking PVT variations and gives the flexibility to tradeoff between the safety of data and decreased leakage power. A 90 nm 128 Kb SRAM test chip confirms that the canary cells track changes in temperature and VDD and that they provide a reliable mechanism for protecting core cells in a closed loop VDD scaling system. Power savings improve by up to 30times compared with the conventional guard-banding approach.
{"title":"Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM","authors":"Jiajing Wang, B. Calhoun","doi":"10.1109/CICC.2007.4405675","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405675","url":null,"abstract":"Canary bitcells act as online monitors in a feedback architecture to sense the proximity to the data retention voltage (DRV) for core SRAM bitcells during standby voltage scaling. This approach implements aggressive standby VDD scaling by tracking PVT variations and gives the flexibility to tradeoff between the safety of data and decreased leakage power. A 90 nm 128 Kb SRAM test chip confirms that the canary cells track changes in temperature and VDD and that they provide a reliable mechanism for protecting core cells in a closed loop VDD scaling system. Power savings improve by up to 30times compared with the conventional guard-banding approach.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405729
Simardeep Maangat, Toàn Nguyên, W. Wong, Sergey Shumarayev, T. Tran, T. Hoang, R. Cliff
A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.
{"title":"Receiver Offset Cancellation in 90-nm PLD Integrated SERDES","authors":"Simardeep Maangat, Toàn Nguyên, W. Wong, Sergey Shumarayev, T. Tran, T. Hoang, R. Cliff","doi":"10.1109/CICC.2007.4405729","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405729","url":null,"abstract":"A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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