Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405780
J. Victory, Zeqin Zhu, Q. Zhou, Wei-Shan Wu, G. Gildenblat, Zhixin Yan, J. Cordovez, C. McAndrew, F. Anderson, J. Paasschens, R. V. Langevelde, P. Kolev, R. Cherne, C. Yao
A physically based scalable model for MOS Varactors is presented. The model includes a PSP-based analytical surface potential charge formulation, MOS varactor specific gate current models, and physical geometry and process parameter based parasitic modeling. Key device performances of capacitance and quality factor Q are validated over voltage, frequency, and geometry, for several technologies. The model, implemented in Verilog-A, provides robust and accurate RF simulation of MOS varactors. A VCO design application is detailed.
{"title":"PSP-Based Scalable MOS Varactor Model","authors":"J. Victory, Zeqin Zhu, Q. Zhou, Wei-Shan Wu, G. Gildenblat, Zhixin Yan, J. Cordovez, C. McAndrew, F. Anderson, J. Paasschens, R. V. Langevelde, P. Kolev, R. Cherne, C. Yao","doi":"10.1109/CICC.2007.4405780","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405780","url":null,"abstract":"A physically based scalable model for MOS Varactors is presented. The model includes a PSP-based analytical surface potential charge formulation, MOS varactor specific gate current models, and physical geometry and process parameter based parasitic modeling. Key device performances of capacitance and quality factor Q are validated over voltage, frequency, and geometry, for several technologies. The model, implemented in Verilog-A, provides robust and accurate RF simulation of MOS varactors. A VCO design application is detailed.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131786320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405732
T. Suttorp, U. Langmann
A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mum CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 times 0.39 mm2. The CDR fulfills the SONET/SDH jitter tolerance requirements at a 231-1 PRBS and a BER of < 10-12. Successful adaptive equalization of a 30 cm (12") and 76 cm (30") channel on standard FR4 substrate is also demonstrated.
{"title":"A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery","authors":"T. Suttorp, U. Langmann","doi":"10.1109/CICC.2007.4405732","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405732","url":null,"abstract":"A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mum CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 times 0.39 mm2. The CDR fulfills the SONET/SDH jitter tolerance requirements at a 231-1 PRBS and a BER of < 10-12. Successful adaptive equalization of a 30 cm (12\") and 76 cm (30\") channel on standard FR4 substrate is also demonstrated.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405717
Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang
This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3 MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 mum CMOS process. The active area is 0.11 mm2. With a single 1.2-V power supply, measurement results show that the 55 dB gain, 15 MHz bandwidth limiter and the RSSI consume 1.9 mA. The FSK demodulator part consumes 300 muA.
本文介绍了一种低中频无线FSK接收机的低压低功率限幅器、RSSI和解调器设计。中频位于3mhz。FSK解调器是由一个与数字偏移抵消和修改相频检测技术相关联的延迟锁相环实现的。解调后的数据可以在1时钟延时下恢复。限幅器和RSSI电路均采用伪差分电路，以减小对电压净空的要求。每个增益单元都具有前馈失调抵消和共模稳定电路，可以确保其功能不受器件失配的影响。该芯片采用标准的0.18 μ m CMOS工艺。活动面积为0.11 mm2。在单个1.2 v电源的情况下，测量结果表明55db增益、15mhz带宽限制器和RSSI消耗1.9 mA。FSK解调器部分消耗300mua。
{"title":"A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver","authors":"Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang","doi":"10.1109/CICC.2007.4405717","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405717","url":null,"abstract":"This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3 MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 mum CMOS process. The active area is 0.11 mm2. With a single 1.2-V power supply, measurement results show that the 55 dB gain, 15 MHz bandwidth limiter and the RSSI consume 1.9 mA. The FSK demodulator part consumes 300 muA.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116225344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405761
Yu-Shiang Lin, D. Sylvester, D. Blaauw
In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.
{"title":"A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems","authors":"Yu-Shiang Lin, D. Sylvester, D. Blaauw","doi":"10.1109/CICC.2007.4405761","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405761","url":null,"abstract":"In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405821
Hua Wang, A. Hajimiri
This paper presents a 10-bit wideband Cartesian phase rotator with a novel linear digital VGA implemented in a 0.13 um CMOS process. The VGA topology is robust to device modeling uncertainties and PVT variations. The system provides 7.8 dB voltage gain with -3 dB bandwidth of 7.6 GHz. A maximum phase error of 2deg has been achieved for a phase shifting range of 360deg with 32 phase steps of 11.25deg. The capability to compensate for mismatched quadrature inputs is also demonstrated.
本文提出了一种采用0.13 um CMOS工艺实现的10位宽带笛卡尔相位旋转器，该旋转器具有新颖的线性数字VGA。VGA拓扑对器件建模不确定性和PVT变化具有鲁棒性。系统提供7.8 dB电压增益，-3 dB带宽为7.6 GHz。当相移范围为360°，32个相移步为11.25°时，最大相位误差为2°。补偿不匹配正交输入的能力也得到了证明。
{"title":"A Wideband CMOS Linear Digital Phase Rotator","authors":"Hua Wang, A. Hajimiri","doi":"10.1109/CICC.2007.4405821","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405821","url":null,"abstract":"This paper presents a 10-bit wideband Cartesian phase rotator with a novel linear digital VGA implemented in a 0.13 um CMOS process. The VGA topology is robust to device modeling uncertainties and PVT variations. The system provides 7.8 dB voltage gain with -3 dB bandwidth of 7.6 GHz. A maximum phase error of 2deg has been achieved for a phase shifting range of 360deg with 32 phase steps of 11.25deg. The capability to compensate for mismatched quadrature inputs is also demonstrated.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"40 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124612069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405729
Simardeep Maangat, Toàn Nguyên, W. Wong, Sergey Shumarayev, T. Tran, T. Hoang, R. Cliff
A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.
{"title":"Receiver Offset Cancellation in 90-nm PLD Integrated SERDES","authors":"Simardeep Maangat, Toàn Nguyên, W. Wong, Sergey Shumarayev, T. Tran, T. Hoang, R. Cliff","doi":"10.1109/CICC.2007.4405729","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405729","url":null,"abstract":"A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405833
D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare
The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
PA6T核心是该电源架构的无序超标量实现。功率效率是通过微架构、逻辑和电路优化实现的。该处理器采用65nm，三Vt，双氧化物8 M CMOS工艺制造。2ghz时最坏功耗为7w。
{"title":"A 2GHz, 7W (max) 64b PowerTM Microprocessor Core","authors":"D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare","doi":"10.1109/CICC.2007.4405833","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405833","url":null,"abstract":"The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131238228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405714
R. Yu, Y. Xu
A 4th-order bandpass ΣΔ modulator employing electromechanical filter as loop filter is proposed. The electromechanical loop filter has the advantages of low power consumption and accurate center frequency without the need for tuning. The proposed bandpass SigmaDelta modulator is implemented in a 0.35-μm SiGe BiCMOS technology and tested with a 110-MHz SAW filter. When sampled at 440 MHz, the prototype chip achieves 65-dB DR and 60-dB peak SNDR in a 1-MHz signal bandwidth.
{"title":"A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filter","authors":"R. Yu, Y. Xu","doi":"10.1109/CICC.2007.4405714","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405714","url":null,"abstract":"A 4th-order bandpass ΣΔ modulator employing electromechanical filter as loop filter is proposed. The electromechanical loop filter has the advantages of low power consumption and accurate center frequency without the need for tuning. The proposed bandpass SigmaDelta modulator is implemented in a 0.35-μm SiGe BiCMOS technology and tested with a 110-MHz SAW filter. When sampled at 440 MHz, the prototype chip achieves 65-dB DR and 60-dB peak SNDR in a 1-MHz signal bandwidth.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405675
Jiajing Wang, B. Calhoun
Canary bitcells act as online monitors in a feedback architecture to sense the proximity to the data retention voltage (DRV) for core SRAM bitcells during standby voltage scaling. This approach implements aggressive standby VDD scaling by tracking PVT variations and gives the flexibility to tradeoff between the safety of data and decreased leakage power. A 90 nm 128 Kb SRAM test chip confirms that the canary cells track changes in temperature and VDD and that they provide a reliable mechanism for protecting core cells in a closed loop VDD scaling system. Power savings improve by up to 30times compared with the conventional guard-banding approach.
{"title":"Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM","authors":"Jiajing Wang, B. Calhoun","doi":"10.1109/CICC.2007.4405675","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405675","url":null,"abstract":"Canary bitcells act as online monitors in a feedback architecture to sense the proximity to the data retention voltage (DRV) for core SRAM bitcells during standby voltage scaling. This approach implements aggressive standby VDD scaling by tracking PVT variations and gives the flexibility to tradeoff between the safety of data and decreased leakage power. A 90 nm 128 Kb SRAM test chip confirms that the canary cells track changes in temperature and VDD and that they provide a reliable mechanism for protecting core cells in a closed loop VDD scaling system. Power savings improve by up to 30times compared with the conventional guard-banding approach.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405796
L. Clark, M. Kabir, J. Knudsen
A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.
{"title":"A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity","authors":"L. Clark, M. Kabir, J. Knudsen","doi":"10.1109/CICC.2007.4405796","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405796","url":null,"abstract":"A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126478041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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