Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405700
Kazuhiro Yamamoto, M. Suda, T. Okayasu
A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.
介绍了一种采用0.18 μ m CMOS工艺制作的差分时间-数字转换器(TDC)，用于源同步器件测试。它的最大采样率为2.133 GS/s，可变分辨率为10-40 ps，测量范围无限，INL为8.5 ps(pk-pk)，抖动为18.3 ps(pk-pk)。它可以应用于无死区时间的抖动直方图测量，因为它连续检测所有的过渡时间。此外，本文还提出了将该TDC应用于ADC或DAC的可能性。
{"title":"2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device","authors":"Kazuhiro Yamamoto, M. Suda, T. Okayasu","doi":"10.1109/CICC.2007.4405700","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405700","url":null,"abstract":"A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125460916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405845
Larry Bair
The interactions between VLSI processes and the products built in them continue to perplex those who design and those who manufacture semiconductor chips. Predicting, preventing, and minimizing these interactions is compounded by attempts to minimize time-to-market through concurrent process and design development in integrated design and manufacturing environments. Past experience, engineering conservatism, and flexible design techniques enable successful concurrent deep submicron CMOS VLSI designs.
{"title":"Process/Product Interactions in a Concurrent Design Environment","authors":"Larry Bair","doi":"10.1109/CICC.2007.4405845","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405845","url":null,"abstract":"The interactions between VLSI processes and the products built in them continue to perplex those who design and those who manufacture semiconductor chips. Predicting, preventing, and minimizing these interactions is compounded by attempts to minimize time-to-market through concurrent process and design development in integrated design and manufacturing environments. Past experience, engineering conservatism, and flexible design techniques enable successful concurrent deep submicron CMOS VLSI designs.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126934187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405681
Takaya Yamamoto, M. Kasahara, T. Matsuura
We developed a 10.7-MHz intermediate frequency (IF) bandpass discrete-time (DT) 4th -order 4-bit ΔΣ modulator for AM/FM car radio tuners. Using direct feed-forward and double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3-kHz AM bandwidth (BW) and a DR of 94 dB in the 200-kHz FM BW. The modulator occupies 3 mm2, in 0.15 μm CMOS technology, and draws 63 mA of current.
{"title":"A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling","authors":"Takaya Yamamoto, M. Kasahara, T. Matsuura","doi":"10.1109/CICC.2007.4405681","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405681","url":null,"abstract":"We developed a 10.7-MHz intermediate frequency (IF) bandpass discrete-time (DT) 4<sup>th</sup> -order 4-bit ΔΣ modulator for AM/FM car radio tuners. Using direct feed-forward and double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3-kHz AM bandwidth (BW) and a DR of 94 dB in the 200-kHz FM BW. The modulator occupies 3 mm<sup>2</sup>, in 0.15 μm CMOS technology, and draws 63 mA of current.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405767
R. Torrance, D. James
The intent of this paper is to give an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products. The continuous drive of Moore's law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns and demanding the adopted of new and more sophisticated technology to analyse chips. This trend is continuing; the 2006 update of the International Technology Roadmap for Semiconductors is predicting the shrinkage of transistor gates from the current 65-nm generation to 16 nm at the turn of the decade, and the usage of over 1.5 billion transistors in high-volume microprocessor chips. The paper covers product teardowns, and discusses the techniques used for system-level analysis, both hardware and software; circuit extraction, taking the chip down to the transistor level and working back up through the interconnects to create schematics; and process analysis, looking at how a chip is made, and what it is made of. Examples are also given of each type of RE.
{"title":"Reverse Engineering in the Semiconductor Industry","authors":"R. Torrance, D. James","doi":"10.1109/CICC.2007.4405767","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405767","url":null,"abstract":"The intent of this paper is to give an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products. The continuous drive of Moore's law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns and demanding the adopted of new and more sophisticated technology to analyse chips. This trend is continuing; the 2006 update of the International Technology Roadmap for Semiconductors is predicting the shrinkage of transistor gates from the current 65-nm generation to 16 nm at the turn of the decade, and the usage of over 1.5 billion transistors in high-volume microprocessor chips. The paper covers product teardowns, and discusses the techniques used for system-level analysis, both hardware and software; circuit extraction, taking the chip down to the transistor level and working back up through the interconnects to create schematics; and process analysis, looking at how a chip is made, and what it is made of. Examples are also given of each type of RE.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405706
Edward K. F. Lee, P. Hess, John Gord, Howard Stover, P. Nercessian
A 2.5 MB/s, 400 MHz RF transceiver was design for implantable biomedical micro-stimulators in a 0.18 mum CMOS process. It consists of a transmitter with an output power of -4.5 dBm and a receiver that can detect input signal at < -95 dBm. When one time slot of 6us in a -llrns data frame is used, the transceiver has an effective bit rate of 1.36 kB/s, and consumes ~23 muA for receive and ~8 muA for transmit from a 3.6 V battery. The total number of stimulators that the system can support is 852.
{"title":"A 400MHz RF Transceiver for Implantable Biomedical Micro-Stimulators","authors":"Edward K. F. Lee, P. Hess, John Gord, Howard Stover, P. Nercessian","doi":"10.1109/CICC.2007.4405706","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405706","url":null,"abstract":"A 2.5 MB/s, 400 MHz RF transceiver was design for implantable biomedical micro-stimulators in a 0.18 mum CMOS process. It consists of a transmitter with an output power of -4.5 dBm and a receiver that can detect input signal at < -95 dBm. When one time slot of 6us in a -llrns data frame is used, the transceiver has an effective bit rate of 1.36 kB/s, and consumes ~23 muA for receive and ~8 muA for transmit from a 3.6 V battery. The total number of stimulators that the system can support is 852.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405857
Y. Nishikawa, S. Kawahito, M. Furuta, Toshihiro Tamura
This paper presents a high-speed CMOS image sensor with on-chip parallel image compression circuits. The chip consists of a pixel array, an A/D converter array with noise canceling function and an image compression processing element array and buffer memories. The image compression processing element is implemented with a 4times4 point discreate cosine transform(DCT) and a modified zigzag scanner with 4 blocks. A prototype high-speed CMOS image sensor integrating the image compression circuits is implemented based on 1-poly 5-metal 0.25-mum CMOS technology. Image encoding using the implemented parallel image compression circuits to the image captured by the high-speed image sensor is successfully performed at 3,000[frame/s].
{"title":"A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits","authors":"Y. Nishikawa, S. Kawahito, M. Furuta, Toshihiro Tamura","doi":"10.1109/CICC.2007.4405857","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405857","url":null,"abstract":"This paper presents a high-speed CMOS image sensor with on-chip parallel image compression circuits. The chip consists of a pixel array, an A/D converter array with noise canceling function and an image compression processing element array and buffer memories. The image compression processing element is implemented with a 4times4 point discreate cosine transform(DCT) and a modified zigzag scanner with 4 blocks. A prototype high-speed CMOS image sensor integrating the image compression circuits is implemented based on 1-poly 5-metal 0.25-mum CMOS technology. Image encoding using the implemented parallel image compression circuits to the image captured by the high-speed image sensor is successfully performed at 3,000[frame/s].","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125052009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405713
Marc Keppler, D. Thelen
This paper presents a first order noise shaped dynamic element matching (DEM) algorithm. The DEM algorithm was developed to improve the signal-to-noise and distortion ratio (SNDR) of a delta-sigma analog to digital converter (ADC). However, it can be applied to any system utilizing averaging and a plurality of unit components. Matlab simulations have shown that the presented algorithm eliminates idle-tones and provides almost a 30dB improvement in SNDR in a second order delta-sigma ADC.
{"title":"An Idle-Tone Free Dynamic Element Matching Algorithm","authors":"Marc Keppler, D. Thelen","doi":"10.1109/CICC.2007.4405713","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405713","url":null,"abstract":"This paper presents a first order noise shaped dynamic element matching (DEM) algorithm. The DEM algorithm was developed to improve the signal-to-noise and distortion ratio (SNDR) of a delta-sigma analog to digital converter (ADC). However, it can be applied to any system utilizing averaging and a plurality of unit components. Matlab simulations have shown that the presented algorithm eliminates idle-tones and provides almost a 30dB improvement in SNDR in a second order delta-sigma ADC.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123332268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405819
T. Umeda, S. Otaka
ECO chip (energy consumption zeroize chip) for standby mode applications is presented. ECO chip detects 953 MHz band radio waves from a remote control using a high-sensitivity rectifier and switches on/off the main power supplies of applications with ultra-low power consumption. Sensitivity of -42 dBm and communication distance of 10 m from 13 dBm output remote control are achieved with 0.14 muW power consumption.
{"title":"ECO chip: Energy Consumption Zeroize Chip with a 953MHz High-Sensitivity Radio Wave Detector for Standby Mode Applications","authors":"T. Umeda, S. Otaka","doi":"10.1109/CICC.2007.4405819","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405819","url":null,"abstract":"ECO chip (energy consumption zeroize chip) for standby mode applications is presented. ECO chip detects 953 MHz band radio waves from a remote control using a high-sensitivity rectifier and switches on/off the main power supplies of applications with ultra-low power consumption. Sensitivity of -42 dBm and communication distance of 10 m from 13 dBm output remote control are achieved with 0.14 muW power consumption.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126329232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405779
Moon-Jung Kim, Henrik Icking, H. Gossner, T. Lee
We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.
{"title":"High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications","authors":"Moon-Jung Kim, Henrik Icking, H. Gossner, T. Lee","doi":"10.1109/CICC.2007.4405779","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405779","url":null,"abstract":"We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131787179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405772
Ruwan N. S. Ratnayake, A. Kavcic, Gu-Yeon Wei
This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo decoding, can approach performance close to the channel capacity limit. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 MHz while consuming 2.4 W. The detector is implemented in a 0.13mum CMOS technology and has a die area of 9.9 mm2.
本文提出了一种基于前向算法的最大后验概率检测器(MAP)，可以实现高吞吐量。MAP算法在误码率(BER)性能方面是最优的，并且通过Turbo解码，可以接近信道容量限制的性能。该检测器采用了一种深流水线架构，实现了耐斜多米诺骨牌，实验测量结果验证了检测器在消耗2.4 W的情况下可以实现大于750 MHz的吞吐量。该探测器采用0.13 mm CMOS技术，芯片面积为9.9 mm2。
{"title":"A High-Throughput Maximum a posteriori Probability Detector","authors":"Ruwan N. S. Ratnayake, A. Kavcic, Gu-Yeon Wei","doi":"10.1109/CICC.2007.4405772","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405772","url":null,"abstract":"This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo decoding, can approach performance close to the channel capacity limit. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 MHz while consuming 2.4 W. The detector is implemented in a 0.13mum CMOS technology and has a die area of 9.9 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123363841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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