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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.最新文献

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Carbon nanotube interconnects: implications for performance, power dissipation and thermal management 碳纳米管互连:对性能、功耗和热管理的影响
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609320
N. Srivastava, R. Joshi, K. Banerjee
This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%
本文从对VLSI电路至关重要的各个方面(性能、功耗和可靠性)对碳纳米管束互连进行了全面评估,同时考虑到该技术的实际局限性。建立了一种新的碳纳米管束互连的延迟模型,利用该模型表明,碳纳米管束可以显著提高长全局互连的性能,并且具有最小的额外功耗(对于最大的金属碳纳米管密度)。虽然众所周知,碳纳米管束互连可以携带比铜高得多的电流密度,但它们对后端热管理和互连温升的影响在这里首次提出。研究表明,使用集成铜互连的碳纳米管束通孔可以将铜互连寿命提高两个数量级,并将最佳全局互连延迟降低多达30%
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引用次数: 87
Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018 到2018年,超薄体完全耗尽SOI金属源/漏n- mosfet和ITRS低备用功率目标
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609524
Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp
Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height
利用2006年至2018年与ITRS LSTP目标相关的参数,对金属(肖特基)源/漏(S/D)超薄体完全耗尽SOI n沟道mosfet(单栅极和双栅极)进行了模拟。通过优化给定S/D势垒高度的S/D对通道的覆盖,可以减少断流,以匹配每年的ITRS LSTP规范。然后ITRS通流目标建立S/D障碍高度的限制
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引用次数: 15
Performance evaluation of 50 nm In/sub 0.7/Ga/sub 0.3/As HEMTs for beyond-CMOS logic applications 用于超cmos逻辑应用的50nm In/sub 0.7/Ga/sub 0.3/As hemt性能评估
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609467
Daehyun Kim, J. D. del Alamo, Jaehak Lee, K. Seo
We have studied the suitability of nanometer-scale In0.7Ga0.3As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In0.7Ga0.3As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit ION/IOFF ratios in excess of 105 and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFETs, the non-optimized 50 nm In0.7Ga0.3As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher fT at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise
我们已经研究了纳米级In0.7Ga0.3As hemt作为超cmos应用的高速,低功耗逻辑技术的适用性。为此,我们制作了50- 150nm栅极长度的In0.7Ga0.3As hemt,并采用不同的栅极堆叠设计。50 nm HEMTs表现出离子/IOFF比超过105,DIBL小于90 mV/dec。与最先进的Si mosfet相比,未经优化的50 nm In0.7Ga0.3As hemt提供了等效的高速性能,其直流功耗降低了15倍,等效功耗水平下的fT至少提高了2.7倍。在CMOS技术之外的替代方案中,富含inas的InGaAs hemt具有相当大的前景
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引用次数: 27
Non-linearity cancellation in MEMS resonators for improved power-handling MEMS谐振器的非线性消除以改善功率处理
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609330
M. Agarwal, K. Park, R. Candler, M. Hopcroft, C. Jha, R. Melamud, B. Kim, B. Murmann, T. Kenny
In this work, we present mathematical analysis and experimental verification of the bifurcation limited power handling in MEMS resonators. We report useful cancellation between electrical and mechanical non-linearities. Within the scaling limits it has been found that the power handling improves for devices with larger electrode to resonator gaps. We also report an alternative method of measuring critical bifurcation using shifts in resonant frequency
在这项工作中,我们对MEMS谐振器中的分岔限制功率处理进行了数学分析和实验验证。我们报告了电非线性和机械非线性之间有用的消去。在标度限制内,对于电极与谐振腔间隙较大的器件,功率处理得到改善。我们还报告了一种利用谐振频率的位移测量临界分岔的替代方法
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引用次数: 33
Moderately doped channel multiple-finFET for logic applications 用于逻辑应用的适度掺杂通道多finet
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609525
Y. Shiho, D. Burnett, M. Orlowski, J. Mogab
In this paper, moderately doped channel (MDC) multiple-FinFET is proposed and its electrical characteristics are investigated using 3D process and device, and 2D mixed-mode device and circuit simulation. It is shown that the MDC offers a better immunity to variations of the fin profile than the undoped channel for a short channel device, and Multiple-FinFET is critical for logic applications. The implementation of an asymmetrical doping profile further improves the performance of MDC Multiple-FinFET
本文提出了一种中等掺杂通道(MDC)多finfet,并利用三维工艺和器件、二维混合模式器件和电路仿真对其电学特性进行了研究。结果表明,对于短通道器件,MDC提供了比未掺杂通道更好的抗翅片形状变化的能力,并且多finfet对于逻辑应用至关重要。不对称掺杂轮廓的实现进一步提高了MDC多finfet的性能
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引用次数: 7
Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor 悬浮栅MOSFET:将新的MEMS功能带入固态MOS晶体管
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609384
N. Abelé, R. Fritschi, K. Boucart, F. Casset, P. Ancey, A. Ionescu
Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05-10
参考文献nanolab - conf -2005-019查看Web of Science record中创建时间为2007-05-16,修改时间为2017-05-10的记录
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引用次数: 176
Monolithic integration of enhancement-and depletion-mode AlGaN/GaN HEMTs for GaN digital integrated circuits 用于GaN数字集成电路的增强和耗尽模式AlGaN/GaN hemt的单片集成
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609468
Yong Cai, Z. Cheng, W.C.-W. Tang, Kevin J. Chen, K. Lau
We demonstrate a novel technique for monolithic integration of enhancement and depletion-mode AlGaN/GaN HEMTs using CF4 plasma treatment. Direct-coupled FET logic circuits such as an E/D HEMT inverter and a 17-stage ring oscillator are demonstrated in GaN system for the first time. At a supply voltage (VDD)of 1.5V, the fabricated E/D inverter shows an output logic swing of 1.25V, logic-low noise margin of 0.21V and logic-high noise margin of 0.51V. The fabricated ring oscillator shows a minimum delay of 130 ps/stage at V DD = 3.5 V, and a minimum power-delay product of 0.113 pJ/stage at VDD = 1 V
我们展示了一种使用CF4等离子体处理增强和耗尽模式AlGaN/GaN hemt的单片集成新技术。本文首次在GaN系统中演示了直接耦合FET逻辑电路,如E/D HEMT逆变器和17级环形振荡器。在电源电压(VDD)为1.5V时,所制备的E/D逆变器的输出逻辑摆幅为1.25V,逻辑低噪声裕度为0.21V,逻辑高噪声裕度为0.51V。所制备的环形振荡器在VDD = 3.5 V时的最小延迟为130 ps/级,在VDD = 1 V时的最小功率延迟积为0.113 pJ/级
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引用次数: 23
Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application 用于后nand存储应用的多层交叉点二元氧化物电阻存储器(OxRRAM)
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609462
I. Baek, D. Kim, M. Lee, H. Kim, E. Yim, M.S. Lee, J. Lee, S. Ahn, S. Seo, J. Lee, J.C. Park, Y. Cha, S.O. Park, H. Kim, I. Yoo, U. Chung, J. Moon, B. Ryu
Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array
对多层交叉点结构二元氧化物电阻存储器(OxRRAM)在下一代非易失性随机存取高密度数据存储中的可行性进行了测试。新型插头触点型底电极(plug- be)可将有源记忆电池直径减小至50nm,且工作电流更小,开关分布更好。有了2个额外的掩模,一层plug-BE包含的交叉点存储阵列可以添加到另一层的顶部。未观察到层间干扰的信号。此外,为了抑制交叉点存储阵列的层内干扰,还制作了基于二元氧化物的原型二极管
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引用次数: 221
Performance and limitations of 65 nm CMOS for integrated RF power applications 集成射频电源应用中65nm CMOS的性能和限制
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609353
J. Scholvin, D. Greenberg, J. D. del Alamo
In this study, we present the first measurements of the RF power performance of 65 nm CMOS for different voltages and layouts. We demonstrate that the 65 nm technology node is capable of achieving PAE values greater than 50% at 8 GHz, with Pout scalable to about 17 dBm. This is of interest for many applications. Greater performance is expected by optimizing the layout to minimize interconnect resistance
在这项研究中,我们首次测量了65nm CMOS在不同电压和布局下的射频功率性能。我们证明了65nm技术节点能够在8ghz下实现大于50%的PAE值,Pout可扩展到约17dbm。这是许多应用程序都感兴趣的。通过优化布局以最小化互连电阻,期望获得更高的性能
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引用次数: 15
8-watt GaN HEMTs at millimeter-wave frequencies 毫米波频率的8瓦GaN hemt
Pub Date : 2005-12-05 DOI: 10.1109/IEDM.2005.1609414
Y. Wu, M. Moore, A. Saxler, T. Wisleder, U. Mishra, P. Parikh
Field-plated short-gate-length GaN HEMTs were developed for superior large-signal performance at millimeter-wave frequencies. 100-mum-wide devices achieved 8.6 W/mm power density at 40 GHz. Scaled-up, pre-matched 1.05-mm-wide devices generated 5.4 & 5.2 W output power with associated PAE of 36 & 31 % at 30 and 35 GHz, respectively. A 1.5-mm-wide device produced 8 W at 30 GHz with 31 % PAE, representing the state-of-the-art for GaN HEMTs at millimeter-wave frequencies
为了在毫米波频率下具有优异的大信号性能,开发了场镀短栅长的GaN hemt。100毫米宽的器件在40 GHz时实现了8.6 W/mm的功率密度。放大后,预先匹配的1.05 mm宽器件在30 GHz和35 GHz下分别产生5.4和5.2 W输出功率,相关PAE分别为36%和31%。一个1.5 mm宽的器件在30 GHz下产生8 W, PAE为31%,代表了毫米波频率下GaN hemt的最新技术
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引用次数: 34
期刊
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
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