Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609320
N. Srivastava, R. Joshi, K. Banerjee
This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%
{"title":"Carbon nanotube interconnects: implications for performance, power dissipation and thermal management","authors":"N. Srivastava, R. Joshi, K. Banerjee","doi":"10.1109/IEDM.2005.1609320","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609320","url":null,"abstract":"This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"9 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80074334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609524
Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp
Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height
{"title":"Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018","authors":"Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp","doi":"10.1109/IEDM.2005.1609524","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609524","url":null,"abstract":"Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"972-975"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90376205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609467
Daehyun Kim, J. D. del Alamo, Jaehak Lee, K. Seo
We have studied the suitability of nanometer-scale In0.7Ga0.3As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In0.7Ga0.3As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit ION/IOFF ratios in excess of 105 and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFETs, the non-optimized 50 nm In0.7Ga0.3As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher fT at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise
{"title":"Performance evaluation of 50 nm In/sub 0.7/Ga/sub 0.3/As HEMTs for beyond-CMOS logic applications","authors":"Daehyun Kim, J. D. del Alamo, Jaehak Lee, K. Seo","doi":"10.1109/IEDM.2005.1609467","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609467","url":null,"abstract":"We have studied the suitability of nanometer-scale In<sub>0.7</sub>Ga<sub>0.3</sub>As HEMTs as a high-speed, low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50-150 nm gate length In<sub>0.7</sub>Ga<sub>0.3</sub>As HEMTs with different gate stack designs. The 50 nm HEMTs exhibit I<sub>ON</sub>/I<sub>OFF</sub> ratios in excess of 10<sup>5</sup> and DIBL less than 90 mV/dec. Compared with state-of-the-art Si MOSFETs, the non-optimized 50 nm In<sub>0.7</sub>Ga<sub>0.3</sub>As HEMTs provide equivalent highspeed performance with 15 times lower DC power dissipation and at least 2.7 times higher f<sub>T</sub> at equivalent power dissipation level. In the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"82 1","pages":"767-770"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88597958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609330
M. Agarwal, K. Park, R. Candler, M. Hopcroft, C. Jha, R. Melamud, B. Kim, B. Murmann, T. Kenny
In this work, we present mathematical analysis and experimental verification of the bifurcation limited power handling in MEMS resonators. We report useful cancellation between electrical and mechanical non-linearities. Within the scaling limits it has been found that the power handling improves for devices with larger electrode to resonator gaps. We also report an alternative method of measuring critical bifurcation using shifts in resonant frequency
{"title":"Non-linearity cancellation in MEMS resonators for improved power-handling","authors":"M. Agarwal, K. Park, R. Candler, M. Hopcroft, C. Jha, R. Melamud, B. Kim, B. Murmann, T. Kenny","doi":"10.1109/IEDM.2005.1609330","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609330","url":null,"abstract":"In this work, we present mathematical analysis and experimental verification of the bifurcation limited power handling in MEMS resonators. We report useful cancellation between electrical and mechanical non-linearities. Within the scaling limits it has been found that the power handling improves for devices with larger electrode to resonator gaps. We also report an alternative method of measuring critical bifurcation using shifts in resonant frequency","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"65 3 1","pages":"286-289"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83285778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609525
Y. Shiho, D. Burnett, M. Orlowski, J. Mogab
In this paper, moderately doped channel (MDC) multiple-FinFET is proposed and its electrical characteristics are investigated using 3D process and device, and 2D mixed-mode device and circuit simulation. It is shown that the MDC offers a better immunity to variations of the fin profile than the undoped channel for a short channel device, and Multiple-FinFET is critical for logic applications. The implementation of an asymmetrical doping profile further improves the performance of MDC Multiple-FinFET
{"title":"Moderately doped channel multiple-finFET for logic applications","authors":"Y. Shiho, D. Burnett, M. Orlowski, J. Mogab","doi":"10.1109/IEDM.2005.1609525","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609525","url":null,"abstract":"In this paper, moderately doped channel (MDC) multiple-FinFET is proposed and its electrical characteristics are investigated using 3D process and device, and 2D mixed-mode device and circuit simulation. It is shown that the MDC offers a better immunity to variations of the fin profile than the undoped channel for a short channel device, and Multiple-FinFET is critical for logic applications. The implementation of an asymmetrical doping profile further improves the performance of MDC Multiple-FinFET","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"60 1","pages":"976-979"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73446971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609384
N. Abelé, R. Fritschi, K. Boucart, F. Casset, P. Ancey, A. Ionescu
Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05-10
参考文献nanolab - conf -2005-019查看Web of Science record中创建时间为2007-05-16，修改时间为2017-05-10的记录
{"title":"Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor","authors":"N. Abelé, R. Fritschi, K. Boucart, F. Casset, P. Ancey, A. Ionescu","doi":"10.1109/IEDM.2005.1609384","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609384","url":null,"abstract":"Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05-10","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"157 1","pages":"479-481"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73448961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609468
Yong Cai, Z. Cheng, W.C.-W. Tang, Kevin J. Chen, K. Lau
We demonstrate a novel technique for monolithic integration of enhancement and depletion-mode AlGaN/GaN HEMTs using CF4 plasma treatment. Direct-coupled FET logic circuits such as an E/D HEMT inverter and a 17-stage ring oscillator are demonstrated in GaN system for the first time. At a supply voltage (VDD)of 1.5V, the fabricated E/D inverter shows an output logic swing of 1.25V, logic-low noise margin of 0.21V and logic-high noise margin of 0.51V. The fabricated ring oscillator shows a minimum delay of 130 ps/stage at V DD = 3.5 V, and a minimum power-delay product of 0.113 pJ/stage at VDD = 1 V
{"title":"Monolithic integration of enhancement-and depletion-mode AlGaN/GaN HEMTs for GaN digital integrated circuits","authors":"Yong Cai, Z. Cheng, W.C.-W. Tang, Kevin J. Chen, K. Lau","doi":"10.1109/IEDM.2005.1609468","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609468","url":null,"abstract":"We demonstrate a novel technique for monolithic integration of enhancement and depletion-mode AlGaN/GaN HEMTs using CF4 plasma treatment. Direct-coupled FET logic circuits such as an E/D HEMT inverter and a 17-stage ring oscillator are demonstrated in GaN system for the first time. At a supply voltage (VDD)of 1.5V, the fabricated E/D inverter shows an output logic swing of 1.25V, logic-low noise margin of 0.21V and logic-high noise margin of 0.51V. The fabricated ring oscillator shows a minimum delay of 130 ps/stage at V DD = 3.5 V, and a minimum power-delay product of 0.113 pJ/stage at VDD = 1 V","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"48 1","pages":"4 pp.-774"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83946515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609462
I. Baek, D. Kim, M. Lee, H. Kim, E. Yim, M.S. Lee, J. Lee, S. Ahn, S. Seo, J. Lee, J.C. Park, Y. Cha, S.O. Park, H. Kim, I. Yoo, U. Chung, J. Moon, B. Ryu
Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array
{"title":"Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application","authors":"I. Baek, D. Kim, M. Lee, H. Kim, E. Yim, M.S. Lee, J. Lee, S. Ahn, S. Seo, J. Lee, J.C. Park, Y. Cha, S.O. Park, H. Kim, I. Yoo, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2005.1609462","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609462","url":null,"abstract":"Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"11 8 1","pages":"750-753"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78388593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609353
J. Scholvin, D. Greenberg, J. D. del Alamo
In this study, we present the first measurements of the RF power performance of 65 nm CMOS for different voltages and layouts. We demonstrate that the 65 nm technology node is capable of achieving PAE values greater than 50% at 8 GHz, with Pout scalable to about 17 dBm. This is of interest for many applications. Greater performance is expected by optimizing the layout to minimize interconnect resistance
{"title":"Performance and limitations of 65 nm CMOS for integrated RF power applications","authors":"J. Scholvin, D. Greenberg, J. D. del Alamo","doi":"10.1109/IEDM.2005.1609353","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609353","url":null,"abstract":"In this study, we present the first measurements of the RF power performance of 65 nm CMOS for different voltages and layouts. We demonstrate that the 65 nm technology node is capable of achieving PAE values greater than 50% at 8 GHz, with Pout scalable to about 17 dBm. This is of interest for many applications. Greater performance is expected by optimizing the layout to minimize interconnect resistance","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"224 1","pages":"369-372"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74445796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609414
Y. Wu, M. Moore, A. Saxler, T. Wisleder, U. Mishra, P. Parikh
Field-plated short-gate-length GaN HEMTs were developed for superior large-signal performance at millimeter-wave frequencies. 100-mum-wide devices achieved 8.6 W/mm power density at 40 GHz. Scaled-up, pre-matched 1.05-mm-wide devices generated 5.4 & 5.2 W output power with associated PAE of 36 & 31 % at 30 and 35 GHz, respectively. A 1.5-mm-wide device produced 8 W at 30 GHz with 31 % PAE, representing the state-of-the-art for GaN HEMTs at millimeter-wave frequencies
{"title":"8-watt GaN HEMTs at millimeter-wave frequencies","authors":"Y. Wu, M. Moore, A. Saxler, T. Wisleder, U. Mishra, P. Parikh","doi":"10.1109/IEDM.2005.1609414","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609414","url":null,"abstract":"Field-plated short-gate-length GaN HEMTs were developed for superior large-signal performance at millimeter-wave frequencies. 100-mum-wide devices achieved 8.6 W/mm power density at 40 GHz. Scaled-up, pre-matched 1.05-mm-wide devices generated 5.4 & 5.2 W output power with associated PAE of 36 & 31 % at 30 and 35 GHz, respectively. A 1.5-mm-wide device produced 8 W at 30 GHz with 31 % PAE, representing the state-of-the-art for GaN HEMTs at millimeter-wave frequencies","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"114 1","pages":"583-585"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77140475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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