Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609290
H. Wakabayashi, T. Tatsumi, N. Ikarashi, M. Oshida, H. Kawamoto, N. Ikezawa, T. Ikezawa, T. Yamamoto, M. Hane, Y. Mochizuki, T. Mogami
Improved sub-10-nm CMOS devices have been investigated by the elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. In this eSDE technology, the SEG-Si thickness for eSDE region is precisely controlled by the self-limited Si-SEG process within a narrow slit underneath a SiN sidewall film. Moreover, the SEG-Si film for the elevated source/drain (eS/D) region is also achieved simultaneously. As the results of simultaneously-reduced short-channel effect and parasitic resistance, the Ioff-CV/I characteristics are remarkably improved for both n- and pMOSFETs, as compared with published sub-10-nm planar bulk CMOS devices
{"title":"Improved sub-10-nm CMOS devices with elevated source/drain extensions by tunneling si-selective-epitaxial-growth","authors":"H. Wakabayashi, T. Tatsumi, N. Ikarashi, M. Oshida, H. Kawamoto, N. Ikezawa, T. Ikezawa, T. Yamamoto, M. Hane, Y. Mochizuki, T. Mogami","doi":"10.1109/IEDM.2005.1609290","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609290","url":null,"abstract":"Improved sub-10-nm CMOS devices have been investigated by the elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. In this eSDE technology, the SEG-Si thickness for eSDE region is precisely controlled by the self-limited Si-SEG process within a narrow slit underneath a SiN sidewall film. Moreover, the SEG-Si film for the elevated source/drain (eS/D) region is also achieved simultaneously. As the results of simultaneously-reduced short-channel effect and parasitic resistance, the Ioff-CV/I characteristics are remarkably improved for both n- and pMOSFETs, as compared with published sub-10-nm planar bulk CMOS devices","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"180 1","pages":"145-148"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85191151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609470
C. Bolognesi, H.G. Liu, N. Tao, L. Zheng, X. Zhang, S. Watkins
The InP/GaAsSb/InP "type-II" heterostructure system is of interest for high-speed devices such as photodetectors and double heterostructure bipolar transistors (DHBTs) because its band alignment enables the straightforward injection of electrons from a ~0.72 eV p-type GaAsSb layer into n-type InP without any need for interface grading. We briefly review the salient features of the InP-GaAsSb system, and consider some of the surprising device characteristics encountered in InP/GaAsSb -based devices. In several respects, the InP/GaAsSb system is shown to offer very appealing opportunities for the development of high-speed NpN DHBTs with ultrathin base and collector layers
{"title":"The InP/GaAsSb type-H heterostructure system and its application to high-speed DHBTs and photodetectors: physics, surprises, and opportunities (INVITED)","authors":"C. Bolognesi, H.G. Liu, N. Tao, L. Zheng, X. Zhang, S. Watkins","doi":"10.1109/IEDM.2005.1609470","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609470","url":null,"abstract":"The InP/GaAsSb/InP \"type-II\" heterostructure system is of interest for high-speed devices such as photodetectors and double heterostructure bipolar transistors (DHBTs) because its band alignment enables the straightforward injection of electrons from a ~0.72 eV p-type GaAsSb layer into n-type InP without any need for interface grading. We briefly review the salient features of the InP-GaAsSb system, and consider some of the surprising device characteristics encountered in InP/GaAsSb -based devices. In several respects, the InP/GaAsSb system is shown to offer very appealing opportunities for the development of high-speed NpN DHBTs with ultrathin base and collector layers","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"236 1","pages":"779-782"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82866064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609413
R. Lossy, A. Liero, J. Wurfl, G. Trankle
Gallium nitride transistors for high power microwave application are often limited by power loss due to extended transistor finger size. A new design for the gate supply is presented which allows for higher power gain compared to conventional transistor designs. Using this technique a linear gain of 20 dB is measured for a packaged power device delivering 28 Watt at 2GHz
{"title":"High power, high AlGaN/GaN-HEMTs with novel powerbar design","authors":"R. Lossy, A. Liero, J. Wurfl, G. Trankle","doi":"10.1109/IEDM.2005.1609413","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609413","url":null,"abstract":"Gallium nitride transistors for high power microwave application are often limited by power loss due to extended transistor finger size. A new design for the gate supply is presented which allows for higher power gain compared to conventional transistor designs. Using this technique a linear gain of 20 dB is measured for a packaged power device delivering 28 Watt at 2GHz","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"12 1","pages":"580-582"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85167633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609506
K. Chung, A. Akinwande
{"title":"Detectors, sensors, and mems thin film transistors for displays and system on panel","authors":"K. Chung, A. Akinwande","doi":"10.1109/IEDM.2005.1609506","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609506","url":null,"abstract":"","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"40 1","pages":"910-910"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82436659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609346
D. Shum, A. Tilke, L. Pescini, M. Stiftinger, R. Kakoschke, K.J. Han, S. Kim, V. Hecht, N. Chan, A. Yang, R. Broze
A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias
{"title":"Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond","authors":"D. Shum, A. Tilke, L. Pescini, M. Stiftinger, R. Kakoschke, K.J. Han, S. Kim, V. Hecht, N. Chan, A. Yang, R. Broze","doi":"10.1109/IEDM.2005.1609346","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609346","url":null,"abstract":"A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"9 1","pages":"344-347"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81897681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609392
D. V. Singh, J. Sleight, J. Hergenrother, Z. Ren, K. Jenkins, O. Dokumaci, L. Black, J.B. Chang, H. Nakayama, D. Chidambarrao, R. Venigalla, J. Pan, W. Natzle, B. Tessier, A. Nomura, J. Ott, M. Ieong, W. Haensch
We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the channel during SM likely occurs through the poly-gate, becoming more effective as the body is thinned. Combining SM and DSL results in a net gain that is substantially larger than that obtained using each technique separately
{"title":"Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths","authors":"D. V. Singh, J. Sleight, J. Hergenrother, Z. Ren, K. Jenkins, O. Dokumaci, L. Black, J.B. Chang, H. Nakayama, D. Chidambarrao, R. Venigalla, J. Pan, W. Natzle, B. Tessier, A. Nomura, J. Ott, M. Ieong, W. Haensch","doi":"10.1109/IEDM.2005.1609392","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609392","url":null,"abstract":"We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the channel during SM likely occurs through the poly-gate, becoming more effective as the body is thinned. Combining SM and DSL results in a net gain that is substantially larger than that obtained using each technique separately","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"132 1","pages":"505-508"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80004308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609443
B. Kaczer, Ming-Fu Li
This Session includes six papers describing recent advances in the understanding and characterization of Bias-Temperature Instability and Interface Traps. The first paper, by D. Varghese (IIT Bombay), shows the importance of time delay in NBTI measurements. The authors argue that short time and long time degradation are respectively dispersive and Arrhenius-like. The second paper, by A. T. Krishnan (Texas Instruments), discusses the material dependence of hydrogen diffusion and its impact on NBTI degradation. The effect of the measurement delay and the role of NBTI degradation at different frequencies are also studied.
本次会议包括六篇论文，描述了对偏温不稳定性和界面陷阱的理解和表征的最新进展。第一篇论文由D. Varghese(印度理工学院孟买分校)撰写，展示了时间延迟在NBTI测量中的重要性。作者认为，短时降解和长时间降解分别具有弥散性和阿累尼乌斯样。第二篇论文由A. T. Krishnan (Texas Instruments)撰写，讨论了氢扩散的材料依赖性及其对NBTI降解的影响。研究了不同频率下测量时延的影响和NBTI退化的作用。
{"title":"CMOS and interconnect reliability bias-temperature instability and interface traps","authors":"B. Kaczer, Ming-Fu Li","doi":"10.1109/IEDM.2005.1609443","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609443","url":null,"abstract":"This Session includes six papers describing recent advances in the understanding and characterization of Bias-Temperature Instability and Interface Traps. The first paper, by D. Varghese (IIT Bombay), shows the importance of time delay in NBTI measurements. The authors argue that short time and long time degradation are respectively dispersive and Arrhenius-like. The second paper, by A. T. Krishnan (Texas Instruments), discusses the material dependence of hydrogen diffusion and its impact on NBTI degradation. The effect of the measurement delay and the role of NBTI degradation at different frequencies are also studied.","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"248 1","pages":"683-683"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89173344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609496
J. Slaughter, R. Dave, M. Durlam, G. Kerszykowski, Ken Smith, K. Nagel, B. Feil, J. Calder, M. Deherrera, B. Garni, S. Tehrani
We report here the first integration of a new generation of high magnetoresistance-ratio (MR) magnetic tunnel junction (MTJ) material with a 90 nm CMOS front-end logic process. This new material, with MgO tunnel barriers, significantly increased the read signal over standard AlOx-based material. The 90 nm CMOS test vehicle has 8 kb arrays of 1T1MTJ memory cells with two orthogonal program lines oriented at 45deg from the bit easy axis for toggle switching. Read and toggle-write operations are demonstrated
{"title":"High speed toggle MRAM with mgO-based tunnel junctions","authors":"J. Slaughter, R. Dave, M. Durlam, G. Kerszykowski, Ken Smith, K. Nagel, B. Feil, J. Calder, M. Deherrera, B. Garni, S. Tehrani","doi":"10.1109/IEDM.2005.1609496","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609496","url":null,"abstract":"We report here the first integration of a new generation of high magnetoresistance-ratio (MR) magnetic tunnel junction (MTJ) material with a 90 nm CMOS front-end logic process. This new material, with MgO tunnel barriers, significantly increased the read signal over standard AlOx-based material. The 90 nm CMOS test vehicle has 8 kb arrays of 1T1MTJ memory cells with two orthogonal program lines oriented at 45deg from the bit easy axis for toggle switching. Read and toggle-write operations are demonstrated","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"14 1","pages":"873-876"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87705674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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