Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609348
Anna W. Topol, D. La Tulipe, L. Shi, S. Alam, D. Frank, S. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. Dimilia, M. Robson, E. Duch, M. Farinelli, C. Wang, R. Conti, D. Canaperi, L. Deligianni, A. Kumar, K. Kwietniak, C. D'Emic, J. Ott, A. Young, K. Guarini, M. Ieong
We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers
我们针对三维(3D)集成电路(ic)的关键工艺技术挑战提出了解决方案，这些解决方案能够创建堆叠器件层，它们之间的距离最短，互连密度最高，晶圆对晶圆对齐非常积极。为了实现这一重要的3D集成电路技术里程碑，我们优化了层转移工艺，包括玻璃手柄晶圆、氧化物熔合、晶圆弓补偿方法，以及用于在两个堆叠器件层之间创建高宽高比(6:1 < AR < 11:1)接触的单大马士革图案和金属化方法
{"title":"Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)","authors":"Anna W. Topol, D. La Tulipe, L. Shi, S. Alam, D. Frank, S. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. Dimilia, M. Robson, E. Duch, M. Farinelli, C. Wang, R. Conti, D. Canaperi, L. Deligianni, A. Kumar, K. Kwietniak, C. D'Emic, J. Ott, A. Young, K. Guarini, M. Ieong","doi":"10.1109/IEDM.2005.1609348","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609348","url":null,"abstract":"We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"22 1","pages":"352-355"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74111535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609302
T. Kouno, I.T. Suzuki, S. Otsuka, T. Hosoda, I. Nakamura, I. Mizushima, M. Shiozu, H. Matsuyama, K. Shono, H. Watatani, Y. Ohkura, M. Sato, S. Fukuyama, M. Miyajima
Stress-induced voiding under vias connected to "narrow" Copper (Cu) lines (SIV-N) was observed, for the first time, using newly prepared test structures which consisted of isolated vias between narrow (0.14 mum-wide) and very long (200 mum-long) 2-level Cu wires. Mechanism of SIV-N is different from that of well-known stress-induced voiding under vias connected to "wide" Cu lines (SIV-W), because SIV-N cannot occur during actual time according to the model that explains SIV-W. In addition, we found the effect of plasma pretreatment of cap dielectrics and cap dielectrics themselves on SIV-N and the other reliability issues, and succeeded in obtaining the condition which satisfied SIV-N, SIV-W and EM
{"title":"Stress-induced voiding under vias connected to \"narrow\" copper lines","authors":"T. Kouno, I.T. Suzuki, S. Otsuka, T. Hosoda, I. Nakamura, I. Mizushima, M. Shiozu, H. Matsuyama, K. Shono, H. Watatani, Y. Ohkura, M. Sato, S. Fukuyama, M. Miyajima","doi":"10.1109/IEDM.2005.1609302","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609302","url":null,"abstract":"Stress-induced voiding under vias connected to \"narrow\" Copper (Cu) lines (SIV-N) was observed, for the first time, using newly prepared test structures which consisted of isolated vias between narrow (0.14 mum-wide) and very long (200 mum-long) 2-level Cu wires. Mechanism of SIV-N is different from that of well-known stress-induced voiding under vias connected to \"wide\" Cu lines (SIV-W), because SIV-N cannot occur during actual time according to the model that explains SIV-W. In addition, we found the effect of plasma pretreatment of cap dielectrics and cap dielectrics themselves on SIV-N and the other reliability issues, and succeeded in obtaining the condition which satisfied SIV-N, SIV-W and EM","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"36 1","pages":"187-190"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84919175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609259
R. Hegde, D. Triyoso, P. Tobin, S. Kalpat, M. Ramón, H. Tseng, J. Schaeffer, E. Luckowski, W. Taylor, C. Capasso, D. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L. La, E. Hebert, R. Cotton, X. Wang, S. Zollner, R. Gregory, D. Werho, R. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y. Chiu, B. White
For the first time we report on the development of a novel hafnium zirconate (HfZrOx) gate dielectric with a TaxCy metal gate. Compared to HfO2, the new HfZrOx gate dielectric showed: (1) higher transconductance, (2) less charge trapping, (3) higher drive current, (4) lower NMOS Vt, (5) reduced C-V hysteresis, (6) lower interface state density, (7) superior wafer-level thickness uniformity, and (8) longer PBTI lifetime. We attribute these improvements to a microstructure that is modified by addition of Zr to HfO2
{"title":"Microstructure modified HfO/sub 2/ using Zr addition with Ta/sub x/ C/sub y/ gate for improved device performance and reliability","authors":"R. Hegde, D. Triyoso, P. Tobin, S. Kalpat, M. Ramón, H. Tseng, J. Schaeffer, E. Luckowski, W. Taylor, C. Capasso, D. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L. La, E. Hebert, R. Cotton, X. Wang, S. Zollner, R. Gregory, D. Werho, R. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y. Chiu, B. White","doi":"10.1109/IEDM.2005.1609259","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609259","url":null,"abstract":"For the first time we report on the development of a novel hafnium zirconate (HfZrO<sub>x</sub>) gate dielectric with a Ta<sub>x</sub>C<sub>y</sub> metal gate. Compared to HfO<sub>2</sub>, the new HfZrO<sub>x</sub> gate dielectric showed: (1) higher transconductance, (2) less charge trapping, (3) higher drive current, (4) lower NMOS V<sub>t</sub>, (5) reduced C-V hysteresis, (6) lower interface state density, (7) superior wafer-level thickness uniformity, and (8) longer PBTI lifetime. We attribute these improvements to a microstructure that is modified by addition of Zr to HfO<sub>2</sub>","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"78 1","pages":"35-38"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84943788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609366
M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, M. Yoneda
F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET. Mobility degradation is not accompanied and drive current is increased by 180%. From analytical and electrical characterization, the Vth shift is attributed to change in trap density
{"title":"Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET","authors":"M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, M. Yoneda","doi":"10.1109/IEDM.2005.1609366","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609366","url":null,"abstract":"F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET. Mobility degradation is not accompanied and drive current is increased by 180%. From analytical and electrical characterization, the Vth shift is attributed to change in trap density","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"39 1","pages":"413-416"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81868429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609515
Y. Kiyota, J. Deen
{"title":"Solid-state and nanoelectronic devices active and passive components in cmos-compatible technologies","authors":"Y. Kiyota, J. Deen","doi":"10.1109/IEDM.2005.1609515","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609515","url":null,"abstract":"","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"72 1","pages":"942-942"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79680403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609461
An Chen, S. Haddad, Yi-Ching Wu, T. Fang, Zhida Lan, S. Avanzino, S. Pangrle, M. Buynoski, M. Rathor, W. Cai, N. Tripsas, C. Bill, M. Vanbuskirk, M. Taguchi
A non-volatile resistive switching mechanism based on trap-related space-charge-limited-conduction (SCLC) is proposed. Excellent memory characteristics have been demonstrated using near-stoichiometric cuprous oxide (CuxO) metal-insulator-metal (MIM) structures: low-power operation, fast switching speed, superior temperature characteristics, and long retention. This MIM memory cell is fully compatible with standard CMOS process. The proposed switching mechanism is a strong contender for high density and low cost memory applications
{"title":"Non-volatile resistive switching for advanced memory applications","authors":"An Chen, S. Haddad, Yi-Ching Wu, T. Fang, Zhida Lan, S. Avanzino, S. Pangrle, M. Buynoski, M. Rathor, W. Cai, N. Tripsas, C. Bill, M. Vanbuskirk, M. Taguchi","doi":"10.1109/IEDM.2005.1609461","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609461","url":null,"abstract":"A non-volatile resistive switching mechanism based on trap-related space-charge-limited-conduction (SCLC) is proposed. Excellent memory characteristics have been demonstrated using near-stoichiometric cuprous oxide (CuxO) metal-insulator-metal (MIM) structures: low-power operation, fast switching speed, superior temperature characteristics, and long retention. This MIM memory cell is fully compatible with standard CMOS process. The proposed switching mechanism is a strong contender for high density and low cost memory applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"37 1","pages":"746-749"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80171961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609415
Wataru Saito, M. Kuraguchi, Y. Takada, K. Tsuda, T. Domon, Ichiro Omura, Masakazu Yamaguchi
The current collapse phenomena in 380V/1.9A GaN power-HEMTs designed for high-voltage power electronics application is reported. The influence of these phenomena to the power-electronics circuit performance under high applied voltage is discussed using a 27.1 MHz class-E amplifier, which can be one of an industrial application candidate. It has been found that the optimized field plate structure minimizes the increase of conduction loss caused by the current collapse phenomena and thus improves the power efficiency of the circuit. The minimized device achieved the output power of 13.8 W and the power efficiency of 89.6 % for the demonstrated circuit even with the applied drain voltage of 330 V and the switching frequency of 27.1 MHz. These results show the nature possibility of a new GaN-device application with both high voltage and high frequency condition
{"title":"380v/1.9A GaN power-HEMT: current collapse phenomena under high applied voltage and demonstration of 27.1 MHz class-E amplifier","authors":"Wataru Saito, M. Kuraguchi, Y. Takada, K. Tsuda, T. Domon, Ichiro Omura, Masakazu Yamaguchi","doi":"10.1109/IEDM.2005.1609415","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609415","url":null,"abstract":"The current collapse phenomena in 380V/1.9A GaN power-HEMTs designed for high-voltage power electronics application is reported. The influence of these phenomena to the power-electronics circuit performance under high applied voltage is discussed using a 27.1 MHz class-E amplifier, which can be one of an industrial application candidate. It has been found that the optimized field plate structure minimizes the increase of conduction loss caused by the current collapse phenomena and thus improves the power efficiency of the circuit. The minimized device achieved the output power of 13.8 W and the power efficiency of 89.6 % for the demonstrated circuit even with the applied drain voltage of 330 V and the switching frequency of 27.1 MHz. These results show the nature possibility of a new GaN-device application with both high voltage and high frequency condition","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"24 1","pages":"586-589"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77839820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609297
S. Samanta, P.K. Singh, W. Yoo, G. Samudra, Y. Yeo, L. Bera, N. Balasubramanian
This paper for the first time, reports the memory enhancement characteristics and good retention with feasibility of two-bit operation of small scale devices with gate length down to 100 nm, using double layer W nanocrystals embedded in HfAlO for the next generation memory application. Double layer device shows increasing memory window with scaling which will be extremely beneficial
{"title":"Enhancement of memory window in short channel non-volatile memory devices using double layer tungsten nanocrystals","authors":"S. Samanta, P.K. Singh, W. Yoo, G. Samudra, Y. Yeo, L. Bera, N. Balasubramanian","doi":"10.1109/IEDM.2005.1609297","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609297","url":null,"abstract":"This paper for the first time, reports the memory enhancement characteristics and good retention with feasibility of two-bit operation of small scale devices with gate length down to 100 nm, using double layer W nanocrystals embedded in HfAlO for the next generation memory application. Double layer device shows increasing memory window with scaling which will be extremely beneficial","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"72 1","pages":"170-173"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80951623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609537
Sheng-Chih Lin, R. Mahajan, V. De, K. Banerjee
Cooled chip operation is being seriously evaluated as a practical technique for boosting the performance of high-end microprocessors. This paper presents, for the first time, a comprehensive analysis of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies. Unlike all previous work, our analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While cooling always gives performance gain at the device or circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and the associated cost may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots
{"title":"Analysis and implications of ic cooling for deep nanometer scale cmos technologies","authors":"Sheng-Chih Lin, R. Mahajan, V. De, K. Banerjee","doi":"10.1109/IEDM.2005.1609537","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609537","url":null,"abstract":"Cooled chip operation is being seriously evaluated as a practical technique for boosting the performance of high-end microprocessors. This paper presents, for the first time, a comprehensive analysis of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies. Unlike all previous work, our analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While cooling always gives performance gain at the device or circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and the associated cost may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"1 1","pages":"1018-1021"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89569069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609514
M. Kane, L. Goodman, A. Firester, P. C. van der Wilt, A. Limanov, J. Im
We have fabricated CMOS circuits using sequential laterally solidified silicon TFTs on plastic substrates. NMOS devices have unity-gain frequencies greater than 250 MHz, and CMOS ring oscillators operate at 100 MHz. To our knowledge these are the highest performance transistors and the fastest circuits ever fabricated directly on plastic
{"title":"100 MHz CMOS circuits using sequential laterally solidified silicon thin-film transistors on plastic","authors":"M. Kane, L. Goodman, A. Firester, P. C. van der Wilt, A. Limanov, J. Im","doi":"10.1109/IEDM.2005.1609514","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609514","url":null,"abstract":"We have fabricated CMOS circuits using sequential laterally solidified silicon TFTs on plastic substrates. NMOS devices have unity-gain frequencies greater than 250 MHz, and CMOS ring oscillators operate at 100 MHz. To our knowledge these are the highest performance transistors and the fastest circuits ever fabricated directly on plastic","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"304 1","pages":"939-941"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89588011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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