Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609325
S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M.J. Declereq, A. Ionescu
A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up to 400K and hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds of pWs has been observed, which is outperforming CMOS technology, in terms of power consumption, by orders of magnitude
{"title":"A new logic family based on hybrid MOSFET-polysilicon nanowires","authors":"S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M.J. Declereq, A. Ionescu","doi":"10.1109/IEDM.2005.1609325","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609325","url":null,"abstract":"A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up to 400K and hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds of pWs has been observed, which is outperforming CMOS technology, in terms of power consumption, by orders of magnitude","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"3 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87197236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609334
M. Agah, K. Wise
This paper describes the realization of low-power high-speed micro gas chromatography columns for portable gas analysis systems. The 25cm-long ultra-low-mass MEMS columns, fabricated using stress-free PECVD-oxynitride films in a CMOS-compatible process, allow high-performance separations of n-alkane gas mixtures, are capable of multi-second analysis, and can dissipate less than 10mW at 150degC in vacuum
{"title":"PECVD-oxynitride gas chromatographic columns","authors":"M. Agah, K. Wise","doi":"10.1109/IEDM.2005.1609334","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609334","url":null,"abstract":"This paper describes the realization of low-power high-speed micro gas chromatography columns for portable gas analysis systems. The 25cm-long ultra-low-mass MEMS columns, fabricated using stress-free PECVD-oxynitride films in a CMOS-compatible process, allow high-performance separations of n-alkane gas mixtures, are capable of multi-second analysis, and can dissipate less than 10mW at 150degC in vacuum","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"2 1","pages":"4 pp.-305"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90080534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609355
D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, T. Egawa
GaN/AlGaN device technologies are presented aiming at the applications to power switching systems. In order to reduce on-resistance (Ron), we developed SL (super lattice) capping and QA (quaternary alloy) over-layer techniques for GaN/AlGaN HFET. Further, we achieved almost the same mobility keeping the same 2DEG density for GaN/AlGaN hetero structure grown on Si (111) substrates, which will make the cost comparable to conventional Si one. The experimentally obtained RonA of the FET is 1.9 mOmegacm2, which is 14 times lower than that of Si ones. Additionally, a novel approach to realize enhancement-mode operation of GaN/AlGaN FET is examined over R-plane sapphire, where non-polar AlGaN/GaN heterostructure, free from polarization charge, can be grown
{"title":"AlGaN/GaN devices for future power switching systems","authors":"D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, T. Egawa","doi":"10.1109/IEDM.2005.1609355","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609355","url":null,"abstract":"GaN/AlGaN device technologies are presented aiming at the applications to power switching systems. In order to reduce on-resistance (Ron), we developed SL (super lattice) capping and QA (quaternary alloy) over-layer techniques for GaN/AlGaN HFET. Further, we achieved almost the same mobility keeping the same 2DEG density for GaN/AlGaN hetero structure grown on Si (111) substrates, which will make the cost comparable to conventional Si one. The experimentally obtained RonA of the FET is 1.9 mOmegacm2, which is 14 times lower than that of Si ones. Additionally, a novel approach to realize enhancement-mode operation of GaN/AlGaN FET is examined over R-plane sapphire, where non-polar AlGaN/GaN heterostructure, free from polarization charge, can be grown","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"34 1","pages":"377-380"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85570428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609526
K. Tanaka, K. Takeuchi, M. Hane
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width
{"title":"Practical finFET design considering GIDL for LSTP (low standby power) devices","authors":"K. Tanaka, K. Takeuchi, M. Hane","doi":"10.1109/IEDM.2005.1609526","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609526","url":null,"abstract":"Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"40 1","pages":"980-983"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73491242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609265
W. Lee, A. Waite, H. Nii, H. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black, R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan-Scholl, D.R. Davies, A. Domenicucci, P. Fisher, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida, M. Kiene, J. Kluth, C. Labelle, A. Madan, K. Malone, P. Mclaughlin, M. Minami, D. Mocuta, R. Murphy, C. Muzzy, M. Newport, S. Panda, I. Peidous, A. Sakamoto, T. Sato, G. Sudo, H. vanMeer, T. Yamashita, H. Zhu, P. Agnello, G. Bronner, G. Freeman, S. Huang, T. Ivers, S. Luning, K. Miyamoto, H. Nye, J. Pellerin, K. Rim, D. Schepis, T. Spooner, X. Chen, M. Khare, M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, H. Engelmann, A. Hellmich, K. Hempel, G. Koerner, A. Neu, R. Otterbach, C. Reichel, M. Trentsch, P. Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw, N. Kepler
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (Vdd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum2
提出了一种高性能65nm SOI CMOS技术。采用双应力线性线(DSL)、嵌入式SiGe和应力记忆技术来提高晶体管的速度。该技术的先进低K BEOL具有10个布线水平，在选定的水平上具有新颖的K=2.75薄膜。该薄膜是基于二氧化硅的电介质，针对应力进行了优化，以实现集成以增强性能。由此产生的技术在200 nA/um (Vdd=1.0 V)的关断电流下提供了分别为735 muA/mum和1259 muA/mum的pet和net交流开关电流，互连延迟降低了6%。在尺寸为0.65 mum2的SRAM电池上演示了工艺产率
{"title":"High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL","authors":"W. Lee, A. Waite, H. Nii, H. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black, R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan-Scholl, D.R. Davies, A. Domenicucci, P. Fisher, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida, M. Kiene, J. Kluth, C. Labelle, A. Madan, K. Malone, P. Mclaughlin, M. Minami, D. Mocuta, R. Murphy, C. Muzzy, M. Newport, S. Panda, I. Peidous, A. Sakamoto, T. Sato, G. Sudo, H. vanMeer, T. Yamashita, H. Zhu, P. Agnello, G. Bronner, G. Freeman, S. Huang, T. Ivers, S. Luning, K. Miyamoto, H. Nye, J. Pellerin, K. Rim, D. Schepis, T. Spooner, X. Chen, M. Khare, M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, H. Engelmann, A. Hellmich, K. Hempel, G. Koerner, A. Neu, R. Otterbach, C. Reichel, M. Trentsch, P. Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw, N. Kepler","doi":"10.1109/IEDM.2005.1609265","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609265","url":null,"abstract":"A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (Vdd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum2","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"1 1","pages":"4 pp.-59"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88850549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609287
Y. Nakabayashi, T. Ishihara, J. Koga, M. Takayanagi, S. Takagi
Inversion-layer mobility in highly doped channel Si MOSFETs was investigated. It was found, for the first time, substrate Coulomb scattering (musub) has anomalous surface carrier density (N S) dependence when acceptor concentration (NA) becomes larger than 2times1018 cm-3. The mu sub behavior can be explained by the suppression of the screening effect. In addition, interface Coulomb scattering (muit ) has stronger NS dependence than ever reported. The muit behavior can be explained in terms of the relative distance between the surface carriers and interface states. Influence of high channel doping on MOS interface barrier height was also studied
{"title":"New findings on inversion-layer mobility in highly doped channel Si MOSFETs","authors":"Y. Nakabayashi, T. Ishihara, J. Koga, M. Takayanagi, S. Takagi","doi":"10.1109/IEDM.2005.1609287","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609287","url":null,"abstract":"Inversion-layer mobility in highly doped channel Si MOSFETs was investigated. It was found, for the first time, substrate Coulomb scattering (mu<sub>sub</sub>) has anomalous surface carrier density (N <sub>S</sub>) dependence when acceptor concentration (N<sub>A</sub>) becomes larger than 2times10<sup>18</sup> cm<sup>-3</sup>. The mu <sub>sub</sub> behavior can be explained by the suppression of the screening effect. In addition, interface Coulomb scattering (mu<sub>it </sub>) has stronger N<sub>S</sub> dependence than ever reported. The mu<sub>it</sub> behavior can be explained in terms of the relative distance between the surface carriers and interface states. Influence of high channel doping on MOS interface barrier height was also studied","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"36 1","pages":"133-136"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81692848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609404
H. Lue, Szu-Yu Wang, E. Lai, Y. Shih, S. Lai, Ling-Wu Yang, Kuang-Chao Chen, J. Ku, K. Hsieh, Rich Liu, Chih-Yuan Lu
A bandgap engineered SONOS with greatly improved reliability properties is proposed. This concept is demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin "O1/N1/O2" serves as a non-trapping tunneling dielectric, N2 the high-trapping-rate charge storage layer, and O3 the blocking oxide. The ultra-thin "O1/N1/O2" provides a "modulated tunneling barrier" - it suppresses direct tunneling at low electric field during retention, while it allows efficient hole tunneling erase at high electric field due to the band offset. Therefore, this BE-SONOS offers fast hole tunneling erase, while it is immune to the retention problem of the conventional SONOS. With a N+-poly gate, we achieve self-convergent erased Vt ~3 V, suitable for NOR flash application. On the other hand, by using a P+-poly gate, a depletion mode device (Vt < 0) is obtained, and a very large memory window (> 6 V) is achieved, ideal for MLC-NAND application. Excellent performance and reliability for both applications are demonstrated. Furthermore, with this simple structure and no new materials BE-SONOS is readily manufacturable
{"title":"BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability","authors":"H. Lue, Szu-Yu Wang, E. Lai, Y. Shih, S. Lai, Ling-Wu Yang, Kuang-Chao Chen, J. Ku, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/IEDM.2005.1609404","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609404","url":null,"abstract":"A bandgap engineered SONOS with greatly improved reliability properties is proposed. This concept is demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin \"O1/N1/O2\" serves as a non-trapping tunneling dielectric, N2 the high-trapping-rate charge storage layer, and O3 the blocking oxide. The ultra-thin \"O1/N1/O2\" provides a \"modulated tunneling barrier\" - it suppresses direct tunneling at low electric field during retention, while it allows efficient hole tunneling erase at high electric field due to the band offset. Therefore, this BE-SONOS offers fast hole tunneling erase, while it is immune to the retention problem of the conventional SONOS. With a N+-poly gate, we achieve self-convergent erased Vt ~3 V, suitable for NOR flash application. On the other hand, by using a P+-poly gate, a depletion mode device (Vt < 0) is obtained, and a very large memory window (> 6 V) is achieved, ideal for MLC-NAND application. Excellent performance and reliability for both applications are demonstrated. Furthermore, with this simple structure and no new materials BE-SONOS is readily manufacturable","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"59 1","pages":"547-550"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85633651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609474
K. Itonaga, H. Abe, I. Yoshihara, T. Hirayama
We've realized a 2.5-mum square pixel with high saturation electron capacity and sensitivity, which realizes the low dark current as well as triple Qs value of the conventional STI, by expanding the buried photodiode under the isolation oxide, and the sensitivity gain will be 20% higher using the Cu process than is possible with the Al process
{"title":"A high-performance and low-noise CMOS image sensor with an expanding photodiode under the isolation oxide","authors":"K. Itonaga, H. Abe, I. Yoshihara, T. Hirayama","doi":"10.1109/IEDM.2005.1609474","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609474","url":null,"abstract":"We've realized a 2.5-mum square pixel with high saturation electron capacity and sensitivity, which realizes the low dark current as well as triple Qs value of the conventional STI, by expanding the buried photodiode under the isolation oxide, and the sensitivity gain will be 20% higher using the Cu process than is possible with the Al process","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"67 1","pages":"4 pp.-794"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85837489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609391
T. Sanuki, H. Tanaka, K. Oota, O. Fujii, R. Yamaguchi, K. Nakayama, Y. Morimasa, Y. Takasu, J. Idebuchi, N. Nishiyama, H. Fukui, H. Yoshimura, K. Matsuo, I. Mizushima, H. Ito, Y. Takegawa, M. Saito, M. Iwai, N. Nagashima, F. Matsuoka
For the first time, a novel CMOSFET structure in substrate strained-Si of lang100rang-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by high channel doping. We applied Si selective epitaxial growth on recessed S/D region in SiGe layer, which is effective to induce high tensile stress and reduce S/D resistance. In strained Si NMOS, 15% performance improvement is achieved. Moreover, additive stress by using tensile CESL can further improve the drive current. In strained Si PMOS, 25% performance improvement is achieved in both narrow and wide channel device
{"title":"New stress inducing technique of epitaxial si on recessed S/D fabricated in substrate strained-si of [100]channel on rotated wafers","authors":"T. Sanuki, H. Tanaka, K. Oota, O. Fujii, R. Yamaguchi, K. Nakayama, Y. Morimasa, Y. Takasu, J. Idebuchi, N. Nishiyama, H. Fukui, H. Yoshimura, K. Matsuo, I. Mizushima, H. Ito, Y. Takegawa, M. Saito, M. Iwai, N. Nagashima, F. Matsuoka","doi":"10.1109/IEDM.2005.1609391","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609391","url":null,"abstract":"For the first time, a novel CMOSFET structure in substrate strained-Si of lang100rang-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by high channel doping. We applied Si selective epitaxial growth on recessed S/D region in SiGe layer, which is effective to induce high tensile stress and reduce S/D resistance. In strained Si NMOS, 15% performance improvement is achieved. Moreover, additive stress by using tensile CESL can further improve the drive current. In strained Si PMOS, 25% performance improvement is achieved in both narrow and wide channel device","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"22 1","pages":"501-504"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87415640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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