Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609325
S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M.J. Declereq, A. Ionescu
A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up to 400K and hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds of pWs has been observed, which is outperforming CMOS technology, in terms of power consumption, by orders of magnitude
{"title":"A new logic family based on hybrid MOSFET-polysilicon nanowires","authors":"S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M.J. Declereq, A. Ionescu","doi":"10.1109/IEDM.2005.1609325","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609325","url":null,"abstract":"A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This logic family can be operated from 4K up to 400K and hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds of pWs has been observed, which is outperforming CMOS technology, in terms of power consumption, by orders of magnitude","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"3 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87197236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609334
M. Agah, K. Wise
This paper describes the realization of low-power high-speed micro gas chromatography columns for portable gas analysis systems. The 25cm-long ultra-low-mass MEMS columns, fabricated using stress-free PECVD-oxynitride films in a CMOS-compatible process, allow high-performance separations of n-alkane gas mixtures, are capable of multi-second analysis, and can dissipate less than 10mW at 150degC in vacuum
{"title":"PECVD-oxynitride gas chromatographic columns","authors":"M. Agah, K. Wise","doi":"10.1109/IEDM.2005.1609334","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609334","url":null,"abstract":"This paper describes the realization of low-power high-speed micro gas chromatography columns for portable gas analysis systems. The 25cm-long ultra-low-mass MEMS columns, fabricated using stress-free PECVD-oxynitride films in a CMOS-compatible process, allow high-performance separations of n-alkane gas mixtures, are capable of multi-second analysis, and can dissipate less than 10mW at 150degC in vacuum","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"2 1","pages":"4 pp.-305"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90080534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609355
D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, T. Egawa
GaN/AlGaN device technologies are presented aiming at the applications to power switching systems. In order to reduce on-resistance (Ron), we developed SL (super lattice) capping and QA (quaternary alloy) over-layer techniques for GaN/AlGaN HFET. Further, we achieved almost the same mobility keeping the same 2DEG density for GaN/AlGaN hetero structure grown on Si (111) substrates, which will make the cost comparable to conventional Si one. The experimentally obtained RonA of the FET is 1.9 mOmegacm2, which is 14 times lower than that of Si ones. Additionally, a novel approach to realize enhancement-mode operation of GaN/AlGaN FET is examined over R-plane sapphire, where non-polar AlGaN/GaN heterostructure, free from polarization charge, can be grown
{"title":"AlGaN/GaN devices for future power switching systems","authors":"D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, T. Egawa","doi":"10.1109/IEDM.2005.1609355","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609355","url":null,"abstract":"GaN/AlGaN device technologies are presented aiming at the applications to power switching systems. In order to reduce on-resistance (Ron), we developed SL (super lattice) capping and QA (quaternary alloy) over-layer techniques for GaN/AlGaN HFET. Further, we achieved almost the same mobility keeping the same 2DEG density for GaN/AlGaN hetero structure grown on Si (111) substrates, which will make the cost comparable to conventional Si one. The experimentally obtained RonA of the FET is 1.9 mOmegacm2, which is 14 times lower than that of Si ones. Additionally, a novel approach to realize enhancement-mode operation of GaN/AlGaN FET is examined over R-plane sapphire, where non-polar AlGaN/GaN heterostructure, free from polarization charge, can be grown","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"34 1","pages":"377-380"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85570428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609359
J. Suñé, E. Wu
The mechanisms of hydrogen release (HR) involved in the degradation and breakdown (BD) of SiO2-based gate dielectrics are studied by means of the analysis of charge to breakdown (QBD ) data versus electron energy, and comparing with scanning tunneling microscope (STM) experiments of H desorption from silicon surfaces. Our results reveal an important role of vibrational and electronic excitation mechanisms
{"title":"Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides","authors":"J. Suñé, E. Wu","doi":"10.1109/IEDM.2005.1609359","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609359","url":null,"abstract":"The mechanisms of hydrogen release (HR) involved in the degradation and breakdown (BD) of SiO2-based gate dielectrics are studied by means of the analysis of charge to breakdown (QBD ) data versus electron energy, and comparing with scanning tunneling microscope (STM) experiments of H desorption from silicon surfaces. Our results reveal an important role of vibrational and electronic excitation mechanisms","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"388-391"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74040883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609526
K. Tanaka, K. Takeuchi, M. Hane
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width
{"title":"Practical finFET design considering GIDL for LSTP (low standby power) devices","authors":"K. Tanaka, K. Takeuchi, M. Hane","doi":"10.1109/IEDM.2005.1609526","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609526","url":null,"abstract":"Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"40 1","pages":"980-983"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73491242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609284
H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki
On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the world's first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz
的基础上制造一个CPU的玻璃作为数字电路在b .李et al。(2003)和t . Ikeda et al。(2004),以及灵活的CPU使用TFT转移的制造技术提出了t .高山et al .(2004),我们已经成功地开发的世界上第一个灵活RFCPUs(8位、被动类型)通过添加CPU天线,一个模拟电路,一个加密函数和一个射频识别功能,使用频率为13.56兆赫的射频信号运作
{"title":"RFCPUs on glass and plastic substrates fabricated by TFT transfer technology","authors":"H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki","doi":"10.1109/IEDM.2005.1609284","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609284","url":null,"abstract":"On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the world's first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"70 1","pages":"125-127"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77389627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609509
R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker
To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO2 in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO2 C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO2 C/L as a part of the gate oxide. Field effect mobility (muFE) for electrons and holes of 510 cm2/Vs and of 210 cm2/Vs were obtained respectively
{"title":"High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer","authors":"R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker","doi":"10.1109/IEDM.2005.1609509","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609509","url":null,"abstract":"To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO<sub>2</sub> in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO<sub>2</sub> C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO<sub>2</sub> C/L as a part of the gate oxide. Field effect mobility (mu<sub>FE</sub>) for electrons and holes of 510 cm<sup>2</sup>/Vs and of 210 cm<sup>2</sup>/Vs were obtained respectively","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"919-922"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76936628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609389
K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo
This paper reports a novel technique to fabricate uniaxial compressive strained p-channel transistors with silicon-germanium (SiGe) source and drain (S/D) stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in silicon-on-insulator (SOI) P-MOSFETs with a gate length LG of 90 nm. Drive current IDsat enhancement of up to 35% was observed
本文报道了一种用硅锗(SiGe)源极和漏极(S/D)应力源制备单轴压缩应变p沟道晶体管的新技术。该工艺涉及选择性生长的SiGe区域的局部Ge凝聚，从而将Ge驱动到晶体管沟道附近的源极和漏极区域并使其浓度增加。该工艺特别适用于超薄体(UTB)晶体管，因为它在SiGe外延之前消除了对Si凹槽蚀刻的需要。此外，对于UTB结构，Ge冷凝所需的热预算并不令人望而却步。在S/D区域可以实现高Ge摩尔分数，从而导致晶体管通道中更高的应变水平。我们在栅极长度LG为90 nm的绝缘体上硅(SOI) p - mosfet中证明了该技术的可行性。观察到驱动电流IDsat增强高达35%
{"title":"Source/drain germanium condensation for p-channel strained ultra-thin body transistors","authors":"K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo","doi":"10.1109/IEDM.2005.1609389","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609389","url":null,"abstract":"This paper reports a novel technique to fabricate uniaxial compressive strained p-channel transistors with silicon-germanium (SiGe) source and drain (S/D) stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in silicon-on-insulator (SOI) P-MOSFETs with a gate length LG of 90 nm. Drive current IDsat enhancement of up to 35% was observed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"219 1","pages":"493-496"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75689596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609320
N. Srivastava, R. Joshi, K. Banerjee
This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%
{"title":"Carbon nanotube interconnects: implications for performance, power dissipation and thermal management","authors":"N. Srivastava, R. Joshi, K. Banerjee","doi":"10.1109/IEDM.2005.1609320","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609320","url":null,"abstract":"This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"9 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80074334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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