Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609403
D. Ielmini, A. Spinelli, A. Lacaita, L. Chiavarone, A. Visconti
A new experimental technique for investigating the trapping-detrapping time constants for electrons at stress-induced defects in the silicon oxide is presented. The new technique is based on the gate-stress measurement for flash memories, with the application of a pulsed gate voltage. Data for 512 Kbit NOR-flash arrays are presented, and analyzed by analytical and Monte Carlo models for the trap-assisted tunneling mechanism under pulsed conditions. Comparison between experimental data and calculations for selected cells allows for an estimation of the energy and spatial depth of the oxide traps
{"title":"A new charge-trapping technique to extract SILC-trap time constants in SiO/sub 2/","authors":"D. Ielmini, A. Spinelli, A. Lacaita, L. Chiavarone, A. Visconti","doi":"10.1109/IEDM.2005.1609403","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609403","url":null,"abstract":"A new experimental technique for investigating the trapping-detrapping time constants for electrons at stress-induced defects in the silicon oxide is presented. The new technique is based on the gate-stress measurement for flash memories, with the application of a pulsed gate voltage. Data for 512 Kbit NOR-flash arrays are presented, and analyzed by analytical and Monte Carlo models for the trap-assisted tunneling mechanism under pulsed conditions. Comparison between experimental data and calculations for selected cells allows for an estimation of the energy and spatial depth of the oxide traps","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"9 1","pages":"543-546"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87890932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609267
A. Steegen, R. Mo, R. Mann, M. Sun, M. Eller, G. Leake, D. Vietzke, A. Tilke, F. Guarín, A. Fischer, T. Pompl, G. Massey, A. Vayshenker, W. Tan, A. Ebert, W. Lin, W. Gao, J. Lian, J. Kim, P. Wrschka, J. Yang, A. Ajmera, R. Knoefler, Y. Teh, F. Jamin, J. Park, K. Hooper, C. Griffin, P. Nguyen, V. Klee, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. Benedict, S. Scheer, H. Zhuang, V. Ramanchandran, G. Matusiewicz, Y. Lin, Y. Siew, F. Zhang, L. S. Leong, S. L. Liew, K. Park, K. Lee, D. Hong, S. Choi, E. Kaltalioglu, S.O. Kim, M. Naujok, M. Sherony, A. Cowley, A. Thomas, J. Sudijohno, T. Schiml, J. Ku, I. Yang
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and power reduction. A gate dielectric with an nfet leakage current as low as 15pA/mum and with exceptional reliability characteristics has been demonstrated. Moreover, competitive drive current has been achieved, 725/343muA/mum at an off current of 7nA/mum for n/pfets at nominal voltage. A pfet performance enhancement of an additional 13% at 7nA/mum off current was achieved by using mobility enhancement techniques without adding process complexity. An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current
{"title":"65nm cmos technology for low power applications","authors":"A. Steegen, R. Mo, R. Mann, M. Sun, M. Eller, G. Leake, D. Vietzke, A. Tilke, F. Guarín, A. Fischer, T. Pompl, G. Massey, A. Vayshenker, W. Tan, A. Ebert, W. Lin, W. Gao, J. Lian, J. Kim, P. Wrschka, J. Yang, A. Ajmera, R. Knoefler, Y. Teh, F. Jamin, J. Park, K. Hooper, C. Griffin, P. Nguyen, V. Klee, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. Benedict, S. Scheer, H. Zhuang, V. Ramanchandran, G. Matusiewicz, Y. Lin, Y. Siew, F. Zhang, L. S. Leong, S. L. Liew, K. Park, K. Lee, D. Hong, S. Choi, E. Kaltalioglu, S.O. Kim, M. Naujok, M. Sherony, A. Cowley, A. Thomas, J. Sudijohno, T. Schiml, J. Ku, I. Yang","doi":"10.1109/IEDM.2005.1609267","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609267","url":null,"abstract":"This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and power reduction. A gate dielectric with an nfet leakage current as low as 15pA/mum and with exceptional reliability characteristics has been demonstrated. Moreover, competitive drive current has been achieved, 725/343muA/mum at an off current of 7nA/mum for n/pfets at nominal voltage. A pfet performance enhancement of an additional 13% at 7nA/mum off current was achieved by using mobility enhancement techniques without adding process complexity. An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"1 1","pages":"64-67"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76474600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609490
G. Servalli, D. Brazzelli, E. Camerlenghi, G. Capetti, S. Costantini, C. Cupeta, D. DeSimone, A. Ghetti, T. Ghilardi, P. Gulli, M. Mariani, A. Pavan, R. Somaschini
A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS
{"title":"A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application","authors":"G. Servalli, D. Brazzelli, E. Camerlenghi, G. Capetti, S. Costantini, C. Cupeta, D. DeSimone, A. Ghetti, T. Ghilardi, P. Gulli, M. Mariani, A. Pavan, R. Somaschini","doi":"10.1109/IEDM.2005.1609490","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609490","url":null,"abstract":"A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"6 1","pages":"849-852"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72656510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609344
W. Müller, G. Aichmayr, W. Bergner, E. Erben, T. Hecht, C. Kapteyn, A. Kersch, S. Kudelka, F. Lau, J. Luetzen, A. Orth, J. Nuetzel, T. Schloesser, A. Scholz, U. Schroeder, Alexander Sieck, Andrea Spitzer, M. Strasser, Peng Wang, S. Wege, R. Weis
This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures
{"title":"Challenges for the DRAM cell scaling to 40nm","authors":"W. Müller, G. Aichmayr, W. Bergner, E. Erben, T. Hecht, C. Kapteyn, A. Kersch, S. Kudelka, F. Lau, J. Luetzen, A. Orth, J. Nuetzel, T. Schloesser, A. Scholz, U. Schroeder, Alexander Sieck, Andrea Spitzer, M. Strasser, Peng Wang, S. Wege, R. Weis","doi":"10.1109/IEDM.2005.1609344","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609344","url":null,"abstract":"This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"4 pp.-339"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73007934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609296
Sangmoo Choi, Hyejung Choi, Tae-Wook Kim, Hyundeok Yang, Takhee Lee, S. Jeon, Chungwoo Kim, H. Hwang
We report on the excellent memory properties of silicon nanocrystals (Si-NCs) embedded in SiN. Si-NCs were formed by SiH4 low-energy plasma immersion ion implantation. Compared with control Si+-implanted sample, additional hydrogen enhanced Si-NC density. By incorporating Si-NCs in SiN, improved program/erase efficiency, endurance and retention characteristics were observed due to the generation of additional accessible deep charge traps. Using conductive atomic force microscopy and MIS device with gate area of 100 nm, charge trapping/detrapping and multi-level charge storage of single Si-NC at room temperature were observed
{"title":"High density silicon nanocrystal embedded in sin prepared by low energy (<500eV) SiH/sub 4/ plasma immersion ion implantation for non-volatile memory applications","authors":"Sangmoo Choi, Hyejung Choi, Tae-Wook Kim, Hyundeok Yang, Takhee Lee, S. Jeon, Chungwoo Kim, H. Hwang","doi":"10.1109/IEDM.2005.1609296","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609296","url":null,"abstract":"We report on the excellent memory properties of silicon nanocrystals (Si-NCs) embedded in SiN. Si-NCs were formed by SiH4 low-energy plasma immersion ion implantation. Compared with control Si+-implanted sample, additional hydrogen enhanced Si-NC density. By incorporating Si-NCs in SiN, improved program/erase efficiency, endurance and retention characteristics were observed due to the generation of additional accessible deep charge traps. Using conductive atomic force microscopy and MIS device with gate area of 100 nm, charge trapping/detrapping and multi-level charge storage of single Si-NC at room temperature were observed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"120 1","pages":"166-169"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79428230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609351
G. Ma, Qiang Chen, O. Tornblad, Tao Wei, C. Ahrens, R. Gerlach
LDMOS technologies based in G. Ma et al. (1996) and H. Brech et al. (2003) have been in dominate position in wireless base station applications for frequencies ranging from 450MHz to 2.7GHz for the last 10 years due to performance, cost, reliability, and power capability advantages. This paper reviews the leading edge LDMOS development at Infineon and discusses future potential and limitation for LDMOS technologies in general; benchmarking with alternative technologies is also presented
{"title":"High frequency power LDMOS technologies for base station applications status, potential, and benchmarking","authors":"G. Ma, Qiang Chen, O. Tornblad, Tao Wei, C. Ahrens, R. Gerlach","doi":"10.1109/IEDM.2005.1609351","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609351","url":null,"abstract":"LDMOS technologies based in G. Ma et al. (1996) and H. Brech et al. (2003) have been in dominate position in wireless base station applications for frequencies ranging from 450MHz to 2.7GHz for the last 10 years due to performance, cost, reliability, and power capability advantages. This paper reviews the leading edge LDMOS development at Infineon and discusses future potential and limitation for LDMOS technologies in general; benchmarking with alternative technologies is also presented","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"71 1","pages":"361-364"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78961430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609341
Yoocheol Shin, Jungdal Choi, Chang-seok Kang, Changhyun Lee, Ki-Tae Park, Jang‐Sik Lee, Jongsun Sel, V. Kim, Byeongin Choi, J. Sim, Dongchan Kim, Hag-ju Cho, Kinam Kim
A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology
{"title":"A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs","authors":"Yoocheol Shin, Jungdal Choi, Chang-seok Kang, Changhyun Lee, Ki-Tae Park, Jang‐Sik Lee, Jongsun Sel, V. Kim, Byeongin Choi, J. Sim, Dongchan Kim, Hag-ju Cho, Kinam Kim","doi":"10.1109/IEDM.2005.1609341","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609341","url":null,"abstract":"A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"70 1","pages":"327-330"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75863563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609491
R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita
It is shown that, for 35 nm gate length, a silicon nitride trap memory using double junction tunneling can retain more than 4 decades memory window for 10 years in less than 9 volts w/e voltage, where 1E+6 w/e cycle endurance is attained simultaneously. This is due to Coulomb blockade and quantum confinement in Si nanocrystals lying between double tunnel oxides, and further improvement is possible by Si nanocrystal scaling. Therefore, the double junction tunneling SiN memory is an excellent candidate for less than 35nm region future memory
{"title":"35 nm floating gate planar MOSFET memory using double junction tunneling","authors":"R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita","doi":"10.1109/IEDM.2005.1609491","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609491","url":null,"abstract":"It is shown that, for 35 nm gate length, a silicon nitride trap memory using double junction tunneling can retain more than 4 decades memory window for 10 years in less than 9 volts w/e voltage, where 1E+6 w/e cycle endurance is attained simultaneously. This is due to Coulomb blockade and quantum confinement in Si nanocrystals lying between double tunnel oxides, and further improvement is possible by Si nanocrystal scaling. Therefore, the double junction tunneling SiN memory is an excellent candidate for less than 35nm region future memory","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"39 1","pages":"853-856"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78083103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609464
H. Sim, Hyejung Choi, Dongsoo Lee, M. Chang, Dooho Choi, Y. Son, Eun-Hong Lee, Wonjoo Kim, Yoondong Park, I. Yoo, H. Hwang
We have investigated single crystal Nb-doped SrTiO3 in terms of its potential utility in nonvolatile memory applications. Compared with polycrystalline oxide (Nb2O5, ZrO x and Cr-SrTiO3), the Pt/single crystal Nb:SrTiO 3 Schottky junction exhibits excellent memory characteristics including uniformity of set/reset bias, die-to-die reproducibility, data retention at high temperature, reliability under cycle stress, and multi-bit operation characteristics. The switching mechanism might be explained by modulation of the Schottky barrier height by charge trapping at the interface
{"title":"Excellent resistance switching characteristics of Pt/SrTiO/sub 3/ schottky junction for multi-bit nonvolatile memory application","authors":"H. Sim, Hyejung Choi, Dongsoo Lee, M. Chang, Dooho Choi, Y. Son, Eun-Hong Lee, Wonjoo Kim, Yoondong Park, I. Yoo, H. Hwang","doi":"10.1109/IEDM.2005.1609464","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609464","url":null,"abstract":"We have investigated single crystal Nb-doped SrTiO<sub>3</sub> in terms of its potential utility in nonvolatile memory applications. Compared with polycrystalline oxide (Nb<sub>2</sub>O<sub>5</sub>, ZrO <sub>x</sub> and Cr-SrTiO<sub>3</sub>), the Pt/single crystal Nb:SrTiO <sub>3</sub> Schottky junction exhibits excellent memory characteristics including uniformity of set/reset bias, die-to-die reproducibility, data retention at high temperature, reliability under cycle stress, and multi-bit operation characteristics. The switching mechanism might be explained by modulation of the Schottky barrier height by charge trapping at the interface","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"31 1","pages":"758-761"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73086536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609442
H. Sanda, J. Mcvittie, M. Koto, K. Yamagata, T. Yonehara, Y. Nishi
To develop a new device layer transfer technology with porous layer splitting, CMOS FETs were successfully fabricated on epitaxial layers with different thicknesses over porous silicon for the first time. FETs on more than 300nm thick epitaxial films show satisfactory electrical performance. A fabricated active layer was successfully transferred on a flexible plastic substrate for the first time. Transferred devices also show excellent performance. This technology is applicable to flexible single crystal ICs and to thermal cooling of active layers
{"title":"Fabrication and characterization of CMOSFETs on porous silicon for novel device layer transfer","authors":"H. Sanda, J. Mcvittie, M. Koto, K. Yamagata, T. Yonehara, Y. Nishi","doi":"10.1109/IEDM.2005.1609442","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609442","url":null,"abstract":"To develop a new device layer transfer technology with porous layer splitting, CMOS FETs were successfully fabricated on epitaxial layers with different thicknesses over porous silicon for the first time. FETs on more than 300nm thick epitaxial films show satisfactory electrical performance. A fabricated active layer was successfully transferred on a flexible plastic substrate for the first time. Transferred devices also show excellent performance. This technology is applicable to flexible single crystal ICs and to thermal cooling of active layers","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"16 1","pages":"679-682"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74102996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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