Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609273
Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang
This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations
{"title":"Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations","authors":"Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang","doi":"10.1109/IEDM.2005.1609273","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609273","url":null,"abstract":"This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"24 1","pages":"4 pp.-88"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80513401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609287
Y. Nakabayashi, T. Ishihara, J. Koga, M. Takayanagi, S. Takagi
Inversion-layer mobility in highly doped channel Si MOSFETs was investigated. It was found, for the first time, substrate Coulomb scattering (musub) has anomalous surface carrier density (N S) dependence when acceptor concentration (NA) becomes larger than 2times1018 cm-3. The mu sub behavior can be explained by the suppression of the screening effect. In addition, interface Coulomb scattering (muit ) has stronger NS dependence than ever reported. The muit behavior can be explained in terms of the relative distance between the surface carriers and interface states. Influence of high channel doping on MOS interface barrier height was also studied
{"title":"New findings on inversion-layer mobility in highly doped channel Si MOSFETs","authors":"Y. Nakabayashi, T. Ishihara, J. Koga, M. Takayanagi, S. Takagi","doi":"10.1109/IEDM.2005.1609287","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609287","url":null,"abstract":"Inversion-layer mobility in highly doped channel Si MOSFETs was investigated. It was found, for the first time, substrate Coulomb scattering (mu<sub>sub</sub>) has anomalous surface carrier density (N <sub>S</sub>) dependence when acceptor concentration (N<sub>A</sub>) becomes larger than 2times10<sup>18</sup> cm<sup>-3</sup>. The mu <sub>sub</sub> behavior can be explained by the suppression of the screening effect. In addition, interface Coulomb scattering (mu<sub>it </sub>) has stronger N<sub>S</sub> dependence than ever reported. The mu<sub>it</sub> behavior can be explained in terms of the relative distance between the surface carriers and interface states. Influence of high channel doping on MOS interface barrier height was also studied","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"36 1","pages":"133-136"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81692848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609265
W. Lee, A. Waite, H. Nii, H. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black, R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan-Scholl, D.R. Davies, A. Domenicucci, P. Fisher, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida, M. Kiene, J. Kluth, C. Labelle, A. Madan, K. Malone, P. Mclaughlin, M. Minami, D. Mocuta, R. Murphy, C. Muzzy, M. Newport, S. Panda, I. Peidous, A. Sakamoto, T. Sato, G. Sudo, H. vanMeer, T. Yamashita, H. Zhu, P. Agnello, G. Bronner, G. Freeman, S. Huang, T. Ivers, S. Luning, K. Miyamoto, H. Nye, J. Pellerin, K. Rim, D. Schepis, T. Spooner, X. Chen, M. Khare, M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, H. Engelmann, A. Hellmich, K. Hempel, G. Koerner, A. Neu, R. Otterbach, C. Reichel, M. Trentsch, P. Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw, N. Kepler
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (Vdd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum2
提出了一种高性能65nm SOI CMOS技术。采用双应力线性线(DSL)、嵌入式SiGe和应力记忆技术来提高晶体管的速度。该技术的先进低K BEOL具有10个布线水平，在选定的水平上具有新颖的K=2.75薄膜。该薄膜是基于二氧化硅的电介质，针对应力进行了优化，以实现集成以增强性能。由此产生的技术在200 nA/um (Vdd=1.0 V)的关断电流下提供了分别为735 muA/mum和1259 muA/mum的pet和net交流开关电流，互连延迟降低了6%。在尺寸为0.65 mum2的SRAM电池上演示了工艺产率
{"title":"High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL","authors":"W. Lee, A. Waite, H. Nii, H. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black, R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan-Scholl, D.R. Davies, A. Domenicucci, P. Fisher, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida, M. Kiene, J. Kluth, C. Labelle, A. Madan, K. Malone, P. Mclaughlin, M. Minami, D. Mocuta, R. Murphy, C. Muzzy, M. Newport, S. Panda, I. Peidous, A. Sakamoto, T. Sato, G. Sudo, H. vanMeer, T. Yamashita, H. Zhu, P. Agnello, G. Bronner, G. Freeman, S. Huang, T. Ivers, S. Luning, K. Miyamoto, H. Nye, J. Pellerin, K. Rim, D. Schepis, T. Spooner, X. Chen, M. Khare, M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, H. Engelmann, A. Hellmich, K. Hempel, G. Koerner, A. Neu, R. Otterbach, C. Reichel, M. Trentsch, P. Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw, N. Kepler","doi":"10.1109/IEDM.2005.1609265","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609265","url":null,"abstract":"A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (Vdd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum2","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"1 1","pages":"4 pp.-59"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88850549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609524
Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp
Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height
{"title":"Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018","authors":"Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp","doi":"10.1109/IEDM.2005.1609524","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609524","url":null,"abstract":"Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"972-975"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90376205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609406
N. Wu, Qingchun Zhang, Chunxiang Zhu, C. Shen, M. Li, D. Chan, N. Balasubramanian
High performance Ge p- and n-MOSFETs with CVD HfO2 gate dielectric were fabricated. Charge trapping and Vth instability were investigated systematically for the first time for Ge MOSFET with different surface treatments (silicon passivation and surface nitridation) and compared to the Si devices. Our results show that: (1) Ge devices with silicon passivation yield better electrical performance and reliability than those with surface nitridation; (2) Ge transistors with silicon passivation exhibit less NBTI degradation than the silicon counterparts; probably due to the larger hole barrier in Ge/dielectric than in Si/dielectric; and (3) PBTI degradation of the Ge transistors is more severe than the silicon devices, which imposes an important reliability issue for Ge CMOS applications
{"title":"BTI and charge trapping in germanium p- and n-MOSFETs with CVD HfO/sub 2/ gate dielectric","authors":"N. Wu, Qingchun Zhang, Chunxiang Zhu, C. Shen, M. Li, D. Chan, N. Balasubramanian","doi":"10.1109/IEDM.2005.1609406","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609406","url":null,"abstract":"High performance Ge p- and n-MOSFETs with CVD HfO2 gate dielectric were fabricated. Charge trapping and Vth instability were investigated systematically for the first time for Ge MOSFET with different surface treatments (silicon passivation and surface nitridation) and compared to the Si devices. Our results show that: (1) Ge devices with silicon passivation yield better electrical performance and reliability than those with surface nitridation; (2) Ge transistors with silicon passivation exhibit less NBTI degradation than the silicon counterparts; probably due to the larger hole barrier in Ge/dielectric than in Si/dielectric; and (3) PBTI degradation of the Ge transistors is more severe than the silicon devices, which imposes an important reliability issue for Ge CMOS applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"4 pp.-558"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84784626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609475
Changrok Moon, Jongwan Jung, Doowon Kwon, Seok-Ha Lee, J. Roh, Kee-Hyun Paik, Doo-Cheol Park, Hongki Kim, Heegeun Jeongc, J. Sim, Hyunpil Noh, Kangbok Lee, Duckhyung Lee, Kinam Kim
5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed
{"title":"The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels","authors":"Changrok Moon, Jongwan Jung, Doowon Kwon, Seok-Ha Lee, J. Roh, Kee-Hyun Paik, Doo-Cheol Park, Hongki Kim, Heegeun Jeongc, J. Sim, Hyunpil Noh, Kangbok Lee, Duckhyung Lee, Kinam Kim","doi":"10.1109/IEDM.2005.1609475","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609475","url":null,"abstract":"5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"33 1","pages":"4 pp.-798"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83620002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609471
A. Villanueva, J. D. del Alamo, T. Hisaka, K. Hayashi, M. Somerville
We have studied the electrical degradation of RF power PHEMTs by means of light-emission measurements performed during bias-stress experiments. We show that electrical degradation can proceed in a highly non-uniform manner across the width of the device. We identify the origin of this as a small systematic non-uniformity in the recess geometry that impacts the electric field and the impact ionization rate on the drain of the device. Our research suggests that a close examination of the width distribution of electric field in RF power PHEMTs (and FETs in general) is essential to enhance their long-term reliability
{"title":"Non-uniform degradation behavior across device width in RF power GaAs PHEMTs","authors":"A. Villanueva, J. D. del Alamo, T. Hisaka, K. Hayashi, M. Somerville","doi":"10.1109/IEDM.2005.1609471","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609471","url":null,"abstract":"We have studied the electrical degradation of RF power PHEMTs by means of light-emission measurements performed during bias-stress experiments. We show that electrical degradation can proceed in a highly non-uniform manner across the width of the device. We identify the origin of this as a small systematic non-uniformity in the recess geometry that impacts the electric field and the impact ionization rate on the drain of the device. Our research suggests that a close examination of the width distribution of electric field in RF power PHEMTs (and FETs in general) is essential to enhance their long-term reliability","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"12 1","pages":"783-786"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83563462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609474
K. Itonaga, H. Abe, I. Yoshihara, T. Hirayama
We've realized a 2.5-mum square pixel with high saturation electron capacity and sensitivity, which realizes the low dark current as well as triple Qs value of the conventional STI, by expanding the buried photodiode under the isolation oxide, and the sensitivity gain will be 20% higher using the Cu process than is possible with the Al process
{"title":"A high-performance and low-noise CMOS image sensor with an expanding photodiode under the isolation oxide","authors":"K. Itonaga, H. Abe, I. Yoshihara, T. Hirayama","doi":"10.1109/IEDM.2005.1609474","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609474","url":null,"abstract":"We've realized a 2.5-mum square pixel with high saturation electron capacity and sensitivity, which realizes the low dark current as well as triple Qs value of the conventional STI, by expanding the buried photodiode under the isolation oxide, and the sensitivity gain will be 20% higher using the Cu process than is possible with the Al process","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"67 1","pages":"4 pp.-794"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85837489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609391
T. Sanuki, H. Tanaka, K. Oota, O. Fujii, R. Yamaguchi, K. Nakayama, Y. Morimasa, Y. Takasu, J. Idebuchi, N. Nishiyama, H. Fukui, H. Yoshimura, K. Matsuo, I. Mizushima, H. Ito, Y. Takegawa, M. Saito, M. Iwai, N. Nagashima, F. Matsuoka
For the first time, a novel CMOSFET structure in substrate strained-Si of lang100rang-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by high channel doping. We applied Si selective epitaxial growth on recessed S/D region in SiGe layer, which is effective to induce high tensile stress and reduce S/D resistance. In strained Si NMOS, 15% performance improvement is achieved. Moreover, additive stress by using tensile CESL can further improve the drive current. In strained Si PMOS, 25% performance improvement is achieved in both narrow and wide channel device
{"title":"New stress inducing technique of epitaxial si on recessed S/D fabricated in substrate strained-si of [100]channel on rotated wafers","authors":"T. Sanuki, H. Tanaka, K. Oota, O. Fujii, R. Yamaguchi, K. Nakayama, Y. Morimasa, Y. Takasu, J. Idebuchi, N. Nishiyama, H. Fukui, H. Yoshimura, K. Matsuo, I. Mizushima, H. Ito, Y. Takegawa, M. Saito, M. Iwai, N. Nagashima, F. Matsuoka","doi":"10.1109/IEDM.2005.1609391","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609391","url":null,"abstract":"For the first time, a novel CMOSFET structure in substrate strained-Si of lang100rang-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by high channel doping. We applied Si selective epitaxial growth on recessed S/D region in SiGe layer, which is effective to induce high tensile stress and reduce S/D resistance. In strained Si NMOS, 15% performance improvement is achieved. Moreover, additive stress by using tensile CESL can further improve the drive current. In strained Si PMOS, 25% performance improvement is achieved in both narrow and wide channel device","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"22 1","pages":"501-504"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87415640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609338
Yong-Sung Kim, Sang-Hyeon Lee, S. Shin, Sung-hee Han, Ju-Yong Lee, Jin-woo Lee, J. Han, Seung-Chul Yang, J. Sung, Eujime Lee, B. Song, Dong-jun Lee, D. Bae, Won-suk Yang, Yang-Keun Park, Kyuhyun Lee, B. Roh, Taeyoung Chung, Kinam Kim, Wonshik Lee
We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices
{"title":"Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations","authors":"Yong-Sung Kim, Sang-Hyeon Lee, S. Shin, Sung-hee Han, Ju-Yong Lee, Jin-woo Lee, J. Han, Seung-Chul Yang, J. Sung, Eujime Lee, B. Song, Dong-jun Lee, D. Bae, Won-suk Yang, Yang-Keun Park, Kyuhyun Lee, B. Roh, Taeyoung Chung, Kinam Kim, Wonshik Lee","doi":"10.1109/IEDM.2005.1609338","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609338","url":null,"abstract":"We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"21 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90238543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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