Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609273
Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang
This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations
{"title":"Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations","authors":"Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang","doi":"10.1109/IEDM.2005.1609273","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609273","url":null,"abstract":"This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"24 1","pages":"4 pp.-88"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80513401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609471
A. Villanueva, J. D. del Alamo, T. Hisaka, K. Hayashi, M. Somerville
We have studied the electrical degradation of RF power PHEMTs by means of light-emission measurements performed during bias-stress experiments. We show that electrical degradation can proceed in a highly non-uniform manner across the width of the device. We identify the origin of this as a small systematic non-uniformity in the recess geometry that impacts the electric field and the impact ionization rate on the drain of the device. Our research suggests that a close examination of the width distribution of electric field in RF power PHEMTs (and FETs in general) is essential to enhance their long-term reliability
{"title":"Non-uniform degradation behavior across device width in RF power GaAs PHEMTs","authors":"A. Villanueva, J. D. del Alamo, T. Hisaka, K. Hayashi, M. Somerville","doi":"10.1109/IEDM.2005.1609471","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609471","url":null,"abstract":"We have studied the electrical degradation of RF power PHEMTs by means of light-emission measurements performed during bias-stress experiments. We show that electrical degradation can proceed in a highly non-uniform manner across the width of the device. We identify the origin of this as a small systematic non-uniformity in the recess geometry that impacts the electric field and the impact ionization rate on the drain of the device. Our research suggests that a close examination of the width distribution of electric field in RF power PHEMTs (and FETs in general) is essential to enhance their long-term reliability","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"12 1","pages":"783-786"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83563462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609475
Changrok Moon, Jongwan Jung, Doowon Kwon, Seok-Ha Lee, J. Roh, Kee-Hyun Paik, Doo-Cheol Park, Hongki Kim, Heegeun Jeongc, J. Sim, Hyunpil Noh, Kangbok Lee, Duckhyung Lee, Kinam Kim
5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed
{"title":"The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels","authors":"Changrok Moon, Jongwan Jung, Doowon Kwon, Seok-Ha Lee, J. Roh, Kee-Hyun Paik, Doo-Cheol Park, Hongki Kim, Heegeun Jeongc, J. Sim, Hyunpil Noh, Kangbok Lee, Duckhyung Lee, Kinam Kim","doi":"10.1109/IEDM.2005.1609475","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609475","url":null,"abstract":"5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"33 1","pages":"4 pp.-798"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83620002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609338
Yong-Sung Kim, Sang-Hyeon Lee, S. Shin, Sung-hee Han, Ju-Yong Lee, Jin-woo Lee, J. Han, Seung-Chul Yang, J. Sung, Eujime Lee, B. Song, Dong-jun Lee, D. Bae, Won-suk Yang, Yang-Keun Park, Kyuhyun Lee, B. Roh, Taeyoung Chung, Kinam Kim, Wonshik Lee
We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices
{"title":"Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations","authors":"Yong-Sung Kim, Sang-Hyeon Lee, S. Shin, Sung-hee Han, Ju-Yong Lee, Jin-woo Lee, J. Han, Seung-Chul Yang, J. Sung, Eujime Lee, B. Song, Dong-jun Lee, D. Bae, Won-suk Yang, Yang-Keun Park, Kyuhyun Lee, B. Roh, Taeyoung Chung, Kinam Kim, Wonshik Lee","doi":"10.1109/IEDM.2005.1609338","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609338","url":null,"abstract":"We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"21 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90238543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609406
N. Wu, Qingchun Zhang, Chunxiang Zhu, C. Shen, M. Li, D. Chan, N. Balasubramanian
High performance Ge p- and n-MOSFETs with CVD HfO2 gate dielectric were fabricated. Charge trapping and Vth instability were investigated systematically for the first time for Ge MOSFET with different surface treatments (silicon passivation and surface nitridation) and compared to the Si devices. Our results show that: (1) Ge devices with silicon passivation yield better electrical performance and reliability than those with surface nitridation; (2) Ge transistors with silicon passivation exhibit less NBTI degradation than the silicon counterparts; probably due to the larger hole barrier in Ge/dielectric than in Si/dielectric; and (3) PBTI degradation of the Ge transistors is more severe than the silicon devices, which imposes an important reliability issue for Ge CMOS applications
{"title":"BTI and charge trapping in germanium p- and n-MOSFETs with CVD HfO/sub 2/ gate dielectric","authors":"N. Wu, Qingchun Zhang, Chunxiang Zhu, C. Shen, M. Li, D. Chan, N. Balasubramanian","doi":"10.1109/IEDM.2005.1609406","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609406","url":null,"abstract":"High performance Ge p- and n-MOSFETs with CVD HfO2 gate dielectric were fabricated. Charge trapping and Vth instability were investigated systematically for the first time for Ge MOSFET with different surface treatments (silicon passivation and surface nitridation) and compared to the Si devices. Our results show that: (1) Ge devices with silicon passivation yield better electrical performance and reliability than those with surface nitridation; (2) Ge transistors with silicon passivation exhibit less NBTI degradation than the silicon counterparts; probably due to the larger hole barrier in Ge/dielectric than in Si/dielectric; and (3) PBTI degradation of the Ge transistors is more severe than the silicon devices, which imposes an important reliability issue for Ge CMOS applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"4 pp.-558"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84784626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609301
T. Fujimaki, K. Higashi, N. Nakamura, N. Matsunaga, K. Yoshida, N. Miyawaki, M. Hatano, M. Hasunuma, J. Wada, T. Nishioka, K. Akiyama, H. Kawashima, Y. Enomoto, T. Hasegawa, K. Honda, M. Iwai, S. Yamada, F. Matsuoka
Moisture induced via failure (MIVF) is studied for 45nm interconnect technology using porous low-k films. Test patterns are designed to examine the layout dependence of the MIVF. Some fundamental and important layout dependencies of the via resistance increase are investigated and considered for the first time. It has been found that the MIVF has not been suppressed, even though multiple vias structure is adopted. On the contrary, local wiring pattern density close to via and dummy wiring pattern area size strongly affect via resistance increase. A model with moisture ventilation can successfully explain those layout dependencies. It is confirmed that the MIVF is completely suppressed by the control of dummy pattern layout
{"title":"Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design","authors":"T. Fujimaki, K. Higashi, N. Nakamura, N. Matsunaga, K. Yoshida, N. Miyawaki, M. Hatano, M. Hasunuma, J. Wada, T. Nishioka, K. Akiyama, H. Kawashima, Y. Enomoto, T. Hasegawa, K. Honda, M. Iwai, S. Yamada, F. Matsuoka","doi":"10.1109/IEDM.2005.1609301","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609301","url":null,"abstract":"Moisture induced via failure (MIVF) is studied for 45nm interconnect technology using porous low-k films. Test patterns are designed to examine the layout dependence of the MIVF. Some fundamental and important layout dependencies of the via resistance increase are investigated and considered for the first time. It has been found that the MIVF has not been suppressed, even though multiple vias structure is adopted. On the contrary, local wiring pattern density close to via and dummy wiring pattern area size strongly affect via resistance increase. A model with moisture ventilation can successfully explain those layout dependencies. It is confirmed that the MIVF is completely suppressed by the control of dummy pattern layout","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"183-186"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91128132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609509
R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker
To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO2 in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO2 C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO2 C/L as a part of the gate oxide. Field effect mobility (muFE) for electrons and holes of 510 cm2/Vs and of 210 cm2/Vs were obtained respectively
{"title":"High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer","authors":"R. Vikas, R. Ishihara, Y. Hiroshima, D. Abe, S. Inoue, T. Shimoda, J. Metselaar, C. Beenakker","doi":"10.1109/IEDM.2005.1609509","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609509","url":null,"abstract":"To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO<sub>2</sub> in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO<sub>2</sub> C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO<sub>2</sub> C/L as a part of the gate oxide. Field effect mobility (mu<sub>FE</sub>) for electrons and holes of 510 cm<sup>2</sup>/Vs and of 210 cm<sup>2</sup>/Vs were obtained respectively","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"29 1","pages":"919-922"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76936628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609284
H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki
On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the world's first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz
的基础上制造一个CPU的玻璃作为数字电路在b .李et al。(2003)和t . Ikeda et al。(2004),以及灵活的CPU使用TFT转移的制造技术提出了t .高山et al .(2004),我们已经成功地开发的世界上第一个灵活RFCPUs(8位、被动类型)通过添加CPU天线,一个模拟电路,一个加密函数和一个射频识别功能,使用频率为13.56兆赫的射频信号运作
{"title":"RFCPUs on glass and plastic substrates fabricated by TFT transfer technology","authors":"H. Dembo, Y. Kurokawa, T. Ikeda, S. Iwata, K. Ohshima, J. Ishii, T. Tsurume, E. Sugiyama, D. Yamada, A. Isobe, S. Saito, K. Dairiki, N. Kusumoto, Y. Shionoiri, T. Atsumi, M. Fujita, H. Kobayashi, H. Takashina, Y. Yamashita, S. Yamazaki","doi":"10.1109/IEDM.2005.1609284","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609284","url":null,"abstract":"On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the world's first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"70 1","pages":"125-127"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77389627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609359
J. Suñé, E. Wu
The mechanisms of hydrogen release (HR) involved in the degradation and breakdown (BD) of SiO2-based gate dielectrics are studied by means of the analysis of charge to breakdown (QBD ) data versus electron energy, and comparing with scanning tunneling microscope (STM) experiments of H desorption from silicon surfaces. Our results reveal an important role of vibrational and electronic excitation mechanisms
{"title":"Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides","authors":"J. Suñé, E. Wu","doi":"10.1109/IEDM.2005.1609359","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609359","url":null,"abstract":"The mechanisms of hydrogen release (HR) involved in the degradation and breakdown (BD) of SiO2-based gate dielectrics are studied by means of the analysis of charge to breakdown (QBD ) data versus electron energy, and comparing with scanning tunneling microscope (STM) experiments of H desorption from silicon surfaces. Our results reveal an important role of vibrational and electronic excitation mechanisms","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"388-391"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74040883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609389
K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo
This paper reports a novel technique to fabricate uniaxial compressive strained p-channel transistors with silicon-germanium (SiGe) source and drain (S/D) stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in silicon-on-insulator (SOI) P-MOSFETs with a gate length LG of 90 nm. Drive current IDsat enhancement of up to 35% was observed
本文报道了一种用硅锗(SiGe)源极和漏极(S/D)应力源制备单轴压缩应变p沟道晶体管的新技术。该工艺涉及选择性生长的SiGe区域的局部Ge凝聚，从而将Ge驱动到晶体管沟道附近的源极和漏极区域并使其浓度增加。该工艺特别适用于超薄体(UTB)晶体管，因为它在SiGe外延之前消除了对Si凹槽蚀刻的需要。此外，对于UTB结构，Ge冷凝所需的热预算并不令人望而却步。在S/D区域可以实现高Ge摩尔分数，从而导致晶体管通道中更高的应变水平。我们在栅极长度LG为90 nm的绝缘体上硅(SOI) p - mosfet中证明了该技术的可行性。观察到驱动电流IDsat增强高达35%
{"title":"Source/drain germanium condensation for p-channel strained ultra-thin body transistors","authors":"K. Chui, K. Ang, A. Madan, Huiqi Wang, C. Tung, L. Wong, Yihua Wang, S. Choy, N. Balasubramanian, M. Li, G. Samudra, Y. Yeo","doi":"10.1109/IEDM.2005.1609389","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609389","url":null,"abstract":"This paper reports a novel technique to fabricate uniaxial compressive strained p-channel transistors with silicon-germanium (SiGe) source and drain (S/D) stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in silicon-on-insulator (SOI) P-MOSFETs with a gate length LG of 90 nm. Drive current IDsat enhancement of up to 35% was observed","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"219 1","pages":"493-496"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75689596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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