Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609400
N. Pimparkar, Jing Guo, M. A. Alam
Nanobundle network transistors (NBTs) have emerged as a viable, higher performance alternative to poly-silicon and organic transistors with possible applications in macroelectronic displays, chemical/biological sensors, and photovoltaics. A simple analytical model for I-V characteristics of NBTs (below the percolation limit) is proposed and validated by numerical simulation and experimental data. The physics-based predictive model provides a simple relation between transistor characteristics and design parameters which can be used for optimization of NBTs. The model provides important insights into the recent experiments on NBT characteristics and electrical purification of nanobundle networks
{"title":"Performance assessment of sub-percolating nanobundle network transistors by an analytical model","authors":"N. Pimparkar, Jing Guo, M. A. Alam","doi":"10.1109/IEDM.2005.1609400","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609400","url":null,"abstract":"Nanobundle network transistors (NBTs) have emerged as a viable, higher performance alternative to poly-silicon and organic transistors with possible applications in macroelectronic displays, chemical/biological sensors, and photovoltaics. A simple analytical model for I-V characteristics of NBTs (below the percolation limit) is proposed and validated by numerical simulation and experimental data. The physics-based predictive model provides a simple relation between transistor characteristics and design parameters which can be used for optimization of NBTs. The model provides important insights into the recent experiments on NBT characteristics and electrical purification of nanobundle networks","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"16 1","pages":"534-537"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89965658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609291
Seong-Dong Kim, S. Narasimha, K. Rim
A new integrated methodology for the accurate extraction of source/drain (S/D) series resistance components with emphasis on the spreading and contact resistance elements is presented. For the first time, detailed extractions of lateral extension doping abruptness and silicide specific contact resistance are made directly from 90nm-node SOI MOSFET characterization. The spreading resistance due to the lateral doping gradient is found to be a key component contributing to total parasitics, and the doping gradient engineering and scaling of specific contact resistance must be employed to overcome this parasitic limitation in future nanoscale CMOS performance roadmap
{"title":"An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs","authors":"Seong-Dong Kim, S. Narasimha, K. Rim","doi":"10.1109/IEDM.2005.1609291","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609291","url":null,"abstract":"A new integrated methodology for the accurate extraction of source/drain (S/D) series resistance components with emphasis on the spreading and contact resistance elements is presented. For the first time, detailed extractions of lateral extension doping abruptness and silicide specific contact resistance are made directly from 90nm-node SOI MOSFET characterization. The spreading resistance due to the lateral doping gradient is found to be a key component contributing to total parasitics, and the doping gradient engineering and scaling of specific contact resistance must be employed to overcome this parasitic limitation in future nanoscale CMOS performance roadmap","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"8 1","pages":"149-152"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86618386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609528
K. Shin, C. O. Chui, T. King
3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance
{"title":"Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology","authors":"K. Shin, C. O. Chui, T. King","doi":"10.1109/IEDM.2005.1609528","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609528","url":null,"abstract":"3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"120 1","pages":"988-991"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87930141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609361
E. Wu, J. Suñé, W. Lai, A. Vayshenker, D. Harmon
Breakdown (BD) characteristics and electron transport across thin SiO2 films has been thoroughly investigated for P+Poly-Si gate/PFET devices stressed under inversion mode. We resolve the anomalies in TBD/QBD polarity dependence and shallower Weibull slopes commonly observed in PFET for TOX>2nm. For thin oxides (1.8nmOX<2.9nm), QBD data and Weibull slopes are found to be in excellent agreement with those of NFETs by considering valence-band electron tunneling. For ultra-thin oxides (T OX<1.8nm), using an improved new BD detection methodology, the derived QBD results show reasonable agreement with those of thick oxides
{"title":"A comprehensive investigation of gate oxide breakdown of P+Poly/PFETs under inversion mode","authors":"E. Wu, J. Suñé, W. Lai, A. Vayshenker, D. Harmon","doi":"10.1109/IEDM.2005.1609361","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609361","url":null,"abstract":"Breakdown (BD) characteristics and electron transport across thin SiO<sub>2</sub> films has been thoroughly investigated for P+Poly-Si gate/PFET devices stressed under inversion mode. We resolve the anomalies in T<sub>BD</sub>/Q<sub>BD</sub> polarity dependence and shallower Weibull slopes commonly observed in PFET for T<sub>OX</sub>>2nm. For thin oxides (1.8nm<T<sub>OX</sub><2.9nm), Q<sub>BD</sub> data and Weibull slopes are found to be in excellent agreement with those of NFETs by considering valence-band electron tunneling. For ultra-thin oxides (T <sub>OX</sub><1.8nm), using an improved new BD detection methodology, the derived Q<sub>BD</sub> results show reasonable agreement with those of thick oxides","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"57 1","pages":"396-399"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76420636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609439
T. Doorn, M. Altheimer
New insights in the programming physics of silicided polysilicon fuses integrated in 90 nm CMOS have led to a programming time of 100 ns, while achieving a resistance increase of 107. This is an order of magnitude better than any previously published result for the programming time and resistance increase individually. Simple calculations and TEM-analyses substantiate the proposed programming mechanism. The advantage of a rectangular fuse head over a tapered fuse head is shown and explained
{"title":"Ultra-fast programming of silicided polysilicon fuses based on new insights in the programming physics","authors":"T. Doorn, M. Altheimer","doi":"10.1109/IEDM.2005.1609439","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609439","url":null,"abstract":"New insights in the programming physics of silicided polysilicon fuses integrated in 90 nm CMOS have led to a programming time of 100 ns, while achieving a resistance increase of 107. This is an order of magnitude better than any previously published result for the programming time and resistance increase individually. Simple calculations and TEM-analyses substantiate the proposed programming mechanism. The advantage of a rectangular fuse head over a tapered fuse head is shown and explained","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"49 1","pages":"667-670"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79924656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609460
A. Redaelli, D. Ielmini, A. Lacaita, F. Pellizzer, A. Pirovano, R. Bez
The stochastic nature of percolation is shown as a possible issue for retention in PCM devices, due to the occurrence of unlikely crystallization events that early decrease the device resistance. Failure time dispersions at high temperatures are measured and analyzed through a crystallization Monte Carlo model. A physical insight into nucleation and growth mechanisms is thus provided and a maximum working temperature of 105degC is extracted to guarantee, on large statistics, the 10 years data retention requirement for non volatile applications
{"title":"Impact of crystallization statistics on data retention for phase change memories","authors":"A. Redaelli, D. Ielmini, A. Lacaita, F. Pellizzer, A. Pirovano, R. Bez","doi":"10.1109/IEDM.2005.1609460","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609460","url":null,"abstract":"The stochastic nature of percolation is shown as a possible issue for retention in PCM devices, due to the occurrence of unlikely crystallization events that early decrease the device resistance. Failure time dispersions at high temperatures are measured and analyzed through a crystallization Monte Carlo model. A physical insight into nucleation and growth mechanisms is thus provided and a maximum working temperature of 105degC is extracted to guarantee, on large statistics, the 10 years data retention requirement for non volatile applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"54 1","pages":"742-745"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88420228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609429
H. Yu, J.D. Chen, M. Li, S.J. Lee, D. Kwong, M. V. van Dal, J. Kittl, A. Lauwers, E. Augendre, S. Kubicek, C. Zhao, H. Bender, B. Brijs, L. Geenen, A. Benedetti, P. Absil, M. Jurczak, S. Biesemans
The key result in this work is the experimental demonstration that adding Yb to Ni FUSI allows for tuning the work function (WF) from midgap (NiSi ~4.72 eV) to n-type band-edge (~4.22 eV) on thin SiON, maintaining same EOT. In addition, we did not observe any interface adhesion issues found in other reports when WF is modulated by dopants such as As or Sb. We also show that reliability is similar to Ni FUSI. This is a promising technique for nFET gate electrode formation and enables dual gate CMOS technologies for 45 nm and beyond in a manufacturable way
{"title":"Modulation of the Ni FUSI workfunction by Yb doping: from midgap to n-type band-edge","authors":"H. Yu, J.D. Chen, M. Li, S.J. Lee, D. Kwong, M. V. van Dal, J. Kittl, A. Lauwers, E. Augendre, S. Kubicek, C. Zhao, H. Bender, B. Brijs, L. Geenen, A. Benedetti, P. Absil, M. Jurczak, S. Biesemans","doi":"10.1109/IEDM.2005.1609429","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609429","url":null,"abstract":"The key result in this work is the experimental demonstration that adding Yb to Ni FUSI allows for tuning the work function (WF) from midgap (NiSi ~4.72 eV) to n-type band-edge (~4.22 eV) on thin SiON, maintaining same EOT. In addition, we did not observe any interface adhesion issues found in other reports when WF is modulated by dopants such as As or Sb. We also show that reliability is similar to Ni FUSI. This is a promising technique for nFET gate electrode formation and enables dual gate CMOS technologies for 45 nm and beyond in a manufacturable way","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"46 1","pages":"630-633"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77223483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609421
A. Rahman, Gerhard Klimeck, M. Lundstrom
Performance limits of unstrained n- and p- MOSFETs with Si, Ge, GaAs and InAs channel materials are investigated using a 20 band sp3d5s*-SO semi-empirical atomistic tight-binding model and a top-of-the-barrier seminumerical ballistic transport model. It is observed that although the deeply scaled III-V devices offer very high electron injection velocities, their very low conduction band density-of-states strongly degrades their performance. Due to the high density-of-states for both electrons and holes in Ge, nanoscale devices with Ge as channel material are found to outperform all other materials considered
{"title":"Novel channel materials for ballistic nanoscale MOSFETs-bandstructure effects","authors":"A. Rahman, Gerhard Klimeck, M. Lundstrom","doi":"10.1109/IEDM.2005.1609421","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609421","url":null,"abstract":"Performance limits of unstrained n- and p- MOSFETs with Si, Ge, GaAs and InAs channel materials are investigated using a 20 band sp3d5s*-SO semi-empirical atomistic tight-binding model and a top-of-the-barrier seminumerical ballistic transport model. It is observed that although the deeply scaled III-V devices offer very high electron injection velocities, their very low conduction band density-of-states strongly degrades their performance. Due to the high density-of-states for both electrons and holes in Ge, nanoscale devices with Ge as channel material are found to outperform all other materials considered","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"26 1","pages":"4 pp.-604"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77616351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609401
A. Visconti, W. Tonti
{"title":"CMOS and interconnect reliability process and electrical degradation in flash memories and performance boosted CMOS devices","authors":"A. Visconti, W. Tonti","doi":"10.1109/IEDM.2005.1609401","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609401","url":null,"abstract":"","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"34 1","pages":"538-538"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86978302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-05DOI: 10.1109/IEDM.2005.1609317
Sungjae Lee, L. Wagner, B. Jagannathan, S. Csutak, J. Pekarik, M. Breitwisch, R. Ramachandran, G. Freeman
We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance. The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX. A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET. A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz
{"title":"Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies","authors":"Sungjae Lee, L. Wagner, B. Jagannathan, S. Csutak, J. Pekarik, M. Breitwisch, R. Ramachandran, G. Freeman","doi":"10.1109/IEDM.2005.1609317","DOIUrl":"https://doi.org/10.1109/IEDM.2005.1609317","url":null,"abstract":"We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance. The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX. A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET. A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"2001 1","pages":"241-244"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88912590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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