Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1
K. Becker, S. Voges, P. Fruehauf, M. Heimann, S. Nerreter, R. Blank, M. Erdmann, S. Gottwald, A. Hofmeister, M. Hesse, M. Thies, S. Mehrafsun, R. Fust, E. Beck, J. Pawlikowski, B. Schröder, C. Voight, T. Braun, M. Schneider-Ramelow
Digitization is one of the hot topics in all Industry 4.0 efforts that are currently discussed. Often the focus is on digitization of business processes with a financial/organizational perspective on manufacturing, so the tools are adapting to enterprise resource planning [ERP] and manufacturing execution system [MES] rather than on actual manufacturing issues on the shop floor. Within the SiEvEI 4.0 project, a research consortium from the area of electronics manufacturing is working on digitization for a manufacturing scenario where high value electronic goods are built in a distributed manufacturing environment. The key research topics addressed are the implementation of a Chain of Trust [CoT] for such a distributed manufacturing, i.e. and the application of artificial intelligence/machine learning to analyze and eventually optimize manufacturing processes. The paper will introduce the concept of both COT and AI-based process analysis that will later on transferred into a microelectronics production environment. Two reference processes are targeted, SMD assembly using fully automated manufacturing equipment and Solder Ball Application using a high-mix/low volume concept. As a result, the paper presents a concept of how to digitize manufacturing processes and use this digital description of a process combination to make a distributed manufacturing flow safe and increase product/process quality.
{"title":"Implementation of Trusted Manufacturing & AI-based process optimization into microelectronic manufacturing research environments","authors":"K. Becker, S. Voges, P. Fruehauf, M. Heimann, S. Nerreter, R. Blank, M. Erdmann, S. Gottwald, A. Hofmeister, M. Hesse, M. Thies, S. Mehrafsun, R. Fust, E. Beck, J. Pawlikowski, B. Schröder, C. Voight, T. Braun, M. Schneider-Ramelow","doi":"10.4071/1085-8024-2021.1","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1","url":null,"abstract":"\u0000 Digitization is one of the hot topics in all Industry 4.0 efforts that are currently discussed. Often the focus is on digitization of business processes with a financial/organizational perspective on manufacturing, so the tools are adapting to enterprise resource planning [ERP] and manufacturing execution system [MES] rather than on actual manufacturing issues on the shop floor. Within the SiEvEI 4.0 project, a research consortium from the area of electronics manufacturing is working on digitization for a manufacturing scenario where high value electronic goods are built in a distributed manufacturing environment. The key research topics addressed are the implementation of a Chain of Trust [CoT] for such a distributed manufacturing, i.e. and the application of artificial intelligence/machine learning to analyze and eventually optimize manufacturing processes.\u0000 The paper will introduce the concept of both COT and AI-based process analysis that will later on transferred into a microelectronics production environment. Two reference processes are targeted, SMD assembly using fully automated manufacturing equipment and Solder Ball Application using a high-mix/low volume concept.\u0000 As a result, the paper presents a concept of how to digitize manufacturing processes and use this digital description of a process combination to make a distributed manufacturing flow safe and increase product/process quality.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"92 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83809655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000060
Alice Guerrero, P. Bex, A. Jones, A. Southard, Daojie Dong, A. Phommahaxay, E. Beyne
Process flows for memory stacking or other heterogeneous integration schemes benefit from die bonding on a thinned silicon wafer 100 μm or less. In scenarios where a thinned device wafer contains features such as microbumps or Cu pillars, a carrier and temporary bonding material (TBM) facilitate the support of the fragile landing wafer during thermocompression bonding (TCB). The landing wafer in this case is vulnerable to deformations including loss of die planarity, Si bulging, Si or low k dielectric cracking, and damage to the underlying device wafer topography. In this paper, a dual layer system for temporary bonding is presented that maintains the integrity of a thinned device wafer during and after TCB. This is achieved with TBM materials which do not reflow at typical TCB conditions. The approach is to simulate TCB conditions which demonstrate the performance between different underlying TBM materials. A method which tracks the bond head z-axis over time during a TCB cycle is described which in turn yields information on the degree of temporary substrate deformation due to TCB force and temperature. The experiments include a worst-case scenario of multiple TCB cycles in the same position to mimic multi-die stacking. Finally, the impact of process conditions on Cu pillars with solder caps embedded in a thinned wafer bond line will be discussed.
{"title":"Prevention of thinned wafer deformation during thermocompression bonding and multi-die stacking supported by temporary bonding materials","authors":"Alice Guerrero, P. Bex, A. Jones, A. Southard, Daojie Dong, A. Phommahaxay, E. Beyne","doi":"10.4071/1085-8024-2021.1.000060","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000060","url":null,"abstract":"\u0000 Process flows for memory stacking or other heterogeneous integration schemes benefit from die bonding on a thinned silicon wafer 100 μm or less. In scenarios where a thinned device wafer contains features such as microbumps or Cu pillars, a carrier and temporary bonding material (TBM) facilitate the support of the fragile landing wafer during thermocompression bonding (TCB). The landing wafer in this case is vulnerable to deformations including loss of die planarity, Si bulging, Si or low k dielectric cracking, and damage to the underlying device wafer topography.\u0000 In this paper, a dual layer system for temporary bonding is presented that maintains the integrity of a thinned device wafer during and after TCB. This is achieved with TBM materials which do not reflow at typical TCB conditions. The approach is to simulate TCB conditions which demonstrate the performance between different underlying TBM materials. A method which tracks the bond head z-axis over time during a TCB cycle is described which in turn yields information on the degree of temporary substrate deformation due to TCB force and temperature. The experiments include a worst-case scenario of multiple TCB cycles in the same position to mimic multi-die stacking. Finally, the impact of process conditions on Cu pillars with solder caps embedded in a thinned wafer bond line will be discussed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"451 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82925992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000328
S. Murali, L. Wan, Dhayalan Mariyappan, Lim Yee Weon Evonne, Kang Sungsig SS
Developments in bonding wire focus on coated silver wire for stacked devices in memory sectors revealing near equivalent performances to 4N Au wire. In addition to stacked device applications, the wire is also examined for other conventional applications. The innovative wire exhibits excellent performance on biased Highly Accelerated Stress Test (bHAST) passing 192h and 504h at 130°C, 85%RH for +3.3V and +20V, respectively. Thus, the wire satisfied one of the important criteria required to pass automotive reliability test (2X stress test, AEC Q100 Rev-H, with limited test samples). The test is conducted using 0.8mil coated silver wire and molded with green epoxy molding compound. Another benefit of the wire is stitch bond bondability with high MTBA of greater than 2h.
{"title":"Distribution of Coated Metal Layer on Free Air Ball (FAB) Surface","authors":"S. Murali, L. Wan, Dhayalan Mariyappan, Lim Yee Weon Evonne, Kang Sungsig SS","doi":"10.4071/1085-8024-2021.1.000328","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000328","url":null,"abstract":"\u0000 Developments in bonding wire focus on coated silver wire for stacked devices in memory sectors revealing near equivalent performances to 4N Au wire. In addition to stacked device applications, the wire is also examined for other conventional applications. The innovative wire exhibits excellent performance on biased Highly Accelerated Stress Test (bHAST) passing 192h and 504h at 130°C, 85%RH for +3.3V and +20V, respectively. Thus, the wire satisfied one of the important criteria required to pass automotive reliability test (2X stress test, AEC Q100 Rev-H, with limited test samples). The test is conducted using 0.8mil coated silver wire and molded with green epoxy molding compound. Another benefit of the wire is stitch bond bondability with high MTBA of greater than 2h.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"56 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84547840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000256
H. Seppänen, Siang Tat Chua, Joel Elizondo Martinez, Pedro Villa
K&S developed and tested the Advanced Process Diagnostics (APD) algorithm to classify bonding outliers in ultrasonic wire bond production. APD is a software feature, part of Kulicke & Soffa wedge bonders to measure and analyze process signals and detect and classify bond outliers. APD helps bonder operators, production supervisors and process engineers to detect process deviations and fix the underlying root causes. APD measures bond signals, such as deformation, ultrasonic current and ultrasonic frequency. Bonds are automatically divided into subgroups based on bond order and process parameters and the signals within a subgroup are then normalized. For outlier classification, the features are extracted from the normalized signals and combined into failure class values. The failure classes, such as contamination, misaligned wire and unstable substrate, are calculated independently. Within the APD feature, a user can define limits for the failure class values and define bonder actions based on the severity of the detected outlier. We measured the detection rates for large wire Al bond failure classes and demonstrate how APD calculates failure class values from the signals. Additionally, we show how new signal features and failure classes can be defined to detect production specific or rare failure classes. Finally, we present outlier classification performance metrics against large production data sets.
{"title":"Ultrasonic Wire Bond Outlier Classification","authors":"H. Seppänen, Siang Tat Chua, Joel Elizondo Martinez, Pedro Villa","doi":"10.4071/1085-8024-2021.1.000256","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000256","url":null,"abstract":"K&S developed and tested the Advanced Process Diagnostics (APD) algorithm to classify bonding outliers in ultrasonic wire bond production. APD is a software feature, part of Kulicke & Soffa wedge bonders to measure and analyze process signals and detect and classify bond outliers. APD helps bonder operators, production supervisors and process engineers to detect process deviations and fix the underlying root causes. APD measures bond signals, such as deformation, ultrasonic current and ultrasonic frequency. Bonds are automatically divided into subgroups based on bond order and process parameters and the signals within a subgroup are then normalized. For outlier classification, the features are extracted from the normalized signals and combined into failure class values. The failure classes, such as contamination, misaligned wire and unstable substrate, are calculated independently. Within the APD feature, a user can define limits for the failure class values and define bonder actions based on the severity of the detected outlier. We measured the detection rates for large wire Al bond failure classes and demonstrate how APD calculates failure class values from the signals. Additionally, we show how new signal features and failure classes can be defined to detect production specific or rare failure classes. Finally, we present outlier classification performance metrics against large production data sets.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"51 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89577546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000142
Ralf Schmidt, Jens Palm, J. Knaup
Heterogeneous integration is considered as the key technology to create large, complex System in Package (SiP) assemblies of separately manufactured, smaller components. Proper control of the uniformity of each process step constitutes one of the main challenges during integration of the different components into a higher-level assembly. In this context, processes that create thick layers by electrochemical deposition are especially susceptible to variations across the substrate. Such processes include copper pillar and bump as well as tin-silver applications. Insufficient coplanarity of electrolytic copper would result in significant reliability issues or evolution of stress in the package. Upcoming hybrid bump designs with features of different dimensions pose additional challenges to the electrolytic copper and tin-silver processes. Purposeful adjustment of differences between the heights of pillars of different diameters may be required after the copper process step in order to obtain the best uniformity for the complete stack with tin-silver on top. In addition to coplanarity, the electrolytic process should allow modification shape of the individual pillar or bump. In this context, a versatile copper electrodeposition process will be discussed that allows adjustment to a broad variety of uniformity parameters and combinations thereof. In combination with suitable tin-silver deposition processes, this process is expected to significantly improve the reliability of copper pillars and bumps for advanced packaging applications.
{"title":"The Pivotal Role of Uniformity of Electrolytic Deposition Processes to Improve the Reliability of Advanced Packaging","authors":"Ralf Schmidt, Jens Palm, J. Knaup","doi":"10.4071/1085-8024-2021.1.000142","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000142","url":null,"abstract":"\u0000 Heterogeneous integration is considered as the key technology to create large, complex System in Package (SiP) assemblies of separately manufactured, smaller components. Proper control of the uniformity of each process step constitutes one of the main challenges during integration of the different components into a higher-level assembly. In this context, processes that create thick layers by electrochemical deposition are especially susceptible to variations across the substrate. Such processes include copper pillar and bump as well as tin-silver applications. Insufficient coplanarity of electrolytic copper would result in significant reliability issues or evolution of stress in the package. Upcoming hybrid bump designs with features of different dimensions pose additional challenges to the electrolytic copper and tin-silver processes. Purposeful adjustment of differences between the heights of pillars of different diameters may be required after the copper process step in order to obtain the best uniformity for the complete stack with tin-silver on top. In addition to coplanarity, the electrolytic process should allow modification shape of the individual pillar or bump. In this context, a versatile copper electrodeposition process will be discussed that allows adjustment to a broad variety of uniformity parameters and combinations thereof. In combination with suitable tin-silver deposition processes, this process is expected to significantly improve the reliability of copper pillars and bumps for advanced packaging applications.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72722840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000244
N. Watanabe, Hiroshi Yamamoto, Takahiko Mitsui, E. Yamamoto
This study examines the impact of the bonding sequence on the contact resistance in the hybrid bonding of a via-middle Cu though-silicon via (TSV) wafer. Hybrid bonding was performed at room temperature via a surface-activated bonding method using an ultrathin Si film. Comparative study of various bonding sequences revealed that the (a) cleaning of the target Si, via-middle TSV, and Cu electrode wafers with an Ar fast atom beam (FAB), (b) transferring of the Cu electrode wafer into another chamber during cleaning of the via-middle TSV wafer, and (c) transferring of the via-middle TSV wafer to another chamber while cleaning the Cu electrode wafer were all effective in decreasing the oxygen atoms in the bonding interface (amorphous Si layer) and reducing the contact resistances between the TSVs and Cu electrodes.
{"title":"Impact of Bonding Sequence on Contact Resistance in Hybrid Bonding of Via-middle TSV Wafer","authors":"N. Watanabe, Hiroshi Yamamoto, Takahiko Mitsui, E. Yamamoto","doi":"10.4071/1085-8024-2021.1.000244","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000244","url":null,"abstract":"\u0000 This study examines the impact of the bonding sequence on the contact resistance in the hybrid bonding of a via-middle Cu though-silicon via (TSV) wafer. Hybrid bonding was performed at room temperature via a surface-activated bonding method using an ultrathin Si film. Comparative study of various bonding sequences revealed that the (a) cleaning of the target Si, via-middle TSV, and Cu electrode wafers with an Ar fast atom beam (FAB), (b) transferring of the Cu electrode wafer into another chamber during cleaning of the via-middle TSV wafer, and (c) transferring of the via-middle TSV wafer to another chamber while cleaning the Cu electrode wafer were all effective in decreasing the oxygen atoms in the bonding interface (amorphous Si layer) and reducing the contact resistances between the TSVs and Cu electrodes.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"2946 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86525963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000045
H. Matsui
New lithography method will be proposed in the paper to enhance resolution limit by half of current one while keeping depth of focus at the same value. The method is based on lithography and copper plating process in order to be applicable to advanced packaging manufacturing.
{"title":"Novel lithography technology for enhancing resolution limit at advanced packaging manufacturing","authors":"H. Matsui","doi":"10.4071/1085-8024-2021.1.000045","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000045","url":null,"abstract":"\u0000 New lithography method will be proposed in the paper to enhance resolution limit by half of current one while keeping depth of focus at the same value. The method is based on lithography and copper plating process in order to be applicable to advanced packaging manufacturing.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"65 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86091220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000011
A. Gaab, Christian J. Wagner, Priyanka Khera
Laser-based dicing of glass wafers for up to 300 mm diameter provides a high quality as well as a high throughput solution for dicing of glass-based products. This technology can be applied to glass wafers for Microfluidic, ME(O)MS and other semiconductor applications as for sensor cover glasses. Based on a die per wafer calculation and nominal processing speeds for laser and breaking technologies, a wafer per hour performance for small dies can be calculated. e.g. for a 3 mm square die design on a 300 mm diameter wafers, a dicing takt of ~10 wafers per hours can be expected. Exemplary investigations of a Corning® HPFS® Fused Silica (HPFS) glass wafer demonstrate the exceptional performance for chipping and edge quality and provide a quality, where the chipping performance is better than 50 μm with very precise edges and die corners.
{"title":"Throughput and Material Utilization by Glass Wafer Laser Dicing","authors":"A. Gaab, Christian J. Wagner, Priyanka Khera","doi":"10.4071/1085-8024-2021.1.000011","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000011","url":null,"abstract":"\u0000 Laser-based dicing of glass wafers for up to 300 mm diameter provides a high quality as well as a high throughput solution for dicing of glass-based products. This technology can be applied to glass wafers for Microfluidic, ME(O)MS and other semiconductor applications as for sensor cover glasses.\u0000 Based on a die per wafer calculation and nominal processing speeds for laser and breaking technologies, a wafer per hour performance for small dies can be calculated. e.g. for a 3 mm square die design on a 300 mm diameter wafers, a dicing takt of ~10 wafers per hours can be expected.\u0000 Exemplary investigations of a Corning® HPFS® Fused Silica (HPFS) glass wafer demonstrate the exceptional performance for chipping and edge quality and provide a quality, where the chipping performance is better than 50 μm with very precise edges and die corners.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"10 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77704630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000154
T. Smith, Bill Rhyne, Rob Reid, Christopher Hatfield
This paper presents the development of a new type of hermetic cavity package for mmWave RF MMICs. The package features an all copper additively manufactured construction for optimal thermal performance as well as low loss air coax RF signal routing with a critical ceramic feedthrough to isolate the internals of the package from the external environment. With a simulated thermal resistance of 1 C/W, from die backside to package lid, and RF insertion loss of less than 0.5dB from 0–80Ghz, this package can support high power as well as high frequency MMICS. With no polymers in the construction of the package true hermetic performance is expected, making this package a high reliability option as well. For this paper two die were selected for demo packages. These die do not have surface mountable packages offered on the market. The die selected are the CMD247 30–40GHz Low Phase Noise Amplifier from Qorvo and the CHA2080-98F 71–86GHz Low Noise Amplifier from United Monolithic Semiconductors. RF insertion loss as well as environmental reliability will be demonstrated with these devices. The additive manufacturing process used is the proprietary PolyStrata® process developed by Nuvotronics. With the development of 14” panel substrate manufacturing line utilizing a mask-less process, fabrication process can support both high-volume, and high-customization without incurring prohibitive tooling costs.
{"title":"High Frequency, Low Loss, Additively Manufactured Hermetic Package","authors":"T. Smith, Bill Rhyne, Rob Reid, Christopher Hatfield","doi":"10.4071/1085-8024-2021.1.000154","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000154","url":null,"abstract":"\u0000 This paper presents the development of a new type of hermetic cavity package for mmWave RF MMICs. The package features an all copper additively manufactured construction for optimal thermal performance as well as low loss air coax RF signal routing with a critical ceramic feedthrough to isolate the internals of the package from the external environment. With a simulated thermal resistance of 1 C/W, from die backside to package lid, and RF insertion loss of less than 0.5dB from 0–80Ghz, this package can support high power as well as high frequency MMICS. With no polymers in the construction of the package true hermetic performance is expected, making this package a high reliability option as well.\u0000 For this paper two die were selected for demo packages. These die do not have surface mountable packages offered on the market. The die selected are the CMD247 30–40GHz Low Phase Noise Amplifier from Qorvo and the CHA2080-98F 71–86GHz Low Noise Amplifier from United Monolithic Semiconductors. RF insertion loss as well as environmental reliability will be demonstrated with these devices. The additive manufacturing process used is the proprietary PolyStrata® process developed by Nuvotronics. With the development of 14” panel substrate manufacturing line utilizing a mask-less process, fabrication process can support both high-volume, and high-customization without incurring prohibitive tooling costs.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"6 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78528413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000089
D. Hackler, E. Prack
With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.
{"title":"Advanced Protected Fan-In WLCSP","authors":"D. Hackler, E. Prack","doi":"10.4071/1085-8024-2021.1.000089","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000089","url":null,"abstract":"\u0000 With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81551701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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