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Enhancing the Paste Release on 55μm pads with Water-Soluble Type 7 SAC305 Solder Paste for High Density SIP Application 用于高密度SIP应用的水溶性7型SAC305锡膏提高55μm焊盘的释出度
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000239
B. Senthil Kumar, Zhang Rui Fen, Yam, Lip Huei, Zhang HanWen, Kang Sungsig, Chan Li-san
The ultra-fine SAC305 solder is widely used as the lead-free solder composition for interconnection in advanced packaging based on its advantages such as good joint strength, thermo-mechanical fatigue behavior and creep resistance. Stencil printing remains the technology of choice for system-in-package (SiP) assembly because of its benefits such as economy of usage, ease of process control, flexibility of usage and fast and wide range of process window. SiP involves the high-level integration of different components, Copper (Cu) pillar flip-chip dies and chips in one package to achieve multiple functions in one system. The need to accommodate ever increasing demand for reduced footprints requires the technology to constantly invent a range of Cu pillar 55μm diameter and smaller components. Many mobile communications SiP consist of 6 or more flip chips in a single package. Conventional flip-chip attach uses flux & Cu pillar solder cap for solder joint formation as it is challenging for solder paste to be printed on fine geometries below 70μm. Additional benefits of solder paste printing help eliminate non-wet Cu pillar defect rates and improve yield over conventional flux printing. Heraeus solder paste (AP series T7) makes use of ultra-fine spherical shape of solder powder to create strong metal coalesce for bonding during reflow process of Cu pillars mounting to substrates. For example, the smallest passive component in use today is 008004 and Cu pillar diameter of 70um, which has a stencil opening of 125μm and 70μm respectively. Further reduction in Cu pillar flip-chip diameter of 55μm will require further reduction in stencil opening to 55μm, thus testing the limits of current type 7 pastes. Current solder pastes (AP series T7) can meet the consistency of printability when the stencil opening is 70μm or more. With smaller stencil opening, down to 55μm, the printing performance is less than desired. In this paper we describe the stencil printing application on the enhanced version of type 7 paste with a reinvented flux. The application tests were carried out using 55μm stencil opening. This paper will report the results of this application test.
超细SAC305焊料具有良好的连接强度、热机械疲劳性能和抗蠕变性能等优点,被广泛应用于先进封装中作为无铅互连焊料。由于模板印刷具有使用经济、易于过程控制、使用灵活以及快速和广泛的过程窗口等优点,因此它仍然是系统级封装(SiP)组装的首选技术。SiP涉及不同组件、铜柱倒装芯片和芯片在一个封装中的高级集成,以在一个系统中实现多种功能。为了适应不断增长的对减小占地面积的需求,该技术需要不断发明一系列直径为55μm的铜柱和更小的组件。许多移动通信SiP在单个封装中包含6个或更多的倒装芯片。传统的倒装芯片附件使用助焊剂和铜柱焊锡帽来形成焊点,因为在70μm以下的精细几何形状上印刷锡膏具有挑战性。锡膏印刷的其他好处有助于消除非湿铜柱缺陷率,提高产量优于传统的助焊剂印刷。贺利氏焊锡膏(AP系列T7)利用超细的球形焊锡粉,在铜柱安装到基板的回流过程中产生牢固的金属凝聚。例如,目前使用的最小的无源元件是008004,铜柱直径为70um,其模板开口分别为125μm和70μm。铜柱倒装芯片直径若进一步减小到55μm,则需要将模板开口进一步减小到55μm,从而测试当前7型浆料的极限。目前的焊膏(AP T7系列)在开口为70μm及以上时,可满足印刷一致性。由于模板开口较小,低至55μm,因此打印性能不如预期。本文介绍了采用改进型助焊剂的7型浆料增强版的模板印刷应用。应用试验采用55μm的模板开口进行。本文将报告该应用测试的结果。
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引用次数: 1
Prevention of thinned wafer deformation during thermocompression bonding and multi-die stacking supported by temporary bonding materials 防止薄晶片在热压键合和临时键合材料支撑下的多模堆积过程中的变形
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000060
Alice Guerrero, P. Bex, A. Jones, A. Southard, Daojie Dong, A. Phommahaxay, E. Beyne
Process flows for memory stacking or other heterogeneous integration schemes benefit from die bonding on a thinned silicon wafer 100 μm or less. In scenarios where a thinned device wafer contains features such as microbumps or Cu pillars, a carrier and temporary bonding material (TBM) facilitate the support of the fragile landing wafer during thermocompression bonding (TCB). The landing wafer in this case is vulnerable to deformations including loss of die planarity, Si bulging, Si or low k dielectric cracking, and damage to the underlying device wafer topography. In this paper, a dual layer system for temporary bonding is presented that maintains the integrity of a thinned device wafer during and after TCB. This is achieved with TBM materials which do not reflow at typical TCB conditions. The approach is to simulate TCB conditions which demonstrate the performance between different underlying TBM materials. A method which tracks the bond head z-axis over time during a TCB cycle is described which in turn yields information on the degree of temporary substrate deformation due to TCB force and temperature. The experiments include a worst-case scenario of multiple TCB cycles in the same position to mimic multi-die stacking. Finally, the impact of process conditions on Cu pillars with solder caps embedded in a thinned wafer bond line will be discussed.
存储器堆叠或其他异构集成方案的工艺流程受益于在100 μm或更薄的硅晶圆上的芯片键合。在薄型器件晶片包含微凸起或铜柱等特征的情况下,载体和临时键合材料(TBM)有助于在热压键合(TCB)过程中支撑脆弱的着陆晶片。在这种情况下,着陆晶圆容易变形,包括模具平面度损失,Si胀形,Si或低k介电开裂,以及对底层器件晶圆形貌的破坏。本文提出了一种用于临时键合的双层系统,可以在TCB期间和之后保持薄化器件晶圆的完整性。这是通过在典型TCB条件下不回流的TBM材料实现的。该方法是模拟TCB条件,以证明不同下垫TBM材料之间的性能。描述了一种在TCB循环期间随时间跟踪键头z轴的方法,该方法反过来产生关于由于TCB力和温度引起的衬底临时变形程度的信息。实验包括多个TCB循环在同一位置的最坏情况,以模拟多模堆叠。最后,讨论了工艺条件对薄晶圆键合线内嵌焊帽铜柱的影响。
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引用次数: 1
Distribution of Coated Metal Layer on Free Air Ball (FAB) Surface 自由空气球(FAB)表面金属涂层的分布
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000328
S. Murali, L. Wan, Dhayalan Mariyappan, Lim Yee Weon Evonne, Kang Sungsig SS
Developments in bonding wire focus on coated silver wire for stacked devices in memory sectors revealing near equivalent performances to 4N Au wire. In addition to stacked device applications, the wire is also examined for other conventional applications. The innovative wire exhibits excellent performance on biased Highly Accelerated Stress Test (bHAST) passing 192h and 504h at 130°C, 85%RH for +3.3V and +20V, respectively. Thus, the wire satisfied one of the important criteria required to pass automotive reliability test (2X stress test, AEC Q100 Rev-H, with limited test samples). The test is conducted using 0.8mil coated silver wire and molded with green epoxy molding compound. Another benefit of the wire is stitch bond bondability with high MTBA of greater than 2h.
键合线的发展主要集中在用于存储领域堆叠器件的涂覆银线上,其性能接近4N金线。除了堆叠设备应用外,还对其他传统应用进行了检查。在+3.3V和+20V条件下,在130°C, 85%RH条件下,该创新导线在偏置高加速应力测试(bast)中表现出优异的性能,分别通过了192h和504h。因此,该电线满足了通过汽车可靠性测试(2X应力测试,AEC Q100 Rev-H,测试样品有限)所需的重要标准之一。试验采用0.8mil包覆银丝,绿色环氧树脂模塑料成型。该钢丝的另一个优点是具有较高的MTBA,大于2h的缝合粘合性。
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引用次数: 0
Ultrasonic Wire Bond Outlier Classification 超声线键异常值分类
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000256
H. Seppänen, Siang Tat Chua, Joel Elizondo Martinez, Pedro Villa
K&S developed and tested the Advanced Process Diagnostics (APD) algorithm to classify bonding outliers in ultrasonic wire bond production. APD is a software feature, part of Kulicke & Soffa wedge bonders to measure and analyze process signals and detect and classify bond outliers. APD helps bonder operators, production supervisors and process engineers to detect process deviations and fix the underlying root causes. APD measures bond signals, such as deformation, ultrasonic current and ultrasonic frequency. Bonds are automatically divided into subgroups based on bond order and process parameters and the signals within a subgroup are then normalized. For outlier classification, the features are extracted from the normalized signals and combined into failure class values. The failure classes, such as contamination, misaligned wire and unstable substrate, are calculated independently. Within the APD feature, a user can define limits for the failure class values and define bonder actions based on the severity of the detected outlier. We measured the detection rates for large wire Al bond failure classes and demonstrate how APD calculates failure class values from the signals. Additionally, we show how new signal features and failure classes can be defined to detect production specific or rare failure classes. Finally, we present outlier classification performance metrics against large production data sets.
K&S开发并测试了先进的过程诊断(APD)算法,用于对超声波线键合生产中的异常值进行分类。APD是Kulicke & Soffa楔形粘结机的一个软件功能,用于测量和分析过程信号,检测和分类粘结异常值。APD帮助粘合剂操作员、生产主管和工艺工程师检测工艺偏差并解决潜在的根本原因。APD测量键合信号,如变形、超声电流和超声频率。根据键的顺序和过程参数自动将键划分为子组,然后将子组内的信号规范化。对于异常点分类,从归一化信号中提取特征并组合成故障类别值。故障类别,如污染、导线错位和衬底不稳定,是独立计算的。在APD功能中,用户可以定义故障类别值的限制,并根据检测到的异常值的严重程度定义绑定操作。我们测量了大型铝键合故障类别的检测率,并演示了APD如何从信号中计算故障类别值。此外,我们还展示了如何定义新的信号特征和故障类别来检测生产特定的或罕见的故障类别。最后,我们提出了针对大型生产数据集的异常值分类性能指标。
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引用次数: 1
The Pivotal Role of Uniformity of Electrolytic Deposition Processes to Improve the Reliability of Advanced Packaging 电解沉积工艺均匀性对提高先进封装可靠性的关键作用
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000142
Ralf Schmidt, Jens Palm, J. Knaup
Heterogeneous integration is considered as the key technology to create large, complex System in Package (SiP) assemblies of separately manufactured, smaller components. Proper control of the uniformity of each process step constitutes one of the main challenges during integration of the different components into a higher-level assembly. In this context, processes that create thick layers by electrochemical deposition are especially susceptible to variations across the substrate. Such processes include copper pillar and bump as well as tin-silver applications. Insufficient coplanarity of electrolytic copper would result in significant reliability issues or evolution of stress in the package. Upcoming hybrid bump designs with features of different dimensions pose additional challenges to the electrolytic copper and tin-silver processes. Purposeful adjustment of differences between the heights of pillars of different diameters may be required after the copper process step in order to obtain the best uniformity for the complete stack with tin-silver on top. In addition to coplanarity, the electrolytic process should allow modification shape of the individual pillar or bump. In this context, a versatile copper electrodeposition process will be discussed that allows adjustment to a broad variety of uniformity parameters and combinations thereof. In combination with suitable tin-silver deposition processes, this process is expected to significantly improve the reliability of copper pillars and bumps for advanced packaging applications.
异构集成被认为是创建大型、复杂的系统封装(SiP)组件的关键技术,这些组件是由单独制造的较小的组件组成的。在将不同组件集成到更高级别的装配中,对每个工艺步骤的均匀性的适当控制构成了主要挑战之一。在这种情况下,通过电化学沉积产生厚层的工艺特别容易受到衬底变化的影响。这些工艺包括铜柱和凸块以及锡银应用。电解铜的共面性不足将导致严重的可靠性问题或封装中应力的演变。即将到来的具有不同尺寸特征的混合凸点设计对电解铜和锡银工艺提出了额外的挑战。在铜工艺步骤后,可能需要有目的地调整不同直径柱的高度差异,以获得顶部有锡银的整个堆的最佳均匀性。除了共面性外,电解过程还应允许修改单个支柱或凸起的形状。在这种情况下,将讨论一种通用的铜电沉积工艺,该工艺允许调整各种均匀性参数及其组合。结合合适的锡银沉积工艺,该工艺有望显著提高铜柱和凸点的可靠性,用于先进的封装应用。
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引用次数: 0
Impact of Bonding Sequence on Contact Resistance in Hybrid Bonding of Via-middle TSV Wafer 通过-中间TSV晶圆杂化键合中键合顺序对接触电阻的影响
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000244
N. Watanabe, Hiroshi Yamamoto, Takahiko Mitsui, E. Yamamoto
This study examines the impact of the bonding sequence on the contact resistance in the hybrid bonding of a via-middle Cu though-silicon via (TSV) wafer. Hybrid bonding was performed at room temperature via a surface-activated bonding method using an ultrathin Si film. Comparative study of various bonding sequences revealed that the (a) cleaning of the target Si, via-middle TSV, and Cu electrode wafers with an Ar fast atom beam (FAB), (b) transferring of the Cu electrode wafer into another chamber during cleaning of the via-middle TSV wafer, and (c) transferring of the via-middle TSV wafer to another chamber while cleaning the Cu electrode wafer were all effective in decreasing the oxygen atoms in the bonding interface (amorphous Si layer) and reducing the contact resistances between the TSVs and Cu electrodes.
本研究考察了通孔-中孔铜通孔-硅通孔(TSV)晶圆杂化键合过程中键合顺序对接触电阻的影响。利用超薄硅薄膜,在室温下通过表面活化键合方法进行杂化键合。不同键合顺序的对比研究表明:(a)用Ar快原子束(FAB)清洗靶Si、过中TSV和Cu电极晶片,(b)在清洗过中TSV晶片过程中将Cu电极晶片转移到另一个腔室中。(c)通过中间TSV晶片转移到另一个腔室,同时清洗Cu电极晶片,都有效地减少了键合界面(非晶Si层)中的氧原子,降低了TSV与Cu电极之间的接触电阻。
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引用次数: 0
Novel lithography technology for enhancing resolution limit at advanced packaging manufacturing 新型光刻技术提高先进包装制造的分辨率极限
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000045
H. Matsui
New lithography method will be proposed in the paper to enhance resolution limit by half of current one while keeping depth of focus at the same value. The method is based on lithography and copper plating process in order to be applicable to advanced packaging manufacturing.
本文将提出一种新的光刻方法,在保持焦深不变的情况下,将分辨率限制提高到现有方法的一半。该方法是基于光刻和镀铜工艺,以适用于先进的包装制造。
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引用次数: 0
Throughput and Material Utilization by Glass Wafer Laser Dicing 玻璃晶圆激光切割的产量和材料利用率
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000011
A. Gaab, Christian J. Wagner, Priyanka Khera
Laser-based dicing of glass wafers for up to 300 mm diameter provides a high quality as well as a high throughput solution for dicing of glass-based products. This technology can be applied to glass wafers for Microfluidic, ME(O)MS and other semiconductor applications as for sensor cover glasses. Based on a die per wafer calculation and nominal processing speeds for laser and breaking technologies, a wafer per hour performance for small dies can be calculated. e.g. for a 3 mm square die design on a 300 mm diameter wafers, a dicing takt of ~10 wafers per hours can be expected. Exemplary investigations of a Corning® HPFS® Fused Silica (HPFS) glass wafer demonstrate the exceptional performance for chipping and edge quality and provide a quality, where the chipping performance is better than 50 μm with very precise edges and die corners.
激光切割直径达300毫米的玻璃晶圆,为玻璃基产品的切割提供了高质量和高吞吐量的解决方案。该技术可应用于微流体,ME(O)MS和其他半导体应用的玻璃晶圆,如传感器覆盖玻璃。基于每晶圆片的芯片计算和激光和破碎技术的标称加工速度,可以计算出小型芯片每小时的晶圆性能。例如,在直径为300毫米的晶圆上设计一个3毫米见方的模具,预计每小时可切割约10片晶圆。对康宁®HPFS®熔融石英(HPFS)玻璃晶圆片的示例性研究表明,其在切屑和边缘质量方面具有卓越的性能,并提供了一个质量,其中切屑性能优于50 μm,具有非常精确的边缘和模角。
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引用次数: 1
High Frequency, Low Loss, Additively Manufactured Hermetic Package 高频,低损耗,增材制造的密封封装
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000154
T. Smith, Bill Rhyne, Rob Reid, Christopher Hatfield
This paper presents the development of a new type of hermetic cavity package for mmWave RF MMICs. The package features an all copper additively manufactured construction for optimal thermal performance as well as low loss air coax RF signal routing with a critical ceramic feedthrough to isolate the internals of the package from the external environment. With a simulated thermal resistance of 1 C/W, from die backside to package lid, and RF insertion loss of less than 0.5dB from 0–80Ghz, this package can support high power as well as high frequency MMICS. With no polymers in the construction of the package true hermetic performance is expected, making this package a high reliability option as well. For this paper two die were selected for demo packages. These die do not have surface mountable packages offered on the market. The die selected are the CMD247 30–40GHz Low Phase Noise Amplifier from Qorvo and the CHA2080-98F 71–86GHz Low Noise Amplifier from United Monolithic Semiconductors. RF insertion loss as well as environmental reliability will be demonstrated with these devices. The additive manufacturing process used is the proprietary PolyStrata® process developed by Nuvotronics. With the development of 14” panel substrate manufacturing line utilizing a mask-less process, fabrication process can support both high-volume, and high-customization without incurring prohibitive tooling costs.
本文介绍了一种新型毫米波射频微处理器的密封腔封装。该封装采用全铜增材制造结构,具有最佳的热性能,以及低损耗的空气同轴射频信号路由,具有关键的陶瓷馈通,可将封装内部与外部环境隔离开来。从芯片背面到封装盖的模拟热阻为1 C/W,在0-80Ghz范围内射频插入损耗小于0.5dB,该封装可以支持高功率和高频mmic。由于在封装的结构中没有聚合物,真正的密封性能是预期的,这使得该封装也是一个高可靠性的选择。本文选择两个模具作为演示封装。这些模具没有在市场上提供的表面安装包。选用的芯片是Qorvo公司的CMD247 30-40GHz低相位噪声放大器和United Monolithic Semiconductors公司的CHA2080-98F 71-86GHz低噪声放大器。这些器件将演示射频插入损耗以及环境可靠性。所使用的增材制造工艺是由Nuvotronics开发的专有PolyStrata®工艺。随着采用无掩膜工艺的14英寸面板基板生产线的发展,制造工艺可以支持大批量和高定制,而不会产生高昂的模具成本。
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引用次数: 0
Advanced Protected Fan-In WLCSP 高级保护风扇入式WLCSP
Pub Date : 2021-10-01 DOI: 10.4071/1085-8024-2021.1.000089
D. Hackler, E. Prack
With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.
随着凸模的出现,新的IC封装不断发展:用于低IO WLCSP(晶圆级芯片规模封装),用于高IO FC(倒装芯片)CBGA(陶瓷球网格阵列)和PBGA(塑料球网格阵列)。对于低IO,受保护CSP是一个新兴和快速增长的市场。到2020年,市场规模将超过20亿美元,预计到2025年将达到25亿美元。1最初,WLCSP,也称为FI(扇入),封装建立在晶圆上,没有主动侧保护,从建立在晶圆上的封装演变为单侧保护,过渡到再分配PSB(钝化应力缓冲)3,PSB用于FC晶圆上的高IO BGA封装。这些过程最初提供了可接受的性能,但是随着设备变得更加复杂和可靠性要求的增加,这些过程不再提供所需的可靠性。为了获得更高的IO能力和更好的可靠性性能,发展到CSP4(非wl),它允许更大的凹凸分布区域和对其余暴露的模具表面的额外保护。完全保护的模具CSP(没有基板或引线框架)最初是通过使用FO(扇出)工艺的m系列等工艺实现的为了获得m系列工艺提供的更高可靠性的六面模具保护,需要模具重构、昂贵的胶带、成型和其他通常在FO工艺中需要的操作,而这些操作在WLCSP保护的FI工艺中是可以消除的。美国半导体公司的半导体聚合物™(SoP™)300mm FleX-TM WLCSP是一种先进的封装工艺,针对受保护的风扇插入进行了优化。FleX-TM生产当今业界最薄,成本最低的保护FI。受保护的FI工艺创新可以提高功率器件,RF开关,芯片堆叠和薄板应用的性能。本文介绍了CSP发展的背景,以及包括FleX-TM在内的SOTA(最先进的)FI流程的比较。
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引用次数: 0
期刊
International Symposium on Microelectronics
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