Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126402
P. Xu, Xinnan Lin
In this paper, a new PNPN tunnel field-effect transistor with L-shaped gate (LG-PNPN TFET) is proposed and investigated by numerical device simulator bringing significant on-state current enhancement. Higher drive current is achieved at VDD = 1.0V than traditional PNPN TFET because of both the line and point tunneling between the source and N+ pocket. Key parameters like the pocket width and doping concentration are further studied for device performance optimization.
{"title":"Current enhanced PNPN tunnel field-effect transistor with L-shaped gate","authors":"P. Xu, Xinnan Lin","doi":"10.1109/EDSSC.2017.8126402","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126402","url":null,"abstract":"In this paper, a new PNPN tunnel field-effect transistor with L-shaped gate (LG-PNPN TFET) is proposed and investigated by numerical device simulator bringing significant on-state current enhancement. Higher drive current is achieved at VDD = 1.0V than traditional PNPN TFET because of both the line and point tunneling between the source and N+ pocket. Key parameters like the pocket width and doping concentration are further studied for device performance optimization.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126570
Guang Zhu, Duona Luo, John Zhuang, C. Zhi, C. Yue
This work presents a self-adaptation algorithm to automatically adjust the peaking settings of a continuous-time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital settings. By performing the peak detection at the output of the equalization summer, the effect of digital equalization is inherently accounted for by the proposed algorithm. To demonstrate the effectiveness of the proposed algorithm, a PAM4 receiver employing two stages of CTLE and 1-tap feed forward equalizer (FFE) is designed to compensate up to 11.8-dB channel loss for a data rate of 56 Gb/s.
{"title":"A fully adaptive continuous-time linear equalizer for PAM4 signaling based on a statistical algorithm (Invited paper)","authors":"Guang Zhu, Duona Luo, John Zhuang, C. Zhi, C. Yue","doi":"10.1109/EDSSC.2017.8126570","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126570","url":null,"abstract":"This work presents a self-adaptation algorithm to automatically adjust the peaking settings of a continuous-time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital settings. By performing the peak detection at the output of the equalization summer, the effect of digital equalization is inherently accounted for by the proposed algorithm. To demonstrate the effectiveness of the proposed algorithm, a PAM4 receiver employing two stages of CTLE and 1-tap feed forward equalizer (FFE) is designed to compensate up to 11.8-dB channel loss for a data rate of 56 Gb/s.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122918770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126548
J. Yan, S. Gogineni, J. Nunn
Airborne ultrawideband radars operating at VHF/UHF frequencies can be used to sound and image polar ice sheets with fine-resolution. The sensitivity of the radar depends upon the power-aperture product. High peak power coupled with a large aperture is required to sound more than 4-km thick ice. In this paper, we present the design of a 400-W power amplifier for operation over the frequency range of 150–550 MHz. The amplifier uses gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) manufactured by Cree. The primary design goals are to maximize the output power and gain while minimizing the harmonic levels. To achieve these, a push-pull configuration with quadrature combining is implemented.
{"title":"Ultrawideband power amplifier for radar sounding and imaging of ice sheets","authors":"J. Yan, S. Gogineni, J. Nunn","doi":"10.1109/EDSSC.2017.8126548","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126548","url":null,"abstract":"Airborne ultrawideband radars operating at VHF/UHF frequencies can be used to sound and image polar ice sheets with fine-resolution. The sensitivity of the radar depends upon the power-aperture product. High peak power coupled with a large aperture is required to sound more than 4-km thick ice. In this paper, we present the design of a 400-W power amplifier for operation over the frequency range of 150–550 MHz. The amplifier uses gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) manufactured by Cree. The primary design goals are to maximize the output power and gain while minimizing the harmonic levels. To achieve these, a push-pull configuration with quadrature combining is implemented.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114366157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126426
Bo Zhou, Qipeng Wang, Pu Ge, Q. Ma, Yue Lu, Chonghu Cheng
A compact narrow-band low temperature co-fired ceramic (LTCC) filter with a fractional bandwidth of 3% is proposed. The proposed filter consists of five cascaded half-wavelength resonators vertically arrayed on each LTCC layer. End-coupling between adjacent resonators is precisely controlled by rectangle-shaped slot on intermediate ground layer. The overall size of the filter is only 8 × 6 × 0.89 mm and a size reduction of 80% is achieved compared with a planar one. Measured S11 and S21 are better than −14 and −2.5 dB in the passband, respectively.
{"title":"Compact LTCC filter with end-coupled resonators","authors":"Bo Zhou, Qipeng Wang, Pu Ge, Q. Ma, Yue Lu, Chonghu Cheng","doi":"10.1109/EDSSC.2017.8126426","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126426","url":null,"abstract":"A compact narrow-band low temperature co-fired ceramic (LTCC) filter with a fractional bandwidth of 3% is proposed. The proposed filter consists of five cascaded half-wavelength resonators vertically arrayed on each LTCC layer. End-coupling between adjacent resonators is precisely controlled by rectangle-shaped slot on intermediate ground layer. The overall size of the filter is only 8 × 6 × 0.89 mm and a size reduction of 80% is achieved compared with a planar one. Measured S11 and S21 are better than −14 and −2.5 dB in the passband, respectively.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8355993
Wenhuan Luan, Ziqiang Wang, S. Yuan, Chun Zhang, Zhihua Wang
This paper presents an eye-opening monitor (EOM) architecture used in the high-speed wireline communication system. Compared with the conventional 2-D EOM, the proposed rectangular 2-D EOM provides variable asymmetric sizes of masks. Single-quadrant phase interpolators (PIs) and independent digital-to-analog converters (DACs) controlled by the external signals generate asymmetric masks. Different masks with the same bit error rate (BER) are overlapped to emerge non-rectangular eye diagram shape. The proposed 2-D EOM is designed in 40 nm CMOS process and operates up to 5 Gb/s data rate at 1.1V power supply. Each PI has 90° variable range with 6° phase step. Meanwhile, each 6 bit DAC generates asymmetric reference voltages compared with the common voltage. So this design provides 1080 different masks to not only improve the accuracy of eye diagram but also detect the offset of data. The total power consumption of the proposed EOM is 13.3mW.
{"title":"A 13.3W 5-Gb/s two-dimensional eye-opening monitor in 40nm CMOS technology","authors":"Wenhuan Luan, Ziqiang Wang, S. Yuan, Chun Zhang, Zhihua Wang","doi":"10.1109/EDSSC.2017.8355993","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8355993","url":null,"abstract":"This paper presents an eye-opening monitor (EOM) architecture used in the high-speed wireline communication system. Compared with the conventional 2-D EOM, the proposed rectangular 2-D EOM provides variable asymmetric sizes of masks. Single-quadrant phase interpolators (PIs) and independent digital-to-analog converters (DACs) controlled by the external signals generate asymmetric masks. Different masks with the same bit error rate (BER) are overlapped to emerge non-rectangular eye diagram shape. The proposed 2-D EOM is designed in 40 nm CMOS process and operates up to 5 Gb/s data rate at 1.1V power supply. Each PI has 90° variable range with 6° phase step. Meanwhile, each 6 bit DAC generates asymmetric reference voltages compared with the common voltage. So this design provides 1080 different masks to not only improve the accuracy of eye diagram but also detect the offset of data. The total power consumption of the proposed EOM is 13.3mW.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126510
Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, S. Yuan, Chun Zhang, Xiang Xie, Hanjun Jiang
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with extra cross-coupled inverter to bring hyterisis delay for oscilating is adopted in the ring PLL. The active area occupied by the proposed LC PLL and ring PLL fabricated in SMIC 40nm CMOS technology is 0.1755mm2 and 0.049mm2. The free running VCO's phase noise at 1MHz for the LC VCO and ring VCO is −105.7dBc/Hz and −72.6dBc/Hz. The power consumption for the LC PLL and the ring PLL are 19.52mW and 16.9mW under 1.1V supply.
{"title":"An 8.5–12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes","authors":"Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, S. Yuan, Chun Zhang, Xiang Xie, Hanjun Jiang","doi":"10.1109/EDSSC.2017.8126510","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126510","url":null,"abstract":"This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with extra cross-coupled inverter to bring hyterisis delay for oscilating is adopted in the ring PLL. The active area occupied by the proposed LC PLL and ring PLL fabricated in SMIC 40nm CMOS technology is 0.1755mm2 and 0.049mm2. The free running VCO's phase noise at 1MHz for the LC VCO and ring VCO is −105.7dBc/Hz and −72.6dBc/Hz. The power consumption for the LC PLL and the ring PLL are 19.52mW and 16.9mW under 1.1V supply.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116246305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126567
Ramendra Singh, P. Kushwaha, Sudip Ghosh, B. Parvais, Y. Chauhan, A. Dixit
RF CMOS technology provides a platform for the production of analog, digital and RF circuits on a single chip for futuristic high-level integration. This facilitates the need for a robust compact model for RF FinFETs to study the circuits in a precise and convenient way. In this paper, we have characterized 14-nm N-channel bulk FinFETs by performing two-port S-parameter measurements. Further, BSIM-CMG model for common multiple gate devices is used to accurately capture the RF behavior of the device.
{"title":"Characterization and modeling of N-channel bulk FinFETs from DC to high frequency","authors":"Ramendra Singh, P. Kushwaha, Sudip Ghosh, B. Parvais, Y. Chauhan, A. Dixit","doi":"10.1109/EDSSC.2017.8126567","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126567","url":null,"abstract":"RF CMOS technology provides a platform for the production of analog, digital and RF circuits on a single chip for futuristic high-level integration. This facilitates the need for a robust compact model for RF FinFETs to study the circuits in a precise and convenient way. In this paper, we have characterized 14-nm N-channel bulk FinFETs by performing two-port S-parameter measurements. Further, BSIM-CMG model for common multiple gate devices is used to accurately capture the RF behavior of the device.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114703477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126449
S. Varma, B. Bhuvan
A low-power high feedback factor common mode feedback technique using subthreshold MOSFETs is presented in this paper. The proposed approach is an improved version of the conventional resistive degeneration of current mirrors. The proposed technique is implemented in preamplifier which is designed in UMC 180 nm technology with 1.8V power supply and 225nA bias current. The SPICE simulations show that the proposed method achieves 1.9 times increase in the differential mode bandwidth besides 2.5 times increase in the common mode feedback factor compared to the conventional approach for the same power consumption.
{"title":"Low-power high-bandwidth preamplifier with improved common mode feedback stability","authors":"S. Varma, B. Bhuvan","doi":"10.1109/EDSSC.2017.8126449","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126449","url":null,"abstract":"A low-power high feedback factor common mode feedback technique using subthreshold MOSFETs is presented in this paper. The proposed approach is an improved version of the conventional resistive degeneration of current mirrors. The proposed technique is implemented in preamplifier which is designed in UMC 180 nm technology with 1.8V power supply and 225nA bias current. The SPICE simulations show that the proposed method achieves 1.9 times increase in the differential mode bandwidth besides 2.5 times increase in the common mode feedback factor compared to the conventional approach for the same power consumption.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127927711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126480
Jia Liu, Fule Li, Weitao Li, Hanjun Jiang, Zhihua Wang
This paper presents a Flash ADC with low offset dynamic comparators using an offset cancellation technique. By dynamically storing the comparator offset on the input capacitors, the offset is suppressed mostly. Two 5-bit 160MS/s Flash ADCs (Flash-A using the proposed offset cancellation technique and Flash-B without cancellation) are fabricated in 65nm CMOS for comparison. The measure results show that, the DNL is reduced from 1.32LSB to 0.62LSB and the INL is reduced from 1.20LSB to 0.55LSB. The SNDR improves from 26.25dB to 29.63dB and the SFDR improves from 35.02dB to 43.61dB. And the power increases from 3.44 mW to 3.79 mW.
{"title":"A flash ADC with low offset dynamic comparators","authors":"Jia Liu, Fule Li, Weitao Li, Hanjun Jiang, Zhihua Wang","doi":"10.1109/EDSSC.2017.8126480","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126480","url":null,"abstract":"This paper presents a Flash ADC with low offset dynamic comparators using an offset cancellation technique. By dynamically storing the comparator offset on the input capacitors, the offset is suppressed mostly. Two 5-bit 160MS/s Flash ADCs (Flash-A using the proposed offset cancellation technique and Flash-B without cancellation) are fabricated in 65nm CMOS for comparison. The measure results show that, the DNL is reduced from 1.32LSB to 0.62LSB and the INL is reduced from 1.20LSB to 0.55LSB. The SNDR improves from 26.25dB to 29.63dB and the SFDR improves from 35.02dB to 43.61dB. And the power increases from 3.44 mW to 3.79 mW.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131252405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126470
Z. Fan, Taotao Guan, Leijian Cheng, Fang Yang, Dacheng Zhang
This paper presents a in situ on-chip micro tensile fracture strength tester, which is based on a thermal actuated test platform. In this test platform, tensile fracture strength could be extracted and process could be evaluated, there are two samples with same layout but fabricated under different process conditions were evaluated through this test platform and the results showed that this test platform has an outstanding ability to evaluate the tensile fracture strength and thus monitor the process quality.
{"title":"A thermal actuated test platform for in situ evaluating the tensile fracture strength of micro-structures","authors":"Z. Fan, Taotao Guan, Leijian Cheng, Fang Yang, Dacheng Zhang","doi":"10.1109/EDSSC.2017.8126470","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126470","url":null,"abstract":"This paper presents a in situ on-chip micro tensile fracture strength tester, which is based on a thermal actuated test platform. In this test platform, tensile fracture strength could be extracted and process could be evaluated, there are two samples with same layout but fabricated under different process conditions were evaluated through this test platform and the results showed that this test platform has an outstanding ability to evaluate the tensile fracture strength and thus monitor the process quality.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131253087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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