A description is given of an expert system that helps diagnose failures on VLSI memories. The expert system is intended to be used in the fields of quality assurance and failure analysis. After a discussion of the problem and the definition of the project, the different databases used and the architecture of the expert system are described. Then, the strategy of the system, which depends on the kind of failure diagnosed after a first-level analysis, is explained. Current developments are discussed that are intended to improve the capability of the expert system and depth of diagnosis
{"title":"An expert system to assist in diagnosis of failures on VLSI memories","authors":"T. Viacroze, M. Lequeux","doi":"10.1109/CICC.1989.56838","DOIUrl":"https://doi.org/10.1109/CICC.1989.56838","url":null,"abstract":"A description is given of an expert system that helps diagnose failures on VLSI memories. The expert system is intended to be used in the fields of quality assurance and failure analysis. After a discussion of the problem and the definition of the project, the different databases used and the architecture of the expert system are described. Then, the strategy of the system, which depends on the kind of failure diagnosed after a first-level analysis, is explained. Current developments are discussed that are intended to improve the capability of the expert system and depth of diagnosis","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124007648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A decimator IC has been developed for use with noise-shaping front-end coders to implement a very-high-resolution A/D (analog-to-digital) converter intended primarily for professional audio applications. The IC contains a multirate filter structure to obtain a decimation ratio of 128:1 with 80 dB of stopband rejection. An input wordlength of 6 bits and an output wordlength of 20 bits allow signal-to-noise ratios in excess of 110 dB to be obtained with the appropriate front-end coder
{"title":"A 20-bit decimator IC for high-resolution audio A/D conversion","authors":"R. Adams, G. Frenkil, D. Gottfried, Paul Pinelle","doi":"10.1109/CICC.1989.56795","DOIUrl":"https://doi.org/10.1109/CICC.1989.56795","url":null,"abstract":"A decimator IC has been developed for use with noise-shaping front-end coders to implement a very-high-resolution A/D (analog-to-digital) converter intended primarily for professional audio applications. The IC contains a multirate filter structure to obtain a decimation ratio of 128:1 with 80 dB of stopband rejection. An input wordlength of 6 bits and an output wordlength of 20 bits allow signal-to-noise ratios in excess of 110 dB to be obtained with the appropriate front-end coder","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129748986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of ±2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of ±0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit
{"title":"An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique","authors":"Jenn-Gang Chern, A. Abidi","doi":"10.1109/CICC.1989.56698","DOIUrl":"https://doi.org/10.1109/CICC.1989.56698","url":null,"abstract":"An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of ±2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of ±0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Sugawa, T. Ikarashi, K. Kuwana, T. Kawakami, A. Kimitsuka, T. Iida
A CMOS low distortion sample and hold circuit with total harmonic distortion of 0.01% for audio D/A (digital-to-analog) convertor has been developed, using a novel circuit architecture and high-speed operational amplifier. As an application of this technology to the audio field, an audio signal delay processing LSI with high-resolution A/D and D/A converters has been realized. The LSI has been fabricated using a 1.5-μm CMOS process and a die size of 18.5 mm2
{"title":"CMOS low distortion sample and hold circuit for audio D/A converter","authors":"N. Sugawa, T. Ikarashi, K. Kuwana, T. Kawakami, A. Kimitsuka, T. Iida","doi":"10.1109/CICC.1989.56701","DOIUrl":"https://doi.org/10.1109/CICC.1989.56701","url":null,"abstract":"A CMOS low distortion sample and hold circuit with total harmonic distortion of 0.01% for audio D/A (digital-to-analog) convertor has been developed, using a novel circuit architecture and high-speed operational amplifier. As an application of this technology to the audio field, an audio signal delay processing LSI with high-resolution A/D and D/A converters has been realized. The LSI has been fabricated using a 1.5-μm CMOS process and a die size of 18.5 mm2","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120914051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Smith, C. Anagnostopoulos, C. Portmann, R. Rao, P. Valdenaire, H. Ching
Efforts to improve the tools and techniques for designing an analog cell library for analog/digital VLSI design are described. The techniques presented allow an analog IC designer to construct a library for cell-based design, as opposed to direct compilation of a full-custom analog/digital IC. Using this approach, the problem of automation is made more tractable, and the result is a more robust, but still flexible, system for mixed analog/digital ASIC (application-specific integrated circuit) design. By combining a study of device scaling issues, careful choice of layout topologies, together with modular construction of cells using lambda based rules, it is possible to extend the lifetime of an analog cell library. Cells have been constructed for both 2- and 1.5-μm down-gate-width technologies with the ability to scale down to a 1-μm process
{"title":"Construction of analog library cells for analog/digital ASICs using novel design and modular assembly techniques","authors":"M. Smith, C. Anagnostopoulos, C. Portmann, R. Rao, P. Valdenaire, H. Ching","doi":"10.1109/CICC.1989.56833","DOIUrl":"https://doi.org/10.1109/CICC.1989.56833","url":null,"abstract":"Efforts to improve the tools and techniques for designing an analog cell library for analog/digital VLSI design are described. The techniques presented allow an analog IC designer to construct a library for cell-based design, as opposed to direct compilation of a full-custom analog/digital IC. Using this approach, the problem of automation is made more tractable, and the result is a more robust, but still flexible, system for mixed analog/digital ASIC (application-specific integrated circuit) design. By combining a study of device scaling issues, careful choice of layout topologies, together with modular construction of cells using lambda based rules, it is possible to extend the lifetime of an analog cell library. Cells have been constructed for both 2- and 1.5-μm down-gate-width technologies with the ability to scale down to a 1-μm process","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single-chip two-channel, 8-bit, analog input/output port with versatile input and output signal conditioning features has been produced. The part is primarily designed for applications in head-positioning servos in Winchester disk drive systems, where the ever-increasing requirement for increased performance and lower production costs has fueled the need for greater system integration
{"title":"Design of an analog 8-bit two-channel I/O ASIC for disk drive control applications","authors":"P. Quinlan","doi":"10.1109/CICC.1989.56732","DOIUrl":"https://doi.org/10.1109/CICC.1989.56732","url":null,"abstract":"A single-chip two-channel, 8-bit, analog input/output port with versatile input and output signal conditioning features has been produced. The part is primarily designed for applications in head-positioning servos in Winchester disk drive systems, where the ever-increasing requirement for increased performance and lower production costs has fueled the need for greater system integration","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124424440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Delaney, C. Chou, L. Larson, J. Jensen, D. Deakin, A. Brown, W. Hooper, M. Thompson, L. McCray, S. Rosenbaum
High-performance digital integrated circuits have been fabricated with low-temperature buffer GaAs MESFET technology. The materials structure eliminates side-gating and light sensitivity, and improves FET performance. Individual transistors with a 0.2-μm gate length have a transconductance gm of 600 mS/mm and an extrapolated cutoff frequency fT of 80 GHz. Static SCFL frequency dividers fabricated in this technology exhibit a maximum clock rate of 22 GHz
{"title":"GaAs MESFET digital integrated circuits fabricated with low temperature buffer technology","authors":"M. Delaney, C. Chou, L. Larson, J. Jensen, D. Deakin, A. Brown, W. Hooper, M. Thompson, L. McCray, S. Rosenbaum","doi":"10.1109/CICC.1989.56782","DOIUrl":"https://doi.org/10.1109/CICC.1989.56782","url":null,"abstract":"High-performance digital integrated circuits have been fabricated with low-temperature buffer GaAs MESFET technology. The materials structure eliminates side-gating and light sensitivity, and improves FET performance. Individual transistors with a 0.2-μm gate length have a transconductance gm of 600 mS/mm and an extrapolated cutoff frequency fT of 80 GHz. Static SCFL frequency dividers fabricated in this technology exhibit a maximum clock rate of 22 GHz","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127925437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Komatsu, K. Watanabe, E. Minamimura, Y. Kowase, S. Ueda, N. Horie, S. Asai, T. Matsuura
A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm 2 chip size and consumes 100 mW
{"title":"CMOS high speed digital datastrobe processor","authors":"T. Komatsu, K. Watanabe, E. Minamimura, Y. Kowase, S. Ueda, N. Horie, S. Asai, T. Matsuura","doi":"10.1109/CICC.1989.56731","DOIUrl":"https://doi.org/10.1109/CICC.1989.56731","url":null,"abstract":"A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm 2 chip size and consumes 100 mW","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A geometric approach for building-block layout compaction is presented. With a systematic method of automatic jog insertion, the authors have proved that the proposed algorithm achieves the lower bound of one-dimensional compaction with jog insertion. The approach presented is extremely powerful and provides a very efficient way to compact very complicated VLSI systems. When the input chip is given in symbolic form, the algorithm can be used to space the chip only if the chip can be expanded at every scan line. In this case, the maximum moves of some objects will be negative; the objects are actually moved up in the y -direction compaction to expand the space
{"title":"Geometric compaction of building-block layout","authors":"X. Xiong, E. Kuh","doi":"10.1109/CICC.1989.56778","DOIUrl":"https://doi.org/10.1109/CICC.1989.56778","url":null,"abstract":"A geometric approach for building-block layout compaction is presented. With a systematic method of automatic jog insertion, the authors have proved that the proposed algorithm achieves the lower bound of one-dimensional compaction with jog insertion. The approach presented is extremely powerful and provides a very efficient way to compact very complicated VLSI systems. When the input chip is given in symbolic form, the algorithm can be used to space the chip only if the chip can be expanded at every scan line. In this case, the maximum moves of some objects will be negative; the objects are actually moved up in the y -direction compaction to expand the space","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129065672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method is presented for the analysis of lossy interconnections terminated with nonlinear loads. The crux of the method is a piecewise decomposition technique that decomposes the nonlinear network into linear and nonlinear subnetworks. The linear subnetworks contain the distributed models for the interconnections. The terminals of the subnetworks are excited by piecewise linear sources. The linear subnetworks are solved in the frequency domain and the nonlinear subnetworks are solved in the time domain. Newton's iterations are used to adjust the parameters of the piecewise linear sources so that the topological and constitutive relations of each subnetwork, as well as the topological equations resulting from the interconnection of the subnetworks, are satisfied
{"title":"Analysis of pulse propagation on high-speed VLSI chips","authors":"M. Nakhla","doi":"10.1109/CICC.1989.56749","DOIUrl":"https://doi.org/10.1109/CICC.1989.56749","url":null,"abstract":"A method is presented for the analysis of lossy interconnections terminated with nonlinear loads. The crux of the method is a piecewise decomposition technique that decomposes the nonlinear network into linear and nonlinear subnetworks. The linear subnetworks contain the distributed models for the interconnections. The terminals of the subnetworks are excited by piecewise linear sources. The linear subnetworks are solved in the frequency domain and the nonlinear subnetworks are solved in the time domain. Newton's iterations are used to adjust the parameters of the piecewise linear sources so that the topological and constitutive relations of each subnetwork, as well as the topological equations resulting from the interconnection of the subnetworks, are satisfied","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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