A decimator IC has been developed for use with noise-shaping front-end coders to implement a very-high-resolution A/D (analog-to-digital) converter intended primarily for professional audio applications. The IC contains a multirate filter structure to obtain a decimation ratio of 128:1 with 80 dB of stopband rejection. An input wordlength of 6 bits and an output wordlength of 20 bits allow signal-to-noise ratios in excess of 110 dB to be obtained with the appropriate front-end coder
{"title":"A 20-bit decimator IC for high-resolution audio A/D conversion","authors":"R. Adams, G. Frenkil, D. Gottfried, Paul Pinelle","doi":"10.1109/CICC.1989.56795","DOIUrl":"https://doi.org/10.1109/CICC.1989.56795","url":null,"abstract":"A decimator IC has been developed for use with noise-shaping front-end coders to implement a very-high-resolution A/D (analog-to-digital) converter intended primarily for professional audio applications. The IC contains a multirate filter structure to obtain a decimation ratio of 128:1 with 80 dB of stopband rejection. An input wordlength of 6 bits and an output wordlength of 20 bits allow signal-to-noise ratios in excess of 110 dB to be obtained with the appropriate front-end coder","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129748986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method is presented for the analysis of lossy interconnections terminated with nonlinear loads. The crux of the method is a piecewise decomposition technique that decomposes the nonlinear network into linear and nonlinear subnetworks. The linear subnetworks contain the distributed models for the interconnections. The terminals of the subnetworks are excited by piecewise linear sources. The linear subnetworks are solved in the frequency domain and the nonlinear subnetworks are solved in the time domain. Newton's iterations are used to adjust the parameters of the piecewise linear sources so that the topological and constitutive relations of each subnetwork, as well as the topological equations resulting from the interconnection of the subnetworks, are satisfied
{"title":"Analysis of pulse propagation on high-speed VLSI chips","authors":"M. Nakhla","doi":"10.1109/CICC.1989.56749","DOIUrl":"https://doi.org/10.1109/CICC.1989.56749","url":null,"abstract":"A method is presented for the analysis of lossy interconnections terminated with nonlinear loads. The crux of the method is a piecewise decomposition technique that decomposes the nonlinear network into linear and nonlinear subnetworks. The linear subnetworks contain the distributed models for the interconnections. The terminals of the subnetworks are excited by piecewise linear sources. The linear subnetworks are solved in the frequency domain and the nonlinear subnetworks are solved in the time domain. Newton's iterations are used to adjust the parameters of the piecewise linear sources so that the topological and constitutive relations of each subnetwork, as well as the topological equations resulting from the interconnection of the subnetworks, are satisfied","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of ±2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of ±0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit
{"title":"An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique","authors":"Jenn-Gang Chern, A. Abidi","doi":"10.1109/CICC.1989.56698","DOIUrl":"https://doi.org/10.1109/CICC.1989.56698","url":null,"abstract":"An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of ±2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of ±0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Murayama, Y. Matsuda, K. Yoshida, H. Ooka, T. Otani, S. Toyoda, F. Tsubokura, A. Aso
A CMOS SOG (sea-of-gates) that contains 177 K raw gates, corresponding to 1.4 M transistors and having a delay time of as fast as 150 ps, has been developed in a 0.8-μm CMOS technology. The SOG can accommodate a RAM of either a high-density type with 64 K bits maximum, a high-speed type with 6-ns access time, or a mixture of both. The SOG contains 1856 I/O buffers in the peripheral area of the die, providing high flexibility for interfacing circuits to the SOG
{"title":"A 177 K gate 150 PS CMOS SOG with 1856 I/O buffers","authors":"M. Murayama, Y. Matsuda, K. Yoshida, H. Ooka, T. Otani, S. Toyoda, F. Tsubokura, A. Aso","doi":"10.1109/CICC.1989.56715","DOIUrl":"https://doi.org/10.1109/CICC.1989.56715","url":null,"abstract":"A CMOS SOG (sea-of-gates) that contains 177 K raw gates, corresponding to 1.4 M transistors and having a delay time of as fast as 150 ps, has been developed in a 0.8-μm CMOS technology. The SOG can accommodate a RAM of either a high-density type with 64 K bits maximum, a high-speed type with 6-ns access time, or a mixture of both. The SOG contains 1856 I/O buffers in the peripheral area of the die, providing high flexibility for interfacing circuits to the SOG","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Fisher, Kuo-Tung Chang, F. Pintchovski, J. Klein, K. Fu, S. Lai, R. Dillard
A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps have been measured on a development 16 K-gate array with 0.8-μm gate lengths
{"title":"A submicron CMOS triple level metal technology for ASIC applications","authors":"D. Fisher, Kuo-Tung Chang, F. Pintchovski, J. Klein, K. Fu, S. Lai, R. Dillard","doi":"10.1109/CICC.1989.56781","DOIUrl":"https://doi.org/10.1109/CICC.1989.56781","url":null,"abstract":"A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps have been measured on a development 16 K-gate array with 0.8-μm gate lengths","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114028345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VLSI design methodologies with fewer abstraction levels than usual are discussed. It is felt that such methods are easier to use and to automatize, while still providing efficient chips. RISC (reduced-instruction-set computer) and CISC (complex-instruction-set computer) methodologies as well as a floorplan-oriented methodology are discussed
{"title":"Design methodologies and CAD tools [VLSI]","authors":"C. Piguet","doi":"10.1109/CICC.1989.56845","DOIUrl":"https://doi.org/10.1109/CICC.1989.56845","url":null,"abstract":"VLSI design methodologies with fewer abstraction levels than usual are discussed. It is felt that such methods are easier to use and to automatize, while still providing efficient chips. RISC (reduced-instruction-set computer) and CISC (complex-instruction-set computer) methodologies as well as a floorplan-oriented methodology are discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114439563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Komatsu, K. Watanabe, E. Minamimura, Y. Kowase, S. Ueda, N. Horie, S. Asai, T. Matsuura
A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm 2 chip size and consumes 100 mW
{"title":"CMOS high speed digital datastrobe processor","authors":"T. Komatsu, K. Watanabe, E. Minamimura, Y. Kowase, S. Ueda, N. Horie, S. Asai, T. Matsuura","doi":"10.1109/CICC.1989.56731","DOIUrl":"https://doi.org/10.1109/CICC.1989.56731","url":null,"abstract":"A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm 2 chip size and consumes 100 mW","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A geometric approach for building-block layout compaction is presented. With a systematic method of automatic jog insertion, the authors have proved that the proposed algorithm achieves the lower bound of one-dimensional compaction with jog insertion. The approach presented is extremely powerful and provides a very efficient way to compact very complicated VLSI systems. When the input chip is given in symbolic form, the algorithm can be used to space the chip only if the chip can be expanded at every scan line. In this case, the maximum moves of some objects will be negative; the objects are actually moved up in the y -direction compaction to expand the space
{"title":"Geometric compaction of building-block layout","authors":"X. Xiong, E. Kuh","doi":"10.1109/CICC.1989.56778","DOIUrl":"https://doi.org/10.1109/CICC.1989.56778","url":null,"abstract":"A geometric approach for building-block layout compaction is presented. With a systematic method of automatic jog insertion, the authors have proved that the proposed algorithm achieves the lower bound of one-dimensional compaction with jog insertion. The approach presented is extremely powerful and provides a very efficient way to compact very complicated VLSI systems. When the input chip is given in symbolic form, the algorithm can be used to space the chip only if the chip can be expanded at every scan line. In this case, the maximum moves of some objects will be negative; the objects are actually moved up in the y -direction compaction to expand the space","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129065672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Haas, K. Au, L. Martin, T. Portlock, T. Sakurai
The authors describe a high-voltage layout usable for output drivers in a standard 5-V CMOS process. These outputs are useful for applications such as vacuum fluorescent displays, motor drivers, automotive equipment. There is no modification of the manufacturing process or additional masking layers needed. An application of this technique to a mux liquid-crystal-display (LCD) driver is also described
{"title":"High voltage CMOS LCD driver using low voltage CMOS process","authors":"J. Haas, K. Au, L. Martin, T. Portlock, T. Sakurai","doi":"10.1109/CICC.1989.56755","DOIUrl":"https://doi.org/10.1109/CICC.1989.56755","url":null,"abstract":"The authors describe a high-voltage layout usable for output drivers in a standard 5-V CMOS process. These outputs are useful for applications such as vacuum fluorescent displays, motor drivers, automotive equipment. There is no modification of the manufacturing process or additional masking layers needed. An application of this technique to a mux liquid-crystal-display (LCD) driver is also described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132976512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, A. Scherf
An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed
{"title":"High performance clock distribution for CMOS ASICs","authors":"S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, A. Scherf","doi":"10.1109/CICC.1989.56761","DOIUrl":"https://doi.org/10.1109/CICC.1989.56761","url":null,"abstract":"An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131278036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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