M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka
A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation
{"title":"A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure","authors":"M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka","doi":"10.1109/CICC.1989.56842","DOIUrl":"https://doi.org/10.1109/CICC.1989.56842","url":null,"abstract":"A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Data stored as magnetic flux reversals on a hard disk are read by an inductive head in close proximity to the disk, across which voltage signals of 0.1-1 mV are induced by the flux. These analog signals must be amplified before they are converted to logic levels by a decision circuit. A read-head preamplifier specially designed to be driven by an inductive source is used for this purpose. In a modern disk-drive subsystem, this amplifier must be wideband (>30 MHz), have a voltage gain of at least 100, and have low input noise (<2 nV/√Hz). The authors report on the first such amplifier fabricated in a 3-μm CMOS process. Some of the unique advantages offered by a CMOS design are highlighted, and its performance in a disk subsystem is compared with that of the industry standard bipolar preamplifier
{"title":"A 30 MHz low-noise CMOS preamplifier for disk drive heads","authors":"T. Pan, A. Abidi","doi":"10.1109/CICC.1989.56704","DOIUrl":"https://doi.org/10.1109/CICC.1989.56704","url":null,"abstract":"Data stored as magnetic flux reversals on a hard disk are read by an inductive head in close proximity to the disk, across which voltage signals of 0.1-1 mV are induced by the flux. These analog signals must be amplified before they are converted to logic levels by a decision circuit. A read-head preamplifier specially designed to be driven by an inductive source is used for this purpose. In a modern disk-drive subsystem, this amplifier must be wideband (>30 MHz), have a voltage gain of at least 100, and have low input noise (<2 nV/√Hz). The authors report on the first such amplifier fabricated in a 3-μm CMOS process. Some of the unique advantages offered by a CMOS design are highlighted, and its performance in a disk subsystem is compared with that of the industry standard bipolar preamplifier","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116841562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, A. Scherf
An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed
{"title":"High performance clock distribution for CMOS ASICs","authors":"S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, A. Scherf","doi":"10.1109/CICC.1989.56761","DOIUrl":"https://doi.org/10.1109/CICC.1989.56761","url":null,"abstract":"An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131278036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A device model is described for the simulation of the effects of single-event and radiation phenomena on the operation of GaAs MESFETs. The model can be utilized in a circuit simulator to evaluate integrated-circuit designs and aid in the provision of adequate upset margins for various operating environments. Additional subcircuit construction is unnecessary since the electrical responses to the different phenomena are intrinsic to the device template. Example simulations using SPICE3 are described
{"title":"Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits","authors":"P. George, P. Ko, C. Hu","doi":"10.1109/CICC.1989.56725","DOIUrl":"https://doi.org/10.1109/CICC.1989.56725","url":null,"abstract":"A device model is described for the simulation of the effects of single-event and radiation phenomena on the operation of GaAs MESFETs. The model can be utilized in a circuit simulator to evaluate integrated-circuit designs and aid in the provision of adequate upset margins for various operating environments. Additional subcircuit construction is unnecessary since the electrical responses to the different phenomena are intrinsic to the device template. Example simulations using SPICE3 are described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131540736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. P. Gowni, P. Platt, A. Hawkins, W. Hiltpold, S. Douglass
A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance
{"title":"A 12 ns, CMOS programmable logic device for combinatorial applications","authors":"S. P. Gowni, P. Platt, A. Hawkins, W. Hiltpold, S. Douglass","doi":"10.1109/CICC.1989.56694","DOIUrl":"https://doi.org/10.1109/CICC.1989.56694","url":null,"abstract":"A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132451244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar
A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces
{"title":"ACACIA: the CMU analog design system","authors":"L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar","doi":"10.1109/CICC.1989.56685","DOIUrl":"https://doi.org/10.1109/CICC.1989.56685","url":null,"abstract":"A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132505328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Murayama, Y. Matsuda, K. Yoshida, H. Ooka, T. Otani, S. Toyoda, F. Tsubokura, A. Aso
A CMOS SOG (sea-of-gates) that contains 177 K raw gates, corresponding to 1.4 M transistors and having a delay time of as fast as 150 ps, has been developed in a 0.8-μm CMOS technology. The SOG can accommodate a RAM of either a high-density type with 64 K bits maximum, a high-speed type with 6-ns access time, or a mixture of both. The SOG contains 1856 I/O buffers in the peripheral area of the die, providing high flexibility for interfacing circuits to the SOG
{"title":"A 177 K gate 150 PS CMOS SOG with 1856 I/O buffers","authors":"M. Murayama, Y. Matsuda, K. Yoshida, H. Ooka, T. Otani, S. Toyoda, F. Tsubokura, A. Aso","doi":"10.1109/CICC.1989.56715","DOIUrl":"https://doi.org/10.1109/CICC.1989.56715","url":null,"abstract":"A CMOS SOG (sea-of-gates) that contains 177 K raw gates, corresponding to 1.4 M transistors and having a delay time of as fast as 150 ps, has been developed in a 0.8-μm CMOS technology. The SOG can accommodate a RAM of either a high-density type with 64 K bits maximum, a high-speed type with 6-ns access time, or a mixture of both. The SOG contains 1856 I/O buffers in the peripheral area of the die, providing high flexibility for interfacing circuits to the SOG","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A prototype frequency-domain simulator that models the nth-order circuit by a lower order q-model has been developed. It combines results equivalent to hand analysis with variable order numerical pole-zero approximation. The dominant poles and zeros, including those that are complex or repeated, are found efficiently on recursive DC analysis of the circuit. In addition, the effect of the variation of element values on the pole locations can be obtained at an incremental cost in CPU time
{"title":"Dominant pole(s)/zero(s) analysis for analog circuit design","authors":"L. Pillage, C. Wolff, R. Rohrer","doi":"10.1109/CICC.1989.56802","DOIUrl":"https://doi.org/10.1109/CICC.1989.56802","url":null,"abstract":"A prototype frequency-domain simulator that models the nth-order circuit by a lower order q-model has been developed. It combines results equivalent to hand analysis with variable order numerical pole-zero approximation. The dominant poles and zeros, including those that are complex or repeated, are found efficiently on recursive DC analysis of the circuit. In addition, the effect of the variation of element values on the pole locations can be obtained at an incremental cost in CPU time","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
BILOW, a steady-state one-dimensional bipolar transistor simulator for the 77 K-300 K temperature range, is presented. Examples of internal device characteristics for a medium-voltage n-p-n silicon bipolar transistor demonstrate the capability of the simulation. Calculated current gain and unity gain frequency versus current density for temperatures down to liquid nitrogen temperature (77 K) are presented and discussed. It is concluded that the simulator is a very useful tool for investigating different design approaches and the influence of process design on the temperature dependence of bipolar transistor parameters
{"title":"Steady-state bipolar transistor simulator for the 77 K-300 K temperature range","authors":"M. Chrzanowska-Jeske, R. Jaeger","doi":"10.1109/CICC.1989.56720","DOIUrl":"https://doi.org/10.1109/CICC.1989.56720","url":null,"abstract":"BILOW, a steady-state one-dimensional bipolar transistor simulator for the 77 K-300 K temperature range, is presented. Examples of internal device characteristics for a medium-voltage n-p-n silicon bipolar transistor demonstrate the capability of the simulation. Calculated current gain and unity gain frequency versus current density for temperatures down to liquid nitrogen temperature (77 K) are presented and discussed. It is concluded that the simulator is a very useful tool for investigating different design approaches and the influence of process design on the temperature dependence of bipolar transistor parameters","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Haas, K. Au, L. Martin, T. Portlock, T. Sakurai
The authors describe a high-voltage layout usable for output drivers in a standard 5-V CMOS process. These outputs are useful for applications such as vacuum fluorescent displays, motor drivers, automotive equipment. There is no modification of the manufacturing process or additional masking layers needed. An application of this technique to a mux liquid-crystal-display (LCD) driver is also described
{"title":"High voltage CMOS LCD driver using low voltage CMOS process","authors":"J. Haas, K. Au, L. Martin, T. Portlock, T. Sakurai","doi":"10.1109/CICC.1989.56755","DOIUrl":"https://doi.org/10.1109/CICC.1989.56755","url":null,"abstract":"The authors describe a high-voltage layout usable for output drivers in a standard 5-V CMOS process. These outputs are useful for applications such as vacuum fluorescent displays, motor drivers, automotive equipment. There is no modification of the manufacturing process or additional masking layers needed. An application of this technique to a mux liquid-crystal-display (LCD) driver is also described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132976512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：