The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-μm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation
介绍了一种通用模糊逻辑推理引擎的单片机实现。功能包括动态可重构和可级联架构，TTL(晶体管-晶体管逻辑)兼容的主机接口，激光编程冗余，可测试性的特殊模式，RAM规则存储，以及片上模糊化和去模糊化。采用1 μm、3.3 v DLM CMOS技术，可在实时控制应用中处理多达102条并行规则。580 KFLIPS(每秒模糊逻辑推理)使用688 K晶体管和36 mhz操作
{"title":"A VLSI fuzzy logic inference engine for real-time process control","authors":"W. Dettloff, K. E. Yount","doi":"10.1109/CICC.1989.56741","DOIUrl":"https://doi.org/10.1109/CICC.1989.56741","url":null,"abstract":"The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-μm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"63 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122471570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Gallia, A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore, C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Rine, Ashwin H. Shah
A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan
{"title":"A 100 K gate sub-micron BiCMOS gate array","authors":"J. Gallia, A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore, C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Rine, Ashwin H. Shah","doi":"10.1109/CICC.1989.56717","DOIUrl":"https://doi.org/10.1109/CICC.1989.56717","url":null,"abstract":"A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"23 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126844905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A BiNMOS test chip has been designed and fabricated in 0.8-μm BiCMOS technology. The test chip consists of a 4×22 array of BiNMOS cells. The test structures include a ring oscillator, a 4-bit SRAM (static random-access memory) core, five types of buffers, a MUX, and a shift register. Ring oscillator measurements indicate a basic BiNMOS inverter delay of 240 ps (FO=1), a result that agrees well with simulation
{"title":"BiNMOS: a basic cell for BiCMOS sea-of-gates","authors":"A. El Gamal, J. Kouloheris, D. How, M. Morf","doi":"10.1109/CICC.1989.56710","DOIUrl":"https://doi.org/10.1109/CICC.1989.56710","url":null,"abstract":"A BiNMOS test chip has been designed and fabricated in 0.8-μm BiCMOS technology. The test chip consists of a 4×22 array of BiNMOS cells. The test structures include a ring oscillator, a 4-bit SRAM (static random-access memory) core, five types of buffers, a MUX, and a shift register. Ring oscillator measurements indicate a basic BiNMOS inverter delay of 240 ps (FO=1), a result that agrees well with simulation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126653228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A built-in test system that is capable of parallel testing all combinational and sequential arrays on a CMOS chip is presented. The system is based on a recently introduced tristate multiplexing design for programmable and register logic arrays and requires minimal on-chip test storage and silicon area overhead. The test procedure is tailored to the detection of real mask defects in the layout of the array. The system also uses simple and economical data compaction circuit that provides a good fault coverage while not precluding the use of more sophisticated data compactors
{"title":"Built-in test of CMOS state machines with realistic faults: a system perspective","authors":"M. Katoozi, M. Soma","doi":"10.1109/CICC.1989.56811","DOIUrl":"https://doi.org/10.1109/CICC.1989.56811","url":null,"abstract":"A built-in test system that is capable of parallel testing all combinational and sequential arrays on a CMOS chip is presented. The system is based on a recently introduced tristate multiplexing design for programmable and register logic arrays and requires minimal on-chip test storage and silicon area overhead. The test procedure is tailored to the detection of real mask defects in the layout of the array. The system also uses simple and economical data compaction circuit that provides a good fault coverage while not precluding the use of more sophisticated data compactors","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An ECL (emitter-coupled logic)-structured array containing 1520 logic cells, 2560 bits of RAM, and a customizable analog section is described. The special needs of high performance VLSI testers was the driving force behind its organization and architecture. The chip is fabricated with a trench isolation bipolar process with 1-μm features, double layers of polysilicon, and triple layers of metallization
{"title":"Q20D080 analog RAM logic array","authors":"C. Blake, M. Hollabaugh","doi":"10.1109/CICC.1989.56762","DOIUrl":"https://doi.org/10.1109/CICC.1989.56762","url":null,"abstract":"An ECL (emitter-coupled logic)-structured array containing 1520 logic cells, 2560 bits of RAM, and a customizable analog section is described. The special needs of high performance VLSI testers was the driving force behind its organization and architecture. The chip is fabricated with a trench isolation bipolar process with 1-μm features, double layers of polysilicon, and triple layers of metallization","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121618952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An effective design method for VLSI-based microprocessors is proposed. The chip is divided into three components, namely control logic, data paths, and macrocells, at a very early stage. The control logic is automatically designed by logic synthesis and automatic placement and routing. For the data paths and the macrocells, logic and layout are designed manually. By combining the design method with so-called design-pipelining, a 32-bit microprocessor with 460 K transistors was designed in a year without sacrificing the chip size and performance. The method's impact on design effort is also discussed
{"title":"Optimized design method for full-custom microprocessors","authors":"K. Usami, J. Iwamura","doi":"10.1109/CICC.1989.56790","DOIUrl":"https://doi.org/10.1109/CICC.1989.56790","url":null,"abstract":"An effective design method for VLSI-based microprocessors is proposed. The chip is divided into three components, namely control logic, data paths, and macrocells, at a very early stage. The control logic is automatically designed by logic synthesis and automatic placement and routing. For the data paths and the macrocells, logic and layout are designed manually. By combining the design method with so-called design-pipelining, a 32-bit microprocessor with 460 K transistors was designed in a year without sacrificing the chip size and performance. The method's impact on design effort is also discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115308485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Integrated circuits are approaching biological complexity in device count. Biological systems are fault tolerant, adaptive, and trainable, and the possibility exists for similar characteristics in ICs. The authors report a limited-interconnect, highly layered synthetic neural network that implements these ideals. These networks are specifically designed to scale to tens of thousands of processing elements on current production size dies. A compact analog cell, a training algorithm, and a limited-interconnect architecture which has demonstrated neuromorphic behavior are described
{"title":"A synthetic neural integrated circuit","authors":"L. Akers, M. Walker, R. Grondin, D. Ferry","doi":"10.1109/CICC.1989.56743","DOIUrl":"https://doi.org/10.1109/CICC.1989.56743","url":null,"abstract":"Integrated circuits are approaching biological complexity in device count. Biological systems are fault tolerant, adaptive, and trainable, and the possibility exists for similar characteristics in ICs. The authors report a limited-interconnect, highly layered synthetic neural network that implements these ideals. These networks are specifically designed to scale to tens of thousands of processing elements on current production size dies. A compact analog cell, a training algorithm, and a limited-interconnect architecture which has demonstrated neuromorphic behavior are described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122630581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A digital bit-serial VLSI chip for accumulating neural activations of a population of neurons that form a linear receptive field is discussed. This type of VLSI circuit is complementary to the best-match classifiers described in the literature. The circuit is called a brute force detector (BFD). The authors have designed and fabricated a prototype BFD neuron cascade through MOSIS in a 3-μm p-well CMOS process (M83M run). The results indicate that a wafer-scale, restructurable version of a detector could be constructed that could implement on the order of 105 receptive fields. A receiver using a cascade of such wafers would be of great practical value for radar and sonar applications as well as useful for the search for extraterrestrial intelligence (SETI)
讨论了一种数字位串行VLSI芯片，用于积累形成线性感受野的神经元群的神经激活。这种类型的VLSI电路是对文献中描述的最佳匹配分类器的补充。这种电路称为BFD (brute force detector)。作者在3 μm孔CMOS工艺(M83M运行)中通过MOSIS设计并制作了BFD神经元级联原型。结果表明，晶圆级、可重构版本的探测器可以构建，可以实现105个接收野的顺序。使用这种晶圆级联的接收器在雷达和声纳应用中具有很大的实用价值，对寻找地外智慧生物(SETI)也很有用。
{"title":"A bit-serial VLSI receptive field accumulator","authors":"K. Strohbehn, A. Andreou","doi":"10.1109/CICC.1989.56742","DOIUrl":"https://doi.org/10.1109/CICC.1989.56742","url":null,"abstract":"A digital bit-serial VLSI chip for accumulating neural activations of a population of neurons that form a linear receptive field is discussed. This type of VLSI circuit is complementary to the best-match classifiers described in the literature. The circuit is called a brute force detector (BFD). The authors have designed and fabricated a prototype BFD neuron cascade through MOSIS in a 3-μm p-well CMOS process (M83M run). The results indicate that a wafer-scale, restructurable version of a detector could be constructed that could implement on the order of 105 receptive fields. A receiver using a cascade of such wafers would be of great practical value for radar and sonar applications as well as useful for the search for extraterrestrial intelligence (SETI)","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125030789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A set of design tools that creates the framework for a loading-edge full-custom design methodology has been developed. The tools provide the design flexibility and accuracy needed to achieve maximum performance in a quality design. Complex chips with clock rates from 90 MHz to 250 MHz have been economically built using the three latest generations of CMOS processing technologies, sized at 1.75 μm, 1.25 μm, and 0.9 μm
{"title":"Computer aids for high performance CMOS custom design","authors":"T. C. Poon, Y. Oh, W. Oswald, P. Magarshack","doi":"10.1109/CICC.1989.56792","DOIUrl":"https://doi.org/10.1109/CICC.1989.56792","url":null,"abstract":"A set of design tools that creates the framework for a loading-edge full-custom design methodology has been developed. The tools provide the design flexibility and accuracy needed to achieve maximum performance in a quality design. Complex chips with clock rates from 90 MHz to 250 MHz have been economically built using the three latest generations of CMOS processing technologies, sized at 1.75 μm, 1.25 μm, and 0.9 μm","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127829016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Trontelj, L. Trontelj, T. Slivnik, T. Pletersek, G. Shenton
The basis for the automation of mixed analog/digital ASIC (application-specific integrated circuit) design is a method previously proposed by the authors. The essence of the method is the introduction of so-called personalized cells, which are optimized to fit the specific needs of the current design. A deterministic method for operational amplifier and layout compilation is presented. In addition, a method is introduced to describe the critical layout parameters in a schematic capture program
{"title":"Automatic circuit and layout design for mixed analog/digital ASICs","authors":"J. Trontelj, L. Trontelj, T. Slivnik, T. Pletersek, G. Shenton","doi":"10.1109/CICC.1989.56773","DOIUrl":"https://doi.org/10.1109/CICC.1989.56773","url":null,"abstract":"The basis for the automation of mixed analog/digital ASIC (application-specific integrated circuit) design is a method previously proposed by the authors. The essence of the method is the introduction of so-called personalized cells, which are optimized to fit the specific needs of the current design. A deterministic method for operational amplifier and layout compilation is presented. In addition, a method is introduced to describe the critical layout parameters in a schematic capture program","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120983549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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