An efficient implementation of a Hopfield-type fully connected neural-network architecture is presented that is based on a pulse-density modulation technique implemented by using fully digital structures. The synaptic weights are programmable, and thus the area of one synapse and the entire network depends on the resolution of the weight. Advantages of the design are its modularity and expandability
{"title":"Fully digital neural network implementation based on pulse density modulation","authors":"J. Tomberg, T. Ritoniemi, K. Kaski, H. Tenhunen","doi":"10.1109/CICC.1989.56744","DOIUrl":"https://doi.org/10.1109/CICC.1989.56744","url":null,"abstract":"An efficient implementation of a Hopfield-type fully connected neural-network architecture is presented that is based on a pulse-density modulation technique implemented by using fully digital structures. The synaptic weights are programmable, and thus the area of one synapse and the entire network depends on the resolution of the weight. Advantages of the design are its modularity and expandability","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124799316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Kernhof, M. Schau, M. Beunder, W. Haas, B. Hoefflinger
Two CMOS semicustom gate forest chips with over 120K active transistors are presented: a digital filter circuit with a performance of 720 MOPS (million operations/s), and a 16-channel 70-Mb/s broadband switch unit. Static and domino cells, analog modules, and multiport RAMs are included. With 1600 transistors per mm2 the chips match the efficiency of 2-μm full-custom designs
{"title":"Mixed design approaches on the semicustom gate forest","authors":"J. Kernhof, M. Schau, M. Beunder, W. Haas, B. Hoefflinger","doi":"10.1109/CICC.1989.56760","DOIUrl":"https://doi.org/10.1109/CICC.1989.56760","url":null,"abstract":"Two CMOS semicustom gate forest chips with over 120K active transistors are presented: a digital filter circuit with a performance of 720 MOPS (million operations/s), and a 16-channel 70-Mb/s broadband switch unit. Static and domino cells, analog modules, and multiport RAMs are included. With 1600 transistors per mm2 the chips match the efficiency of 2-μm full-custom designs","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124833174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A combinatorial optimization algorithm called simulated annealing (SA) is applied to the modeling process of active devices. The objective is to obtain simplified yet accurate models by integrating both model minimization and parameter determination into one process. In this approach, two nested SA loops are used to determine the least-complicated model of a device that closely matches the measured characteristics. The outer loop reconfigures and simplifies a fully expanded, detailed equivalent-circuit mode, of which the parameters are optimized iteratively in the inner loop. This approach is technology-independent and versatile and can be applied to any device
{"title":"A technology-independent device modeling program using simulated annealing optimization","authors":"M. Vai, M.F.D. Ng","doi":"10.1109/CICC.1989.56722","DOIUrl":"https://doi.org/10.1109/CICC.1989.56722","url":null,"abstract":"A combinatorial optimization algorithm called simulated annealing (SA) is applied to the modeling process of active devices. The objective is to obtain simplified yet accurate models by integrating both model minimization and parameter determination into one process. In this approach, two nested SA loops are used to determine the least-complicated model of a device that closely matches the measured characteristics. The outer loop reconfigures and simplifies a fully expanded, detailed equivalent-circuit mode, of which the parameters are optimized iteratively in the inner loop. This approach is technology-independent and versatile and can be applied to any device","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128698471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A differential phase-locked-loop architecture that can be used in high-speed data recovery systems is described. The differential architecture has superior tracking performance in the presence of noise and thus superior bit-error-rate performance compared to the conventional single-ended realization. For operation at 10 Mb/s using a Manchester line code, the theoretical limit of ±25-ns jitter margin has been approached. The device, which is fabricated in a 1.25-μm digital CMOS process, includes zero-phase start circuitry for instant phase/frequency acquisition, a precision self-calibrated delay element, and a line receiver/driver for a complete line interface function
{"title":"A differential PLL architecture for high speed data recovery","authors":"R. Co, J. Liang, Kenneth W. Ouyang","doi":"10.1109/CICC.1989.56705","DOIUrl":"https://doi.org/10.1109/CICC.1989.56705","url":null,"abstract":"A differential phase-locked-loop architecture that can be used in high-speed data recovery systems is described. The differential architecture has superior tracking performance in the presence of noise and thus superior bit-error-rate performance compared to the conventional single-ended realization. For operation at 10 Mb/s using a Manchester line code, the theoretical limit of ±25-ns jitter margin has been approached. The device, which is fabricated in a 1.25-μm digital CMOS process, includes zero-phase start circuitry for instant phase/frequency acquisition, a precision self-calibrated delay element, and a line receiver/driver for a complete line interface function","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128910540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. W. Lang, C. Erdelyi, J. L. Lamphere, S. F. Oakland, J. D. Blair, A. Correale, H. C. Cranford, D. A. Dombrowski, C. R. Hoffman, Joseph Kinman Lee, J. M. Mullen, V. R. Norman
A 9.02-mm×9.02-mm chip built in 1-μm CMOS with two levels of metal and an addition mask level for fabricating capacitors is described. It contains both analog and digital circuits and has provisions for self-test. The functions include the transmitter, receiver, protocol handler, and microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. 24 K circuits of standard cell gates, 10 K circuits equivalent hand-honed custom microprocessor, and an analog macro form the physical design terrains. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s
{"title":"A 16 Mbps adapter chip for the IBM token-ring local area network","authors":"K. W. Lang, C. Erdelyi, J. L. Lamphere, S. F. Oakland, J. D. Blair, A. Correale, H. C. Cranford, D. A. Dombrowski, C. R. Hoffman, Joseph Kinman Lee, J. M. Mullen, V. R. Norman","doi":"10.1109/CICC.1989.56733","DOIUrl":"https://doi.org/10.1109/CICC.1989.56733","url":null,"abstract":"A 9.02-mm×9.02-mm chip built in 1-μm CMOS with two levels of metal and an addition mask level for fabricating capacitors is described. It contains both analog and digital circuits and has provisions for self-test. The functions include the transmitter, receiver, protocol handler, and microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. 24 K circuits of standard cell gates, 10 K circuits equivalent hand-honed custom microprocessor, and an analog macro form the physical design terrains. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126974400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is presented of a serial interfacing technique for embedded RAMs, which has been successfully applied to static single-port and dual-port memories in custom integrated circuits. A single bit of the input data path of a RAM (or a group of RAMs) is controlled by the built-in self-test (BIST) circuit, and a single bit of the output data path is observed during the execution of the algorithms. The other bits are controlled and observed indirectly through the serial data path. Automatically generated BIST circuits, which embed an algorithm suited for the application with the RAM, have been developed. The serial data path interface has also been used to provide external access to memories on cost sensitive chips which could not justify the full BIST overhead. This provides a simple external test access mode which uses a minimal number of pins yet exercises the memory at full speed
{"title":"A serial interfacing technique for built-in and external testing of embedded memories","authors":"B. Nadeau-Dostie, A. Silburt, V. Agarwal","doi":"10.1109/CICC.1989.56808","DOIUrl":"https://doi.org/10.1109/CICC.1989.56808","url":null,"abstract":"A description is presented of a serial interfacing technique for embedded RAMs, which has been successfully applied to static single-port and dual-port memories in custom integrated circuits. A single bit of the input data path of a RAM (or a group of RAMs) is controlled by the built-in self-test (BIST) circuit, and a single bit of the output data path is observed during the execution of the algorithms. The other bits are controlled and observed indirectly through the serial data path. Automatically generated BIST circuits, which embed an algorithm suited for the application with the RAM, have been developed. The serial data path interface has also been used to provide external access to memories on cost sensitive chips which could not justify the full BIST overhead. This provides a simple external test access mode which uses a minimal number of pins yet exercises the memory at full speed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130639186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An innovative technology that yields greater VLSI/VHSIC packaging densities and reliability while meeting military requirements including solderability and inspectability. The approach is called pinless grid array (PLGA) technology. Its reliability is examined, and its capability for increasing radiation hardness of electronic systems is briefly discussed
{"title":"Packaging structures utilizing new `pinless' grid array technologies and vacuum well processes to provide enhanced reliability and circuit densities","authors":"Patrick O. Nunally","doi":"10.1109/CICC.1989.56751","DOIUrl":"https://doi.org/10.1109/CICC.1989.56751","url":null,"abstract":"An innovative technology that yields greater VLSI/VHSIC packaging densities and reliability while meeting military requirements including solderability and inspectability. The approach is called pinless grid array (PLGA) technology. Its reliability is examined, and its capability for increasing radiation hardness of electronic systems is briefly discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126685504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2
{"title":"A 6 nsec CMOS EPLD with μW standby power","authors":"M. J. Allen","doi":"10.1109/CICC.1989.56689","DOIUrl":"https://doi.org/10.1109/CICC.1989.56689","url":null,"abstract":"A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126827757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit
{"title":"iSPLICE3: a new simulator for mixed analog/digital circuits","authors":"E. L. Acuna, J. Dervenis, A. J. Pagones, R. Saleh","doi":"10.1109/CICC.1989.56745","DOIUrl":"https://doi.org/10.1109/CICC.1989.56745","url":null,"abstract":"A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126218998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yiu-Fai Chan, C. Hung, C. Hsiao, P. Wong, N. Lee, C. McClintock
A description is given of VLSI devices that solve the complex interface problems between the Micro Channel Bus protocols of the IBM PS/2 system and add-on boards. One of the VLSI devices described makes use of programmability to allow system designers to customize their own interface through on-chip EPROM (erasable programmable read-only memory) bits. To make the task of interfacing to the Micro Channel straightforward for the system designer, accompanying software called McMap is provided. It is a table-driven program that will lead the system designer through the specifications. A custom version of his or her own interface can be specified through programming of the on-chip EPROM arrays. Adapter description files required by the PS/2 system are automatically generated for the user to install the board
{"title":"A function specific EPLD for the PS/2 Micro Channel Bus adapter","authors":"Yiu-Fai Chan, C. Hung, C. Hsiao, P. Wong, N. Lee, C. McClintock","doi":"10.1109/CICC.1989.56690","DOIUrl":"https://doi.org/10.1109/CICC.1989.56690","url":null,"abstract":"A description is given of VLSI devices that solve the complex interface problems between the Micro Channel Bus protocols of the IBM PS/2 system and add-on boards. One of the VLSI devices described makes use of programmability to allow system designers to customize their own interface through on-chip EPROM (erasable programmable read-only memory) bits. To make the task of interfacing to the Micro Channel straightforward for the system designer, accompanying software called McMap is provided. It is a table-driven program that will lead the system designer through the specifications. A custom version of his or her own interface can be specified through programming of the on-chip EPROM arrays. Adapter description files required by the PS/2 system are automatically generated for the user to install the board","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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