T. Nishimura, H. Satoh, M. Tatsuki, A. Ohba, S. Hine, K. Uga, Y. Kuramitsu
A 12 K-gate ECL (emitter-coupled logic) gate array with dedicated memory has been developed using 0.6-μm bipolar process technology. The memory is available for RAM or ROM storage. The gate array can also be used to implement a configurable RAM having internal cells
{"title":"0.6-μm 12 K-gate ECL gate array with RAM and ROM","authors":"T. Nishimura, H. Satoh, M. Tatsuki, A. Ohba, S. Hine, K. Uga, Y. Kuramitsu","doi":"10.1109/CICC.1989.56763","DOIUrl":"https://doi.org/10.1109/CICC.1989.56763","url":null,"abstract":"A 12 K-gate ECL (emitter-coupled logic) gate array with dedicated memory has been developed using 0.6-μm bipolar process technology. The memory is available for RAM or ROM storage. The gate array can also be used to implement a configurable RAM having internal cells","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116186939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design and construction of a complete high-speed modem front end on a single combined analog/digital application-specific integrated circuit are described. The chip is part of a highly integrated modem core created specifically for a family of V.32-based products. It incorporates all of the necessary analog/digital conversion, filtering, and gain control functions. Also included is an adaptive analog echo canceler designed to enhance system performance and reduce circuit complexity in other areas of the chip
{"title":"An analog front end chip for V.32 modems","authors":"J. Roesgen, G. Warren","doi":"10.1109/CICC.1989.56766","DOIUrl":"https://doi.org/10.1109/CICC.1989.56766","url":null,"abstract":"The design and construction of a complete high-speed modem front end on a single combined analog/digital application-specific integrated circuit are described. The chip is part of a highly integrated modem core created specifically for a family of V.32-based products. It incorporates all of the necessary analog/digital conversion, filtering, and gain control functions. Also included is an adaptive analog echo canceler designed to enhance system performance and reduce circuit complexity in other areas of the chip","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121654282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Okada, Y. Matsumoto, T. Matsuura, T. Shinmi, H. Nishijima, M. Masuda, S. Ueda
A special-purpose video signal processing (picture-in-picture processing) CMOS LSI with a 4-K gate digital section and on-chip video analog-to-digital and digital-to-analog converters has been realized. This mixed analog/digital system-on-chip VLSI (5.98 mm×6.86 mm) is designed using mixed-mode simulation and testing architecture and a noise suppression scheme, and is fabricated in a 2-μm CMOS process. The mixed analog/digital integration is a very attractive LSI feature for video system applications and satisfies future needs of system-on-chip VLSIs
{"title":"A mixed analog/digital video signal processing LSI with on-chip AD and DA converters","authors":"Y. Okada, Y. Matsumoto, T. Matsuura, T. Shinmi, H. Nishijima, M. Masuda, S. Ueda","doi":"10.1109/CICC.1989.56822","DOIUrl":"https://doi.org/10.1109/CICC.1989.56822","url":null,"abstract":"A special-purpose video signal processing (picture-in-picture processing) CMOS LSI with a 4-K gate digital section and on-chip video analog-to-digital and digital-to-analog converters has been realized. This mixed analog/digital system-on-chip VLSI (5.98 mm×6.86 mm) is designed using mixed-mode simulation and testing architecture and a noise suppression scheme, and is fabricated in a 2-μm CMOS process. The mixed analog/digital integration is a very attractive LSI feature for video system applications and satisfies future needs of system-on-chip VLSIs","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130711713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A coprocessor supporting a variety of placement and floorplanning algorithms is described. Without special hardware, the CPU time used by placement algorithms for net length computations can reach up to about 50% of the total run time. The proposed coprocessor architecture has special provisions for efficient net length computation which also allow concurrent execution with the main CPU. A prototype chip has been manufactured. The estimated speedup factor is about 40 for wire-length calculations. The chip can easily be integrated into current computer systems and usually requires only minimal changes to existing placement programs
{"title":"A special purpose coprocessor supporting cell placement and floorplanning algorithms","authors":"R. Kling, P. Banerjee","doi":"10.1109/CICC.1989.56678","DOIUrl":"https://doi.org/10.1109/CICC.1989.56678","url":null,"abstract":"A coprocessor supporting a variety of placement and floorplanning algorithms is described. Without special hardware, the CPU time used by placement algorithms for net length computations can reach up to about 50% of the total run time. The proposed coprocessor architecture has special provisions for efficient net length computation which also allow concurrent execution with the main CPU. A prototype chip has been manufactured. The estimated speedup factor is about 40 for wire-length calculations. The chip can easily be integrated into current computer systems and usually requires only minimal changes to existing placement programs","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132204156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The PIRAMID silicon compiler, which incorporates architecture synthesis, module generation, and floorplanning tools, is described. Design efficiency is evaluated by the design of an error corrector for a compact-disk digital audio system. A syndrome generator chip was found functionally correct and showed acceptable performance. The silicon compilation method has proved to be sufficiently mature to approach industrial constraints. Using a complete silicon compilation design system like PIRAMID, a system designer can iterate many different architecture solutions within a man-week. A flexible module library and gridless layout strategy give area efficient solutions
{"title":"The design of DSP components for the CD digital audio system using silicon compilation techniques","authors":"R. Woudsma, A. Delaruelle","doi":"10.1109/CICC.1989.56796","DOIUrl":"https://doi.org/10.1109/CICC.1989.56796","url":null,"abstract":"The PIRAMID silicon compiler, which incorporates architecture synthesis, module generation, and floorplanning tools, is described. Design efficiency is evaluated by the design of an error corrector for a compact-disk digital audio system. A syndrome generator chip was found functionally correct and showed acceptable performance. The silicon compilation method has proved to be sufficiently mature to approach industrial constraints. Using a complete silicon compilation design system like PIRAMID, a system designer can iterate many different architecture solutions within a man-week. A flexible module library and gridless layout strategy give area efficient solutions","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131291706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution
{"title":"A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture","authors":"K. Aono, M. Toyokura, T. Araki","doi":"10.1109/CICC.1989.56825","DOIUrl":"https://doi.org/10.1109/CICC.1989.56825","url":null,"abstract":"A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124114894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Okuno, M. Okabe, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, Y. Kuramitsu
Column macro-cell architecture has been verified to be advantageous for increasing silicon utilization in experimental circuit layouts. As an application, a 64-b multiplier with 32-kb RAM and 65-kb ROM using a 1.4-M transistor sea of gates (SOG) has been developed, using 0.8-μm two-layer-metal CMOS. Gate density of 1.5 kg/mm2 and bit densities of 1.9 kb/mm2 for RAM and 6.3/mm2 for ROM have been achieved
{"title":"0.8 μm 1.4 MTr. CMOS SOG based on column macro-cell","authors":"Y. Okuno, M. Okabe, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, Y. Kuramitsu","doi":"10.1109/CICC.1989.56716","DOIUrl":"https://doi.org/10.1109/CICC.1989.56716","url":null,"abstract":"Column macro-cell architecture has been verified to be advantageous for increasing silicon utilization in experimental circuit layouts. As an application, a 64-b multiplier with 32-kb RAM and 65-kb ROM using a 1.4-M transistor sea of gates (SOG) has been developed, using 0.8-μm two-layer-metal CMOS. Gate density of 1.5 kg/mm2 and bit densities of 1.9 kb/mm2 for RAM and 6.3/mm2 for ROM have been achieved","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114806825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of an analog front-end chip relating to a video phone for transmission of audio signals and freeze-frame video images over voice-grade telephone lines. The device is implemented in a 3-μm CMOS process, utilizes switched-capacitor circuit technology and contains major functional blocks, such as a synchronous demodulator, transmit/receive filters, baseband and interpolating filters, an 8-bit digital-to-analog converter, a programmable gain amplifier, and clock and carrier recovery circuits. The chip occupies 27000 mil2 and dissipates 100 mW. System and circuit aspects of the design are discussed
{"title":"CMOS analog front-end for conversational video phone modem","authors":"C. Solomon, L. Ozcolak, G. Sellani, W. E. Brisco","doi":"10.1109/CICC.1989.56706","DOIUrl":"https://doi.org/10.1109/CICC.1989.56706","url":null,"abstract":"A description is given of an analog front-end chip relating to a video phone for transmission of audio signals and freeze-frame video images over voice-grade telephone lines. The device is implemented in a 3-μm CMOS process, utilizes switched-capacitor circuit technology and contains major functional blocks, such as a synchronous demodulator, transmit/receive filters, baseband and interpolating filters, an 8-bit digital-to-analog converter, a programmable gain amplifier, and clock and carrier recovery circuits. The chip occupies 27000 mil2 and dissipates 100 mW. System and circuit aspects of the design are discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116201957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A system of four integrated circuits along with discretes that form part of an implantable defibrillator is outlined. Circuit techniques to reduce battery power drain and a 12-bit integrating analog-to-digital converter that monitors several system utility voltages including battery terminal voltage, are presented. Typical system current drain is 20 μA
{"title":"A four chip implantable defibrillator/pacemaker chipset","authors":"J. Ryan, K. Carroll, B. Pless","doi":"10.1109/CICC.1989.56708","DOIUrl":"https://doi.org/10.1109/CICC.1989.56708","url":null,"abstract":"A system of four integrated circuits along with discretes that form part of an implantable defibrillator is outlined. Circuit techniques to reduce battery power drain and a 12-bit integrating analog-to-digital converter that monitors several system utility voltages including battery terminal voltage, are presented. Typical system current drain is 20 μA","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121989306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The architecture of an N-×M-bit, pipelined, datapath multiplier compiler. The architecture allows the total delay through the multiplier to be broken into the individual delays through each column of the array. The algorithm that determines where pipeline stage columns should be inserted is efficient because it uses a simple model for the column delays. Since pipeline stages are inserted only where necessary, the compiler can produce an optimized multiplier that can be easily integrated into a fully pipelined system. Set-up and output delay times can also be used by the compiler to allow the designer to integrate the multiplier into a fully pipelined datapath
{"title":"A datapath multiplier with automatic insertion of pipeline stages","authors":"C. Asato, C. Ditzen, S. Dholakia","doi":"10.1109/CICC.1989.56815","DOIUrl":"https://doi.org/10.1109/CICC.1989.56815","url":null,"abstract":"The architecture of an N-×M-bit, pipelined, datapath multiplier compiler. The architecture allows the total delay through the multiplier to be broken into the individual delays through each column of the array. The algorithm that determines where pipeline stage columns should be inserted is efficient because it uses a simple model for the column delays. Since pipeline stages are inserted only where necessary, the compiler can produce an optimized multiplier that can be easily integrated into a fully pipelined system. Set-up and output delay times can also be used by the compiler to allow the designer to integrate the multiplier into a fully pipelined datapath","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125789898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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