A two-stage method is proposed for generating dense MOS modules. The first stage is generation of dense placements of FETs (field-effect transistors) from the gate-matrix layouts, using a gate matrix deformation method. The deformation of gate-matrix layouts is guided by the design rules, using FETs with meander channel structures if needed. The second stage is routing of metal wires to connect FETs in modules. The authors have developed a three-dimensional maze router by extending the method to cope with arbitrary multilayer connections with user-defined costs for the connections in each layer. The costs can be used to assign desired priorities for each metal layer in the routing. This method results in about 65% reduction in chip area compared with the gate matrix method for typical examples using three- or four-layer connections
{"title":"A gate matrix deformation and three-dimensional maze routing for dense MOS module generation","authors":"Y. Sone, S. Suzuki, K. Asada","doi":"10.1109/CICC.1989.56693","DOIUrl":"https://doi.org/10.1109/CICC.1989.56693","url":null,"abstract":"A two-stage method is proposed for generating dense MOS modules. The first stage is generation of dense placements of FETs (field-effect transistors) from the gate-matrix layouts, using a gate matrix deformation method. The deformation of gate-matrix layouts is guided by the design rules, using FETs with meander channel structures if needed. The second stage is routing of metal wires to connect FETs in modules. The authors have developed a three-dimensional maze router by extending the method to cope with arbitrary multilayer connections with user-defined costs for the connections in each layer. The costs can be used to assign desired priorities for each metal layer in the routing. This method results in about 65% reduction in chip area compared with the gate matrix method for typical examples using three- or four-layer connections","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast algorithm for computing the capacitance of a complicated 3-D geometry of ideal conductors in a uniform dielectric is described. The method is an acceleration of the standard integral-equation for multiconductor capacitance extraction. These integral-equation methods are slow because they lead to dense matrix problems which are typically solved with some form of Gaussian elimination. This implies that the computation grows like n3, where n is the number of tiles needed to accuracy-discretize the conductor surface charges. The authors present a preconditioned conjugate-gradient iterative algorithm with a multipole approximation to compute the iterates. This reduces the complexity so that accurate multiconductor capacitance calculations grow as nm, where m is the number of conductors
{"title":"A fast multipole algorithm for capacitance extraction of complex 3-D geometries","authors":"K. Nabors, Jacob K. White","doi":"10.1109/CICC.1989.56806","DOIUrl":"https://doi.org/10.1109/CICC.1989.56806","url":null,"abstract":"A fast algorithm for computing the capacitance of a complicated 3-D geometry of ideal conductors in a uniform dielectric is described. The method is an acceleration of the standard integral-equation for multiconductor capacitance extraction. These integral-equation methods are slow because they lead to dense matrix problems which are typically solved with some form of Gaussian elimination. This implies that the computation grows like n3, where n is the number of tiles needed to accuracy-discretize the conductor surface charges. The authors present a preconditioned conjugate-gradient iterative algorithm with a multipole approximation to compute the iterates. This reduces the complexity so that accurate multiconductor capacitance calculations grow as nm, where m is the number of conductors","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131104799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single-chip two-channel, 8-bit, analog input/output port with versatile input and output signal conditioning features has been produced. The part is primarily designed for applications in head-positioning servos in Winchester disk drive systems, where the ever-increasing requirement for increased performance and lower production costs has fueled the need for greater system integration
{"title":"Design of an analog 8-bit two-channel I/O ASIC for disk drive control applications","authors":"P. Quinlan","doi":"10.1109/CICC.1989.56732","DOIUrl":"https://doi.org/10.1109/CICC.1989.56732","url":null,"abstract":"A single-chip two-channel, 8-bit, analog input/output port with versatile input and output signal conditioning features has been produced. The part is primarily designed for applications in head-positioning servos in Winchester disk drive systems, where the ever-increasing requirement for increased performance and lower production costs has fueled the need for greater system integration","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124424440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. P. Gowni, P. Platt, A. Hawkins, W. Hiltpold, S. Douglass
A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance
{"title":"A 12 ns, CMOS programmable logic device for combinatorial applications","authors":"S. P. Gowni, P. Platt, A. Hawkins, W. Hiltpold, S. Douglass","doi":"10.1109/CICC.1989.56694","DOIUrl":"https://doi.org/10.1109/CICC.1989.56694","url":null,"abstract":"A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132451244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar
A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces
{"title":"ACACIA: the CMU analog design system","authors":"L. Carley, D. J. Garrod, R. Harjani, J. Kelly, T. Lim, Emil S. Ochotta, Rob A. Rutenbar","doi":"10.1109/CICC.1989.56685","DOIUrl":"https://doi.org/10.1109/CICC.1989.56685","url":null,"abstract":"A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132505328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A device model is described for the simulation of the effects of single-event and radiation phenomena on the operation of GaAs MESFETs. The model can be utilized in a circuit simulator to evaluate integrated-circuit designs and aid in the provision of adequate upset margins for various operating environments. Additional subcircuit construction is unnecessary since the electrical responses to the different phenomena are intrinsic to the device template. Example simulations using SPICE3 are described
{"title":"Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits","authors":"P. George, P. Ko, C. Hu","doi":"10.1109/CICC.1989.56725","DOIUrl":"https://doi.org/10.1109/CICC.1989.56725","url":null,"abstract":"A device model is described for the simulation of the effects of single-event and radiation phenomena on the operation of GaAs MESFETs. The model can be utilized in a circuit simulator to evaluate integrated-circuit designs and aid in the provision of adequate upset margins for various operating environments. Additional subcircuit construction is unnecessary since the electrical responses to the different phenomena are intrinsic to the device template. Example simulations using SPICE3 are described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131540736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
BILOW, a steady-state one-dimensional bipolar transistor simulator for the 77 K-300 K temperature range, is presented. Examples of internal device characteristics for a medium-voltage n-p-n silicon bipolar transistor demonstrate the capability of the simulation. Calculated current gain and unity gain frequency versus current density for temperatures down to liquid nitrogen temperature (77 K) are presented and discussed. It is concluded that the simulator is a very useful tool for investigating different design approaches and the influence of process design on the temperature dependence of bipolar transistor parameters
{"title":"Steady-state bipolar transistor simulator for the 77 K-300 K temperature range","authors":"M. Chrzanowska-Jeske, R. Jaeger","doi":"10.1109/CICC.1989.56720","DOIUrl":"https://doi.org/10.1109/CICC.1989.56720","url":null,"abstract":"BILOW, a steady-state one-dimensional bipolar transistor simulator for the 77 K-300 K temperature range, is presented. Examples of internal device characteristics for a medium-voltage n-p-n silicon bipolar transistor demonstrate the capability of the simulation. Calculated current gain and unity gain frequency versus current density for temperatures down to liquid nitrogen temperature (77 K) are presented and discussed. It is concluded that the simulator is a very useful tool for investigating different design approaches and the influence of process design on the temperature dependence of bipolar transistor parameters","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A rail-to-rail input/output CMOS amplifier is presented in which the shortcomings presented in previous designs have been eliminated. The small (0.3-mm2) amplifier has an acceptable common-mode rejection ratio (55 dB), valid for the entire common-mode range. The device handles up to 4 nF, and on a 5-V supply it drives 3.8 V pp into 100 Ω (0.1% total harmonic distortion, 10 kHz)
提出了一种轨对轨输入/输出CMOS放大器，消除了以往设计中存在的缺点。小型(0.3 mm2)放大器具有可接受的共模抑制比(55 dB)，适用于整个共模范围。该设备处理高达4nf，并在5v电源上驱动3.8 V pp到100 Ω(0.1%总谐波失真，10 kHz)
{"title":"A rail-to-rail input/output CMOS power amplifier","authors":"Matthijs D. Pardoen","doi":"10.1109/CICC.1989.56832","DOIUrl":"https://doi.org/10.1109/CICC.1989.56832","url":null,"abstract":"A rail-to-rail input/output CMOS amplifier is presented in which the shortcomings presented in previous designs have been eliminated. The small (0.3-mm2) amplifier has an acceptable common-mode rejection ratio (55 dB), valid for the entire common-mode range. The device handles up to 4 nF, and on a 5-V supply it drives 3.8 V pp into 100 Ω (0.1% total harmonic distortion, 10 kHz)","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"620 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117084456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W.R. Bullman, L.A. Davieau, H. Moscovitz, G. O'Donnell
A description is given of PANDA, a hierarchical, constraint-based mixed-mode VLSI module assembler. PANDA was developed as a testbed for exploring VLSI design methods and tools. It uses pitchmatching and abutment as the primary assembly technique with channel and river routers available as options. PANDA features a recursive compaction algorithm using depth-first searching, constraint resolution, and wire-length minimization to optimize layout area, while maintaining the input hierarchy. Instead of using a predetermined stand-off distance between cells, PANDA's abutment algorithm calculates the minimum distance required to guarantee no design-rule errors between modules. PANDA has the unique ability to assemble mixed-mode layouts, which are defined as a mixture of fixed-grid cells, such as hand layouts, and symbolic cells (virtual-grid), and places few constraints on the hierarchical description. Hierarchical models of over 70 K transistors have been assembled with layout densities as good as or better than achieved with hand layout
{"title":"PANDA-a hierarchical mixed mode VLSI module assembler","authors":"W.R. Bullman, L.A. Davieau, H. Moscovitz, G. O'Donnell","doi":"10.1109/CICC.1989.56820","DOIUrl":"https://doi.org/10.1109/CICC.1989.56820","url":null,"abstract":"A description is given of PANDA, a hierarchical, constraint-based mixed-mode VLSI module assembler. PANDA was developed as a testbed for exploring VLSI design methods and tools. It uses pitchmatching and abutment as the primary assembly technique with channel and river routers available as options. PANDA features a recursive compaction algorithm using depth-first searching, constraint resolution, and wire-length minimization to optimize layout area, while maintaining the input hierarchy. Instead of using a predetermined stand-off distance between cells, PANDA's abutment algorithm calculates the minimum distance required to guarantee no design-rule errors between modules. PANDA has the unique ability to assemble mixed-mode layouts, which are defined as a mixture of fixed-grid cells, such as hand layouts, and symbolic cells (virtual-grid), and places few constraints on the hierarchical description. Hierarchical models of over 70 K transistors have been assembled with layout densities as good as or better than achieved with hand layout","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Smith, C. Anagnostopoulos, C. Portmann, R. Rao, P. Valdenaire, H. Ching
Efforts to improve the tools and techniques for designing an analog cell library for analog/digital VLSI design are described. The techniques presented allow an analog IC designer to construct a library for cell-based design, as opposed to direct compilation of a full-custom analog/digital IC. Using this approach, the problem of automation is made more tractable, and the result is a more robust, but still flexible, system for mixed analog/digital ASIC (application-specific integrated circuit) design. By combining a study of device scaling issues, careful choice of layout topologies, together with modular construction of cells using lambda based rules, it is possible to extend the lifetime of an analog cell library. Cells have been constructed for both 2- and 1.5-μm down-gate-width technologies with the ability to scale down to a 1-μm process
{"title":"Construction of analog library cells for analog/digital ASICs using novel design and modular assembly techniques","authors":"M. Smith, C. Anagnostopoulos, C. Portmann, R. Rao, P. Valdenaire, H. Ching","doi":"10.1109/CICC.1989.56833","DOIUrl":"https://doi.org/10.1109/CICC.1989.56833","url":null,"abstract":"Efforts to improve the tools and techniques for designing an analog cell library for analog/digital VLSI design are described. The techniques presented allow an analog IC designer to construct a library for cell-based design, as opposed to direct compilation of a full-custom analog/digital IC. Using this approach, the problem of automation is made more tractable, and the result is a more robust, but still flexible, system for mixed analog/digital ASIC (application-specific integrated circuit) design. By combining a study of device scaling issues, careful choice of layout topologies, together with modular construction of cells using lambda based rules, it is possible to extend the lifetime of an analog cell library. Cells have been constructed for both 2- and 1.5-μm down-gate-width technologies with the ability to scale down to a 1-μm process","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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