A two-stage method is proposed for generating dense MOS modules. The first stage is generation of dense placements of FETs (field-effect transistors) from the gate-matrix layouts, using a gate matrix deformation method. The deformation of gate-matrix layouts is guided by the design rules, using FETs with meander channel structures if needed. The second stage is routing of metal wires to connect FETs in modules. The authors have developed a three-dimensional maze router by extending the method to cope with arbitrary multilayer connections with user-defined costs for the connections in each layer. The costs can be used to assign desired priorities for each metal layer in the routing. This method results in about 65% reduction in chip area compared with the gate matrix method for typical examples using three- or four-layer connections
{"title":"A gate matrix deformation and three-dimensional maze routing for dense MOS module generation","authors":"Y. Sone, S. Suzuki, K. Asada","doi":"10.1109/CICC.1989.56693","DOIUrl":"https://doi.org/10.1109/CICC.1989.56693","url":null,"abstract":"A two-stage method is proposed for generating dense MOS modules. The first stage is generation of dense placements of FETs (field-effect transistors) from the gate-matrix layouts, using a gate matrix deformation method. The deformation of gate-matrix layouts is guided by the design rules, using FETs with meander channel structures if needed. The second stage is routing of metal wires to connect FETs in modules. The authors have developed a three-dimensional maze router by extending the method to cope with arbitrary multilayer connections with user-defined costs for the connections in each layer. The costs can be used to assign desired priorities for each metal layer in the routing. This method results in about 65% reduction in chip area compared with the gate matrix method for typical examples using three- or four-layer connections","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast algorithm for computing the capacitance of a complicated 3-D geometry of ideal conductors in a uniform dielectric is described. The method is an acceleration of the standard integral-equation for multiconductor capacitance extraction. These integral-equation methods are slow because they lead to dense matrix problems which are typically solved with some form of Gaussian elimination. This implies that the computation grows like n3, where n is the number of tiles needed to accuracy-discretize the conductor surface charges. The authors present a preconditioned conjugate-gradient iterative algorithm with a multipole approximation to compute the iterates. This reduces the complexity so that accurate multiconductor capacitance calculations grow as nm, where m is the number of conductors
{"title":"A fast multipole algorithm for capacitance extraction of complex 3-D geometries","authors":"K. Nabors, Jacob K. White","doi":"10.1109/CICC.1989.56806","DOIUrl":"https://doi.org/10.1109/CICC.1989.56806","url":null,"abstract":"A fast algorithm for computing the capacitance of a complicated 3-D geometry of ideal conductors in a uniform dielectric is described. The method is an acceleration of the standard integral-equation for multiconductor capacitance extraction. These integral-equation methods are slow because they lead to dense matrix problems which are typically solved with some form of Gaussian elimination. This implies that the computation grows like n3, where n is the number of tiles needed to accuracy-discretize the conductor surface charges. The authors present a preconditioned conjugate-gradient iterative algorithm with a multipole approximation to compute the iterates. This reduces the complexity so that accurate multiconductor capacitance calculations grow as nm, where m is the number of conductors","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131104799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Fisher, Kuo-Tung Chang, F. Pintchovski, J. Klein, K. Fu, S. Lai, R. Dillard
A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps have been measured on a development 16 K-gate array with 0.8-μm gate lengths
{"title":"A submicron CMOS triple level metal technology for ASIC applications","authors":"D. Fisher, Kuo-Tung Chang, F. Pintchovski, J. Klein, K. Fu, S. Lai, R. Dillard","doi":"10.1109/CICC.1989.56781","DOIUrl":"https://doi.org/10.1109/CICC.1989.56781","url":null,"abstract":"A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps have been measured on a development 16 K-gate array with 0.8-μm gate lengths","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114028345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W.R. Bullman, L.A. Davieau, H. Moscovitz, G. O'Donnell
A description is given of PANDA, a hierarchical, constraint-based mixed-mode VLSI module assembler. PANDA was developed as a testbed for exploring VLSI design methods and tools. It uses pitchmatching and abutment as the primary assembly technique with channel and river routers available as options. PANDA features a recursive compaction algorithm using depth-first searching, constraint resolution, and wire-length minimization to optimize layout area, while maintaining the input hierarchy. Instead of using a predetermined stand-off distance between cells, PANDA's abutment algorithm calculates the minimum distance required to guarantee no design-rule errors between modules. PANDA has the unique ability to assemble mixed-mode layouts, which are defined as a mixture of fixed-grid cells, such as hand layouts, and symbolic cells (virtual-grid), and places few constraints on the hierarchical description. Hierarchical models of over 70 K transistors have been assembled with layout densities as good as or better than achieved with hand layout
{"title":"PANDA-a hierarchical mixed mode VLSI module assembler","authors":"W.R. Bullman, L.A. Davieau, H. Moscovitz, G. O'Donnell","doi":"10.1109/CICC.1989.56820","DOIUrl":"https://doi.org/10.1109/CICC.1989.56820","url":null,"abstract":"A description is given of PANDA, a hierarchical, constraint-based mixed-mode VLSI module assembler. PANDA was developed as a testbed for exploring VLSI design methods and tools. It uses pitchmatching and abutment as the primary assembly technique with channel and river routers available as options. PANDA features a recursive compaction algorithm using depth-first searching, constraint resolution, and wire-length minimization to optimize layout area, while maintaining the input hierarchy. Instead of using a predetermined stand-off distance between cells, PANDA's abutment algorithm calculates the minimum distance required to guarantee no design-rule errors between modules. PANDA has the unique ability to assemble mixed-mode layouts, which are defined as a mixture of fixed-grid cells, such as hand layouts, and symbolic cells (virtual-grid), and places few constraints on the hierarchical description. Hierarchical models of over 70 K transistors have been assembled with layout densities as good as or better than achieved with hand layout","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VLSI design methodologies with fewer abstraction levels than usual are discussed. It is felt that such methods are easier to use and to automatize, while still providing efficient chips. RISC (reduced-instruction-set computer) and CISC (complex-instruction-set computer) methodologies as well as a floorplan-oriented methodology are discussed
{"title":"Design methodologies and CAD tools [VLSI]","authors":"C. Piguet","doi":"10.1109/CICC.1989.56845","DOIUrl":"https://doi.org/10.1109/CICC.1989.56845","url":null,"abstract":"VLSI design methodologies with fewer abstraction levels than usual are discussed. It is felt that such methods are easier to use and to automatize, while still providing efficient chips. RISC (reduced-instruction-set computer) and CISC (complex-instruction-set computer) methodologies as well as a floorplan-oriented methodology are discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114439563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A rail-to-rail input/output CMOS amplifier is presented in which the shortcomings presented in previous designs have been eliminated. The small (0.3-mm2) amplifier has an acceptable common-mode rejection ratio (55 dB), valid for the entire common-mode range. The device handles up to 4 nF, and on a 5-V supply it drives 3.8 V pp into 100 Ω (0.1% total harmonic distortion, 10 kHz)
提出了一种轨对轨输入/输出CMOS放大器，消除了以往设计中存在的缺点。小型(0.3 mm2)放大器具有可接受的共模抑制比(55 dB)，适用于整个共模范围。该设备处理高达4nf，并在5v电源上驱动3.8 V pp到100 Ω(0.1%总谐波失真，10 kHz)
{"title":"A rail-to-rail input/output CMOS power amplifier","authors":"Matthijs D. Pardoen","doi":"10.1109/CICC.1989.56832","DOIUrl":"https://doi.org/10.1109/CICC.1989.56832","url":null,"abstract":"A rail-to-rail input/output CMOS amplifier is presented in which the shortcomings presented in previous designs have been eliminated. The small (0.3-mm2) amplifier has an acceptable common-mode rejection ratio (55 dB), valid for the entire common-mode range. The device handles up to 4 nF, and on a 5-V supply it drives 3.8 V pp into 100 Ω (0.1% total harmonic distortion, 10 kHz)","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"620 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117084456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 440000-transistor, full-custom CMOS processor that is used as the basis of a parallel computer system is described. The primary design goal was to produce a processor that performed roughly an order of magnitude faster than its predecessor. The author discusses the chip-level architecture of the processor, comparing it to the original design, and shows what was done architecturally to increase the performance by an order of magnitude
{"title":"A custom processor for use in a parallel computer system","authors":"D. Wilde","doi":"10.1109/CICC.1989.56728","DOIUrl":"https://doi.org/10.1109/CICC.1989.56728","url":null,"abstract":"A 440000-transistor, full-custom CMOS processor that is used as the basis of a parallel computer system is described. The primary design goal was to produce a processor that performed roughly an order of magnitude faster than its predecessor. The author discusses the chip-level architecture of the processor, comparing it to the original design, and shows what was done architecturally to increase the performance by an order of magnitude","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123247477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Large change sensitivities are needed in many situations since parameters are subjected to variations that are not small. The authors have implemented three different methods in SPICE3 for computing DC large change sensitivities. The incremental approach is observed to give speed improvements of more than an order of magnitude over the direct approach
{"title":"Computing DC large change sensitivities","authors":"D. Divekar, H. Daseking, R. Apte","doi":"10.1109/CICC.1989.56804","DOIUrl":"https://doi.org/10.1109/CICC.1989.56804","url":null,"abstract":"Large change sensitivities are needed in many situations since parameters are subjected to variations that are not small. The authors have implemented three different methods in SPICE3 for computing DC large change sensitivities. The incremental approach is observed to give speed improvements of more than an order of magnitude over the direct approach","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121741405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A comprehensive bipolar transistor model based on the Gummel-Poon model for low-temperature circuit simulation is presented. Low-temperature physical properties such as doping-dependent dielectric permittivity, temperature-dependent free-carrier mobility and intrinsic carrier density, and deionization of impurity dopants are included in the model. Consequently, the model does not require temperature-fitting parameters as does the Gummel-Poon model. Comparisons of the present model with the Gummel-Poon model, with experimental data, and with PISCES two-dimensional device simulation are included
{"title":"Physics-based bipolar transistor model for low-temperature circuit simulation","authors":"J. Liou, J. Yuan","doi":"10.1109/CICC.1989.56719","DOIUrl":"https://doi.org/10.1109/CICC.1989.56719","url":null,"abstract":"A comprehensive bipolar transistor model based on the Gummel-Poon model for low-temperature circuit simulation is presented. Low-temperature physical properties such as doping-dependent dielectric permittivity, temperature-dependent free-carrier mobility and intrinsic carrier density, and deionization of impurity dopants are included in the model. Consequently, the model does not require temperature-fitting parameters as does the Gummel-Poon model. Comparisons of the present model with the Gummel-Poon model, with experimental data, and with PISCES two-dimensional device simulation are included","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121884748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. C. Munroe, D. R. Arsenault, K. E. Thompson, A. Lattes
The authors designed, fabricated, and tested a four-channel, analog-ternary charge-coupled device (CCD) correlator that extends the state of the art in several important areas. In addition to a sampling rate up to 40 Ms/s, dynamic range of 66 dB, and nonlinearity below -50 dB, the device exhibits a level of integration and user-friendliness not previously available. The correlator is intended for use in communications and radar systems where pseudonoise codes are used
{"title":"Programmable, four-channel, 128-sample, 40-Ms/s analog-ternary correlator","authors":"S. C. Munroe, D. R. Arsenault, K. E. Thompson, A. Lattes","doi":"10.1109/CICC.1989.56828","DOIUrl":"https://doi.org/10.1109/CICC.1989.56828","url":null,"abstract":"The authors designed, fabricated, and tested a four-channel, analog-ternary charge-coupled device (CCD) correlator that extends the state of the art in several important areas. In addition to a sampling rate up to 40 Ms/s, dynamic range of 66 dB, and nonlinearity below -50 dB, the device exhibits a level of integration and user-friendliness not previously available. The correlator is intended for use in communications and radar systems where pseudonoise codes are used","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122775415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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