This work introduces a designing and implementing of digitally controlled gain amplifier for audio frequency range applications. The amplifier circuit is based on the Switched-MOSFET (SM) technique, which is appropriate for low voltage operation. The MOSFET Only Current Divider (MOCD) is employed to realize digitally controlled unite. The designed amplifier is fabricated in SCNE technology (1.2 /spl mu/m) from MOSIS with /spl plusmn/1.5V power supply.
{"title":"CMOS digitally controlled amplifier for low voltage applications","authors":"F. Farag","doi":"10.1109/ICM.2003.238247","DOIUrl":"https://doi.org/10.1109/ICM.2003.238247","url":null,"abstract":"This work introduces a designing and implementing of digitally controlled gain amplifier for audio frequency range applications. The amplifier circuit is based on the Switched-MOSFET (SM) technique, which is appropriate for low voltage operation. The MOSFET Only Current Divider (MOCD) is employed to realize digitally controlled unite. The designed amplifier is fabricated in SCNE technology (1.2 /spl mu/m) from MOSIS with /spl plusmn/1.5V power supply.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B.S. Makki, M. Kargar, S. Mohajerzadeh, T. Maleki, D. Shahrjerdi
Polycrystalline germanium-based thermopiles are fabricated at reduced temperatures on plastic substrate. The Amorphous Ge film, deposited using electron beam evaporation, is post-treated to form a polycrystalline film. The annealing process has been performed at temperatures ranging from 120 to 175/spl deg/C. The physical characteristics of Ge films have been investigated using XRD and SEM tools confirming the crystallinity of the annealed films. A Seebeck value of 100 /spl mu/V//spl deg/C is extracted for the Ge-Al junctions. A novel ultraviolet assisted micro-machining is presented in which anisotropic etching of PET plastic substrate is achieved. The etching of plastic is performed in a DMF solution and in presence of ultraviolet light illumination with a typical intensity of 15 mW/hr measured at a wavelength of 360 nm. This technique has been applied to realize square membrane, craters, micro-gears and micro-molds.
{"title":"Application of PET plastics in micro-sensor fabrication","authors":"B.S. Makki, M. Kargar, S. Mohajerzadeh, T. Maleki, D. Shahrjerdi","doi":"10.1109/ICM.2003.237932","DOIUrl":"https://doi.org/10.1109/ICM.2003.237932","url":null,"abstract":"Polycrystalline germanium-based thermopiles are fabricated at reduced temperatures on plastic substrate. The Amorphous Ge film, deposited using electron beam evaporation, is post-treated to form a polycrystalline film. The annealing process has been performed at temperatures ranging from 120 to 175/spl deg/C. The physical characteristics of Ge films have been investigated using XRD and SEM tools confirming the crystallinity of the annealed films. A Seebeck value of 100 /spl mu/V//spl deg/C is extracted for the Ge-Al junctions. A novel ultraviolet assisted micro-machining is presented in which anisotropic etching of PET plastic substrate is achieved. The etching of plastic is performed in a DMF solution and in presence of ultraviolet light illumination with a typical intensity of 15 mW/hr measured at a wavelength of 360 nm. This technique has been applied to realize square membrane, craters, micro-gears and micro-molds.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122830572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An adaptive digital calibration technique for enhancing the accuracy of Pipelined Analog-to-Digital Converters (ADC) is discussed in this paper. In contrast to the traditional approach that uses ideal bit-weights for calculation of digital output, the approach adopted here is based on calculating digital output using actual bit-weights. Actual bit-weights are extracted by measuring discontinuities at points where the bit transition occurs and applying the Least Mean Square (LMS) algorithm in the sense that mean-squared error is minimized to improve the linearity of the ADC. In contrast to the traditional MDAC residue characteristics that introduce errors in both stage-gain and reference terms, the modified MDAC architecture used here has only one error term in residue characteristic. Simulation results demonstrate the extension of inherent accuracy of ADC to 16-Bits and more.
{"title":"An adaptive digital domain calibration technique for pipelined Analog-To-Digital Converters","authors":"H. Hedayati, S. M. Kashmiri, O. Shoaei","doi":"10.1109/ICM.2003.238617","DOIUrl":"https://doi.org/10.1109/ICM.2003.238617","url":null,"abstract":"An adaptive digital calibration technique for enhancing the accuracy of Pipelined Analog-to-Digital Converters (ADC) is discussed in this paper. In contrast to the traditional approach that uses ideal bit-weights for calculation of digital output, the approach adopted here is based on calculating digital output using actual bit-weights. Actual bit-weights are extracted by measuring discontinuities at points where the bit transition occurs and applying the Least Mean Square (LMS) algorithm in the sense that mean-squared error is minimized to improve the linearity of the ADC. In contrast to the traditional MDAC residue characteristics that introduce errors in both stage-gain and reference terms, the modified MDAC architecture used here has only one error term in residue characteristic. Simulation results demonstrate the extension of inherent accuracy of ADC to 16-Bits and more.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122938167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A technique for a low voltage low distortion digitally programmable current-mode continuous-time filter is proposed. The technique of digitally programmable is based on an inherent linear MOST-only current division technique. This technique is used to design a digitally programmable current mirror (DPCM). Then we used the (DPCM) to design a digitally programmable current mode integrator. As an application for the digitally programmable current mode integrator, a digitally programmable analog filter is designed. Both of selectivity and center frequency can be programmed independently. The filter has been simulated using the parameters of 0.8 /spl mu/m CMOS process, and 3volt power supply.
{"title":"A low voltage digitally programmable current-mode filter","authors":"H. Hamed","doi":"10.1109/ICM.2003.238013","DOIUrl":"https://doi.org/10.1109/ICM.2003.238013","url":null,"abstract":"A technique for a low voltage low distortion digitally programmable current-mode continuous-time filter is proposed. The technique of digitally programmable is based on an inherent linear MOST-only current division technique. This technique is used to design a digitally programmable current mirror (DPCM). Then we used the (DPCM) to design a digitally programmable current mode integrator. As an application for the digitally programmable current mode integrator, a digitally programmable analog filter is designed. Both of selectivity and center frequency can be programmed independently. The filter has been simulated using the parameters of 0.8 /spl mu/m CMOS process, and 3volt power supply.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Small area, Low power and high speed circuits are essential components propelling today's microprocessors. Domino logic gates are basic components in this family. One disadvantage pertaining to domino gates is the trade-off between speed and noise immunity, which is highly affected by leakage currents. In this paper, we propose the usage of reverse bulk node voltage in order to resolve this trade-off, while reducing the active leakage power consumed. A 50% reduction in active leakage power, and 40% saving in gate delay were achieved.
{"title":"Leakage control for large fan-in Domino gates using substrate biasing","authors":"A. Youssef, M. Anis, M. Elmasry","doi":"10.1109/ICM.2003.238360","DOIUrl":"https://doi.org/10.1109/ICM.2003.238360","url":null,"abstract":"Small area, Low power and high speed circuits are essential components propelling today's microprocessors. Domino logic gates are basic components in this family. One disadvantage pertaining to domino gates is the trade-off between speed and noise immunity, which is highly affected by leakage currents. In this paper, we propose the usage of reverse bulk node voltage in order to resolve this trade-off, while reducing the active leakage power consumed. A 50% reduction in active leakage power, and 40% saving in gate delay were achieved.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126570067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper shows that the uncertainties in voltage levels in mixed-signal circuits can compromise test quality and cause operational circuits to be considered as failed. A test scheme is developed where a subset of the test vectors produced by a pseudorandom test pattern generator is constructed to eliminate patterns that may lead to test failure. The size of this subset is shown to be a function of the level of uncertainty. It is also proven that, although test quality increases, coverage may decrease.
{"title":"Effective pseudorandom testing of mixed-signal circuits","authors":"H. Amer, A. Salama","doi":"10.1109/ICM.2003.238010","DOIUrl":"https://doi.org/10.1109/ICM.2003.238010","url":null,"abstract":"This paper shows that the uncertainties in voltage levels in mixed-signal circuits can compromise test quality and cause operational circuits to be considered as failed. A test scheme is developed where a subset of the test vectors produced by a pseudorandom test pattern generator is constructed to eliminate patterns that may lead to test failure. The size of this subset is shown to be a function of the level of uncertainty. It is also proven that, although test quality increases, coverage may decrease.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131170916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A wide bandwidth BiCMOS differential voltage second generation current conveyor (DVCCII) is presented. It has the advantages of a wide bandwidth, low input impedance at X-terminal, and low voltage operation. It is a useful building block for analog circuits, especially for application demanding differential input. It can be directly used with MOS transistors operating in ohmic region to implement required analogue functions. As applications, DVCCII based OTA, and DVCCII based analog multiplier are presented. PSPICE simulations indicate the very good performance of the proposed DVCCII and its circuits applications.
{"title":"/spl plusmn/1.5 V supply, BiCMOS wideband DVCCII and its applications as programmable OTA and analog multiplier","authors":"H. Hamed","doi":"10.1109/ICM.2003.238358","DOIUrl":"https://doi.org/10.1109/ICM.2003.238358","url":null,"abstract":"A wide bandwidth BiCMOS differential voltage second generation current conveyor (DVCCII) is presented. It has the advantages of a wide bandwidth, low input impedance at X-terminal, and low voltage operation. It is a useful building block for analog circuits, especially for application demanding differential input. It can be directly used with MOS transistors operating in ohmic region to implement required analogue functions. As applications, DVCCII based OTA, and DVCCII based analog multiplier are presented. PSPICE simulations indicate the very good performance of the proposed DVCCII and its circuits applications.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"186 5 Suppl Nature 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123256080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, Switched Current Technique is at the aim of interest. However, the running of this kind of cells is disturbed by several error sources which affect its performances. The Grounded Gate Class AB Memory Cell is adopted because it solves some of non-idealities affecting the conventional second generation Class A memory cell. Namely, the output to input conductances ratio error, maximum allowed input current and other imperfections like charge injection error and input to output conductance ratio error. Nevertheless, this cell has to be more improved. Thanks to technology evolution some error sources are becoming negligible such as errors due to charge injection. Thus we focused our work on optimizing the cell's settling time in order to get the 'fastest' cell. Since the key point to design high performance integrator is to design high performance memory cells, we use the optimized class AB grounded gate memory cell to design improved integrators suitable for designing high performance filters. MATLAB, AMS- 0.35 /spl mu/m process, SPICE and CADENCE simulation results are presented to show the good reached results.
{"title":"An optimized Switched Current integrator","authors":"M. Fakhfakh, M. Loulou, N. Masmoudi","doi":"10.1109/ICM.2003.238356","DOIUrl":"https://doi.org/10.1109/ICM.2003.238356","url":null,"abstract":"Nowadays, Switched Current Technique is at the aim of interest. However, the running of this kind of cells is disturbed by several error sources which affect its performances. The Grounded Gate Class AB Memory Cell is adopted because it solves some of non-idealities affecting the conventional second generation Class A memory cell. Namely, the output to input conductances ratio error, maximum allowed input current and other imperfections like charge injection error and input to output conductance ratio error. Nevertheless, this cell has to be more improved. Thanks to technology evolution some error sources are becoming negligible such as errors due to charge injection. Thus we focused our work on optimizing the cell's settling time in order to get the 'fastest' cell. Since the key point to design high performance integrator is to design high performance memory cells, we use the optimized class AB grounded gate memory cell to design improved integrators suitable for designing high performance filters. MATLAB, AMS- 0.35 /spl mu/m process, SPICE and CADENCE simulation results are presented to show the good reached results.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114439008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. A. Metwally, I. M. Hafez, H. El-Ghitani, Hani Ragai
A new architecture of a CMOS voltage-controlled current conveyor is introduced. The conveyor satisfies the matrix-relationship of the second-generation conveyors and exhibits high frequency, low power consumption, low noise and small chip area as well as simple parameter-adjustment mechanism, so it can complete with BJT and BiCMOS conventional conveyors in different applications.
{"title":"Novel CMOS voltage-controlled current conveyor","authors":"E. A. Metwally, I. M. Hafez, H. El-Ghitani, Hani Ragai","doi":"10.1109/ICM.2003.238357","DOIUrl":"https://doi.org/10.1109/ICM.2003.238357","url":null,"abstract":"A new architecture of a CMOS voltage-controlled current conveyor is introduced. The conveyor satisfies the matrix-relationship of the second-generation conveyors and exhibits high frequency, low power consumption, low noise and small chip area as well as simple parameter-adjustment mechanism, so it can complete with BJT and BiCMOS conventional conveyors in different applications.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126897226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the usage of the family of space filling curves in capacitor design. Some of the known family members are studied regarding their applications as area efficient capacitor elements. One of the main advantages of these structures is that they divide the space into two continuous electrodes. This makes extra connecting vias and metal layers unnecessary, and enables implementation on a single metal layer. The capacitance of the suggested structures are obtained and compared with some of the reference structures such as the interdigitated and woven capacitors.
{"title":"Investigation of space filling capacitors","authors":"T. Moselhy, H. Ghali, H. Ragaie, H. Haddara","doi":"10.1109/ICM.2003.237831","DOIUrl":"https://doi.org/10.1109/ICM.2003.237831","url":null,"abstract":"This paper investigates the usage of the family of space filling curves in capacitor design. Some of the known family members are studied regarding their applications as area efficient capacitor elements. One of the main advantages of these structures is that they divide the space into two continuous electrodes. This makes extra connecting vias and metal layers unnecessary, and enables implementation on a single metal layer. The capacitance of the suggested structures are obtained and compared with some of the reference structures such as the interdigitated and woven capacitors.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127187862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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