M. Zakaria, M. Madbouly, M. El-Nozahi, M. Dessouky
The design of highly non-linear circuits is a challenging and time-consuming task both for designers and design-automation tools. This paper presents a method for automated design of such circuits. By combining equations and heuristics with simulation-corrections, it allows to achieve the accuracy of optimization-based sizing with the speed of knowledge-based sizing one. The correction scheme is also used to reduce the number of independent variables. Sizing, speed and accuracy allow it to be used in the design and technology migration of digital libraries, full-custom cells as well as dynamically during timing analysis to compensate long critical paths. Applications are also appealing for highly non-linear analog functions. A prototype tool has been implemented in MATLAB.
{"title":"Knowledge-based design automation of highly non-linear circuits using simulation correction","authors":"M. Zakaria, M. Madbouly, M. El-Nozahi, M. Dessouky","doi":"10.1109/ICM.2003.238303","DOIUrl":"https://doi.org/10.1109/ICM.2003.238303","url":null,"abstract":"The design of highly non-linear circuits is a challenging and time-consuming task both for designers and design-automation tools. This paper presents a method for automated design of such circuits. By combining equations and heuristics with simulation-corrections, it allows to achieve the accuracy of optimization-based sizing with the speed of knowledge-based sizing one. The correction scheme is also used to reduce the number of independent variables. Sizing, speed and accuracy allow it to be used in the design and technology migration of digital libraries, full-custom cells as well as dynamically during timing analysis to compensate long critical paths. Applications are also appealing for highly non-linear analog functions. A prototype tool has been implemented in MATLAB.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127393559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Shahrjerdi, B. Hekmatshoar, S. Mohajerzadeh, S. Darbari
Fabrication of depletion-mode poly Ge TFTs with field-effect hole mobility of 120 cm/sup 2//V-s on flexible PET substrates is reported. The fabricated TFTs show an ON/OFF ratio of 4/spl times/l0/sup 4/. All of the fabrication steps have been done at temperatures as low as 130/spl deg/C. A recently established stress-assisted copper-induced crystallization technique has been exploited to crystallize the amorphous Ge (a-Ge) layer. Mechanical compressive stress has been applied to the Ge layer by bending the flexible substrate inward. Proper patterning of the a-Ge layer before thermo-mechanical post-treatment alleviates the density of cracks induced in the Ge layer as the main repercussion of the interfacial stress.
{"title":"Low temperature fabrication of high mobility poly-Ge TFTs on plastic","authors":"D. Shahrjerdi, B. Hekmatshoar, S. Mohajerzadeh, S. Darbari","doi":"10.1109/ICM.2003.237966","DOIUrl":"https://doi.org/10.1109/ICM.2003.237966","url":null,"abstract":"Fabrication of depletion-mode poly Ge TFTs with field-effect hole mobility of 120 cm/sup 2//V-s on flexible PET substrates is reported. The fabricated TFTs show an ON/OFF ratio of 4/spl times/l0/sup 4/. All of the fabrication steps have been done at temperatures as low as 130/spl deg/C. A recently established stress-assisted copper-induced crystallization technique has been exploited to crystallize the amorphous Ge (a-Ge) layer. Mechanical compressive stress has been applied to the Ge layer by bending the flexible substrate inward. Proper patterning of the a-Ge layer before thermo-mechanical post-treatment alleviates the density of cracks induced in the Ge layer as the main repercussion of the interfacial stress.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122698763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A rate-1/3 8-state log-MAP turbo decoder architecture for third-generation wireless data terminals is designed. Several architectural and logic level techniques are applied throughout the design to reduce area, power, and increase throughout of the turbo decoder. The decoder is described in VHDL and synthesized into a 0.18 /spl mu/ 6-metal CMOS standard cell library. The synthesized decoder has a core area of about 0.54 mm/sup 2/. At 100 MHz clock frequency, the decoder achieves a data rate of 5 Mb/s using 5 iterations and produces power consumption of about 376 mW; that amounts to an energy consumption of about 15 nJ/b/iteration.
{"title":"Design of an energy-efficient turbo decoder for 3/sup RD/ generation wireless applications","authors":"I.A. Al-Mohandes, M. Elmasry","doi":"10.1109/ICM.2003.238428","DOIUrl":"https://doi.org/10.1109/ICM.2003.238428","url":null,"abstract":"A rate-1/3 8-state log-MAP turbo decoder architecture for third-generation wireless data terminals is designed. Several architectural and logic level techniques are applied throughout the design to reduce area, power, and increase throughout of the turbo decoder. The decoder is described in VHDL and synthesized into a 0.18 /spl mu/ 6-metal CMOS standard cell library. The synthesized decoder has a core area of about 0.54 mm/sup 2/. At 100 MHz clock frequency, the decoder achieves a data rate of 5 Mb/s using 5 iterations and produces power consumption of about 376 mW; that amounts to an energy consumption of about 15 nJ/b/iteration.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131824411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cascode compensation increases the speed of two stage amplifiers compared to conventional Miller compensation. The cost is an increase of pole zero complexity such that traditional open loop analysis will not lead to intuitive design equations. This paper introduces a systematic design approach of cascode compensated two stage OTAs. The parametric transfer function, settling error and thermal noise equations were first extracted from the small signal equivalent circuit of the OTA, then a set of poles and zeros which best suited settling requirements was asserted into the non-linear equations relating pole zero and circuit parameters, through which circuit parameters were calculated. Using the system level results Spice simulation of the OTA was performed in a 0.35 /spl mu/m CMOS process. The simulated OTA achieved a DC-gain of 100dB with a 120MHz bandwidth and a 62/spl deg/ phase margin from a 3V power supply. The measured dissipated power was 2.01 mW with a settling time of 7 nSec.
{"title":"Systematic steps in design of a CMOS two-stage cascode-compensated OTA","authors":"S. M. Kashmiri, H. Hedayati, O. Shoaei","doi":"10.1109/ICM.2003.238012","DOIUrl":"https://doi.org/10.1109/ICM.2003.238012","url":null,"abstract":"Cascode compensation increases the speed of two stage amplifiers compared to conventional Miller compensation. The cost is an increase of pole zero complexity such that traditional open loop analysis will not lead to intuitive design equations. This paper introduces a systematic design approach of cascode compensated two stage OTAs. The parametric transfer function, settling error and thermal noise equations were first extracted from the small signal equivalent circuit of the OTA, then a set of poles and zeros which best suited settling requirements was asserted into the non-linear equations relating pole zero and circuit parameters, through which circuit parameters were calculated. Using the system level results Spice simulation of the OTA was performed in a 0.35 /spl mu/m CMOS process. The simulated OTA achieved a DC-gain of 100dB with a 120MHz bandwidth and a 62/spl deg/ phase margin from a 3V power supply. The measured dissipated power was 2.01 mW with a settling time of 7 nSec.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133493863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. de Moor, Y. Creten, C. Goessens, B. Grietens, V. Leonov, J. Vermeiren, C. van Hoof
In this paper, we discuss the SiGe technology for uncooled microbolometer arrays of small format, ie 200/spl times/1 and 14/spl times/14, is transferred from IMEC to XenICs allowing of the poly-SiGe arrays for application in non-contact temperature measurements, infrared spectroscopy, technological process monitoring, quality control, etc. The arrays demonstrate an exceptional uniformity, about 100% pixel yield, 100% operability, and a NETD of about 100 mK at a readout level. These advantages combined with a possibility of hermetic zero-level micropacking make the SiGe technology a proper one for the low-cost production of infrared arrays.
{"title":"Thermal infrared detection using linear arrays of poly SiGe uncooled microbolometers","authors":"P. de Moor, Y. Creten, C. Goessens, B. Grietens, V. Leonov, J. Vermeiren, C. van Hoof","doi":"10.1109/ICM.2003.238498","DOIUrl":"https://doi.org/10.1109/ICM.2003.238498","url":null,"abstract":"In this paper, we discuss the SiGe technology for uncooled microbolometer arrays of small format, ie 200/spl times/1 and 14/spl times/14, is transferred from IMEC to XenICs allowing of the poly-SiGe arrays for application in non-contact temperature measurements, infrared spectroscopy, technological process monitoring, quality control, etc. The arrays demonstrate an exceptional uniformity, about 100% pixel yield, 100% operability, and a NETD of about 100 mK at a readout level. These advantages combined with a possibility of hermetic zero-level micropacking make the SiGe technology a proper one for the low-cost production of infrared arrays.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133602447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern systems become more and more complex and tendency turn to the integration on one single chip: System on Chip (SoC). A major constraint consists of "Time-to-Market". Hence, the emergence of SoC is creating many new challenges, especially, the necessity of a unified language for the system level design. SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware / software systems. This paper describes a method of stepwise refinement with SystemC, starting from an algorithmic description and progressively adding implementation details. The method is described with reference to a Turbo encoder, which is progressively moved from a purely abstract level to a more detailed description. This study is realized to emphasize on the importance of this tendency within the framework of SoC design. We also present the experimental results from specification, refinement and validation with SystemC and simulation effectiveness of the proposed method.
{"title":"SoC design case study using SystemC specifications","authors":"F. Abbes, E. Casseau, M. Abid","doi":"10.1109/ICM.2003.238563","DOIUrl":"https://doi.org/10.1109/ICM.2003.238563","url":null,"abstract":"Modern systems become more and more complex and tendency turn to the integration on one single chip: System on Chip (SoC). A major constraint consists of \"Time-to-Market\". Hence, the emergence of SoC is creating many new challenges, especially, the necessity of a unified language for the system level design. SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware / software systems. This paper describes a method of stepwise refinement with SystemC, starting from an algorithmic description and progressively adding implementation details. The method is described with reference to a Turbo encoder, which is progressively moved from a purely abstract level to a more detailed description. This study is realized to emphasize on the importance of this tendency within the framework of SoC design. We also present the experimental results from specification, refinement and validation with SystemC and simulation effectiveness of the proposed method.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new extraction method of radiation-induced oxide-trap density (/spl Delta/N/sub ot/), called OTCP (Oxide-Trap based on Charge-Pumping). In this method, we use a High Frequency (HF) standard CP measurement. We avoid the border-trap effect in CP current (I/sub cp/) measurements. Hence, I/sub cp/ is only due to the interface-trap contribution. We demonstrate that /spl Delta/N/sub ot/ is only dependent on /spl Delta/V/sub th/ (threshold voltage shift) and /spl Delta/I/sub cpm/ (augmentation of maximum CP current). We also show that /spl Delta/V/sub th/ can be obtained from lateral shift of CP Elliot curves and /spl Delta/I/sub cpm/ from vertical shift.
{"title":"New oxide-trap extraction method for irradiated MOSFET devices at high frequencies","authors":"B. Djezzar, S. Oussalah, A. Smatti","doi":"10.1109/ICM.2003.237971","DOIUrl":"https://doi.org/10.1109/ICM.2003.237971","url":null,"abstract":"This paper proposes a new extraction method of radiation-induced oxide-trap density (/spl Delta/N/sub ot/), called OTCP (Oxide-Trap based on Charge-Pumping). In this method, we use a High Frequency (HF) standard CP measurement. We avoid the border-trap effect in CP current (I/sub cp/) measurements. Hence, I/sub cp/ is only due to the interface-trap contribution. We demonstrate that /spl Delta/N/sub ot/ is only dependent on /spl Delta/V/sub th/ (threshold voltage shift) and /spl Delta/I/sub cpm/ (augmentation of maximum CP current). We also show that /spl Delta/V/sub th/ can be obtained from lateral shift of CP Elliot curves and /spl Delta/I/sub cpm/ from vertical shift.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114283993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a design for a 4Gb/s half rate 1:16 DEMUX based on 0.18 /spl mu/m CMOS technology using only static CMOS logic. A new sizing methodology is used to minimize the power consumption. The power consumption is reduced several times compared to recently published results with the delay power product also reduced by 33%.
{"title":"A 4Gb/s 1:16 DEMUX using an all-static 0.18-/spl mu/m CMOS logic","authors":"Y. Abdalla, M. Elmasry","doi":"10.1109/ICM.2003.238426","DOIUrl":"https://doi.org/10.1109/ICM.2003.238426","url":null,"abstract":"This paper introduces a design for a 4Gb/s half rate 1:16 DEMUX based on 0.18 /spl mu/m CMOS technology using only static CMOS logic. A new sizing methodology is used to minimize the power consumption. The power consumption is reduced several times compared to recently published results with the delay power product also reduced by 33%.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115795910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a novel circuit design technique for low-voltage CMOS operational transconductance amplifiers (OTA) based on CMOS square-law composite cells. This cell is used as a main building block to achieve accurate signal processing with low-power dissipation under low-voltage condition. Two pairs of this cell are connected in parallel to achieve rail-to-rail input voltage range. The transconductances of each pairs are inherently tunable by a biasing voltage. The constant-g/sub m/ characteristic is controlled by applying suitable values to these biasing voltages maintaining the smooth response over the change of input common mode voltage. HSPISE simulations show that the overall transconductance has linearity better than 6 percent with 2.5 V supply voltage.
{"title":"Low-voltage CMOS transconductance cell based on composite cells","authors":"A. Nabavi, M.A. Mansouri Birjandi, M. Jalali","doi":"10.1109/ICM.2003.238616","DOIUrl":"https://doi.org/10.1109/ICM.2003.238616","url":null,"abstract":"This paper describes a novel circuit design technique for low-voltage CMOS operational transconductance amplifiers (OTA) based on CMOS square-law composite cells. This cell is used as a main building block to achieve accurate signal processing with low-power dissipation under low-voltage condition. Two pairs of this cell are connected in parallel to achieve rail-to-rail input voltage range. The transconductances of each pairs are inherently tunable by a biasing voltage. The constant-g/sub m/ characteristic is controlled by applying suitable values to these biasing voltages maintaining the smooth response over the change of input common mode voltage. HSPISE simulations show that the overall transconductance has linearity better than 6 percent with 2.5 V supply voltage.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124099323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new semi-empirical model for the funneling-assisted currents due to single events. It is then used to predict the collected charge due to the funneling process. Comparison with previously published simulated data using ISE CAD tools has shown that the relative error in the collected charge prediction is of about 0.8%. This model can be used for circuit simulations in space applications.
{"title":"A new semi-empirical model for funneling assisted drain currents due to single events","authors":"G.B. Abadir, W. Fikry, H. Ragai, O. A. Omar","doi":"10.1109/ICM.2003.238008","DOIUrl":"https://doi.org/10.1109/ICM.2003.238008","url":null,"abstract":"We present a new semi-empirical model for the funneling-assisted currents due to single events. It is then used to predict the collected charge due to the funneling process. Comparison with previously published simulated data using ISE CAD tools has shown that the relative error in the collected charge prediction is of about 0.8%. This model can be used for circuit simulations in space applications.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124506555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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