Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401596
S. Raman, C. L. Dohrman, Tsu-Hsi Chang
The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor (CS) devices, as well as other emerging materials and devices, with high-density silicon CMOS technology. This technology is currently enabling RF/mixed signal circuits with revolutionary performance. For example, InP HBT + CMOS technology is being utilized in advanced DACs and ADCs with CMOS-enabled calibration and self-healing techniques for correcting static and dynamic errors in situ. Such CMOS-enabled self-healing techniques are expected to more generally enable improved CS-based circuit performance and yield in the presence of process and environmental variability, as well as aging. DAHI is also expected to enable the integration of high power CS devices with silicon-based linearization techniques to realize highly power efficient transmitters. By enabling this heterogeneous integration capability, DAHI seeks to establish a new paradigm for microsystems designers to utilize a diverse array of materials and device technologies on a common silicon-based platform.
{"title":"The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program: Convergence of compound semiconductor devices and silicon-enabled architectures","authors":"S. Raman, C. L. Dohrman, Tsu-Hsi Chang","doi":"10.1109/RFIT.2012.6401596","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401596","url":null,"abstract":"The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor (CS) devices, as well as other emerging materials and devices, with high-density silicon CMOS technology. This technology is currently enabling RF/mixed signal circuits with revolutionary performance. For example, InP HBT + CMOS technology is being utilized in advanced DACs and ADCs with CMOS-enabled calibration and self-healing techniques for correcting static and dynamic errors in situ. Such CMOS-enabled self-healing techniques are expected to more generally enable improved CS-based circuit performance and yield in the presence of process and environmental variability, as well as aging. DAHI is also expected to enable the integration of high power CS devices with silicon-based linearization techniques to realize highly power efficient transmitters. By enabling this heterogeneous integration capability, DAHI seeks to establish a new paradigm for microsystems designers to utilize a diverse array of materials and device technologies on a common silicon-based platform.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131496311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401667
C. Boon, M. Krishna, M. Do, K. Yeo, A. Do, T. S. Wong
This paper presents a low power 1.2 V, 2.4 GHz low spur, Quadrature PLL synthesizer for IEEE 802.15.4 batteryless transceiver in CMOS 0.18 μm technology. The PLL employs a 1 MHz fully programmable divider with an improved CML 2/3 prescaler, a novel bit-cell for the programmable counters and a novel charge pump with gain-boosted technique to reduce the PLL reference spurs. The PLL consumes a power of 1.85 mW at 1.2 V power supply with the programmable divider consuming only 350 μW. The phase noise of the PLL is -112.77 dBc/Hz at 1 MHz offset and the spurs are -46.2 dB below the carrier and the PLL is successfully tested with the energy harvesting circuit.
{"title":"A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver","authors":"C. Boon, M. Krishna, M. Do, K. Yeo, A. Do, T. S. Wong","doi":"10.1109/RFIT.2012.6401667","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401667","url":null,"abstract":"This paper presents a low power 1.2 V, 2.4 GHz low spur, Quadrature PLL synthesizer for IEEE 802.15.4 batteryless transceiver in CMOS 0.18 μm technology. The PLL employs a 1 MHz fully programmable divider with an improved CML 2/3 prescaler, a novel bit-cell for the programmable counters and a novel charge pump with gain-boosted technique to reduce the PLL reference spurs. The PLL consumes a power of 1.85 mW at 1.2 V power supply with the programmable divider consuming only 350 μW. The phase noise of the PLL is -112.77 dBc/Hz at 1 MHz offset and the spurs are -46.2 dB below the carrier and the PLL is successfully tested with the energy harvesting circuit.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132652215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401601
Zhenghao Lu, C. Feng, Xiaopeng Yu, Yajie Qin, K. Yeo
This paper presents the design of a low-power millimeter wave receiver for Gbps short range wireless communications in the 60GHz frequency range. The scope of this paper covers the system design of the OOK direct conversion receiver, the design of a novel 60GHz low-noise amplifier, the co-design of the mixer with the IF amplifier and the design of a IF variable gain amplifier. The full receiver is realized in Global Foundry 65nm CMOS technology. The extracted simulation results show that the receiver is able to work from 50GHz-70GHz with a data rate higher than 1Gbps while consuming a current of about 25mA from a standard 1.2V supply voltage at maximum gain.
{"title":"Design of a low power 60GHz OOK receiver in 65nm CMOS technology","authors":"Zhenghao Lu, C. Feng, Xiaopeng Yu, Yajie Qin, K. Yeo","doi":"10.1109/RFIT.2012.6401601","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401601","url":null,"abstract":"This paper presents the design of a low-power millimeter wave receiver for Gbps short range wireless communications in the 60GHz frequency range. The scope of this paper covers the system design of the OOK direct conversion receiver, the design of a novel 60GHz low-noise amplifier, the co-design of the mixer with the IF amplifier and the design of a IF variable gain amplifier. The full receiver is realized in Global Foundry 65nm CMOS technology. The extracted simulation results show that the receiver is able to work from 50GHz-70GHz with a data rate higher than 1Gbps while consuming a current of about 25mA from a standard 1.2V supply voltage at maximum gain.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"12 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131836875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401604
C. Kok, L. Siek, W. M. Lim
This article presents an ultra-fast 65nm LDO regulator dedicated for sensory detection using a direct feedback dual self reacting loop technique. This novel technique enabled the regulator to achieve a very fast response time of 0.10μs for a maximum load current transition from 1 to 50mA. Furthermore, it achieves a very low quiescent current of 5.0μA coupled with a low power consumption of 5.0μW. This LDO regulator, simulated with Global Foundries 65nm CMOS process, yields a stable output voltage of 0.8V with a supply voltage ranging from 1-1.4V. Its distinct features, ultra-fast response time and very low power consumption, make it ideally suitable for sensory detection.
{"title":"An ultra-fast 65nm capacitorless LDO regulator dedicated for sensory detection using a direct feedback dual self-reacting loop technique","authors":"C. Kok, L. Siek, W. M. Lim","doi":"10.1109/RFIT.2012.6401604","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401604","url":null,"abstract":"This article presents an ultra-fast 65nm LDO regulator dedicated for sensory detection using a direct feedback dual self reacting loop technique. This novel technique enabled the regulator to achieve a very fast response time of 0.10μs for a maximum load current transition from 1 to 50mA. Furthermore, it achieves a very low quiescent current of 5.0μA coupled with a low power consumption of 5.0μW. This LDO regulator, simulated with Global Foundries 65nm CMOS process, yields a stable output voltage of 0.8V with a supply voltage ranging from 1-1.4V. Its distinct features, ultra-fast response time and very low power consumption, make it ideally suitable for sensory detection.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114800002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper designed an automatic gain control(AGC) amplifier for CMOS Image Sensor. The AGC amplifier adopts translinear variable gain amplifier (VGA) to realize a good linearity. It detects valley to present the strength of signal, and uses a succinct adjustment circuit to control the gain of VGA. A bandgap reference not needing start-up circuit was designed for the whole system. Simulated in SMIC 0.35um CMOS, it can compressed the dynamic range of 100kHz signal from 55.32dB to 7.36dB.
{"title":"Design of AGC amplifier for CMOS Image Sensor","authors":"Guoyi Yu, Xuecheng Zou, Le Zhang, Qiming Zou, Meijun Zheng, Jianfu Zhong","doi":"10.1109/RFIT.2012.6401605","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401605","url":null,"abstract":"This paper designed an automatic gain control(AGC) amplifier for CMOS Image Sensor. The AGC amplifier adopts translinear variable gain amplifier (VGA) to realize a good linearity. It detects valley to present the strength of signal, and uses a succinct adjustment circuit to control the gain of VGA. A bandgap reference not needing start-up circuit was designed for the whole system. Simulated in SMIC 0.35um CMOS, it can compressed the dynamic range of 100kHz signal from 55.32dB to 7.36dB.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122037460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401637
Chaojun Ye, Chun Zhang, Hong Chen, Zhihua Wang
This paper presents a smart UHF near-field RFID system with contactless inductively coupled antenna. A fully integrated inductively coupled antenna is designed to solve the problem of short read distance of the On-chip Antenna (OCA) tag. The inductively coupled antenna used a novel cross structure to achieve resonant effect which also diminishes the size of the antenna. No physical connection between the antenna and the tag chip greatly reduces the cost of assembling and testing. The size of the inductively coupled antenna is only 1 × 1.1cm2 small. Test proved that the tag chip with this contactless antenna is responded properly at 2cm away from the reader antenna of 20dBm.
{"title":"A UHF near-field RFID system with contactless inductively coupled antenna","authors":"Chaojun Ye, Chun Zhang, Hong Chen, Zhihua Wang","doi":"10.1109/RFIT.2012.6401637","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401637","url":null,"abstract":"This paper presents a smart UHF near-field RFID system with contactless inductively coupled antenna. A fully integrated inductively coupled antenna is designed to solve the problem of short read distance of the On-chip Antenna (OCA) tag. The inductively coupled antenna used a novel cross structure to achieve resonant effect which also diminishes the size of the antenna. No physical connection between the antenna and the tag chip greatly reduces the cost of assembling and testing. The size of the inductively coupled antenna is only 1 × 1.1cm2 small. Test proved that the tag chip with this contactless antenna is responded properly at 2cm away from the reader antenna of 20dBm.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122796470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401599
Chih-Chen Chang, Yen-Chung Chiang
In this paper, a two-stage low-noise amplifier (LNA) designed for V-band applications is presented. Both stages are the common source-common gate (CS-CG) cascoded topologies with inductive degeneration structure for minimizing the noise figure (NF). This proposed LNA is implemented in a GaAs 0.15μm pHEMT process technology, which achieves a peak gain of 12.1 dB, a NF of 5.456 dB, and an input P1dB of -20 dBm at the 56.8 GHz frequency. The 3dB bandwidth is from 54.9 GHz to 58 GHz. The power consumption of the proposed LNA is 26.6 mW from the 1.8V voltage supply.
{"title":"Low-noise amplifier with 12.1 dB gain and 5.456 dB NF for V-band applications in GaAs 0.15μm pHEMT process","authors":"Chih-Chen Chang, Yen-Chung Chiang","doi":"10.1109/RFIT.2012.6401599","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401599","url":null,"abstract":"In this paper, a two-stage low-noise amplifier (LNA) designed for V-band applications is presented. Both stages are the common source-common gate (CS-CG) cascoded topologies with inductive degeneration structure for minimizing the noise figure (NF). This proposed LNA is implemented in a GaAs 0.15μm pHEMT process technology, which achieves a peak gain of 12.1 dB, a NF of 5.456 dB, and an input P1dB of -20 dBm at the 56.8 GHz frequency. The 3dB bandwidth is from 54.9 GHz to 58 GHz. The power consumption of the proposed LNA is 26.6 mW from the 1.8V voltage supply.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115974122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper designed a low-noise high-gain tran simpedance amplifier with high dynamic range. The input stage of TIA uses an individual power supply to accommodate the level of the photodiode(PD). Then the signal is transmitted to the subsequent circuit by a level shifting circuit. The TIA adopts DCrestore to stabilize work points, and uses a MOS working in the linear region to reduce the effective input signal to realize high dynamic range. Key noise components are optimized to reduce the input referred current noise. This TIA was validated in 0.13 urn CMOS. The simulation results show the -3dB bandwidth is 1.8GHz, the maximum gain is 82.27dB Ω, the input referred noise is 125nA, and the measure current ranges 5uA ~2mA.
{"title":"A low-noise high-gain transimpedance amplifier with high dynamic range in 0.13ìm CMOS","authors":"Guoyi Yu, Xuecheng Zou, Le Zhang, Qiming Zou, Meijun Zheng, Jianfu Zhong","doi":"10.1109/RFIT.2012.6401606","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401606","url":null,"abstract":"This paper designed a low-noise high-gain tran simpedance amplifier with high dynamic range. The input stage of TIA uses an individual power supply to accommodate the level of the photodiode(PD). Then the signal is transmitted to the subsequent circuit by a level shifting circuit. The TIA adopts DCrestore to stabilize work points, and uses a MOS working in the linear region to reduce the effective input signal to realize high dynamic range. Key noise components are optimized to reduce the input referred current noise. This TIA was validated in 0.13 urn CMOS. The simulation results show the -3dB bandwidth is 1.8GHz, the maximum gain is 82.27dB Ω, the input referred noise is 125nA, and the measure current ranges 5uA ~2mA.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133550586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401634
R. Jegadeesan, Yong-xin Guo, Rui-Feng Xue, M. Je
An efficient resonant tuned wireless power transfer (WPT) link using inductive coupling has been proposed for the neural implant application in this work. The power link is optimized for an operating frequency of 10 MHz using coil, load and frequency optimization. The lossy tissue model was used to mimic the power loss in tissue and the simulated (HFSS) peak SAR values were within the allowed limit for 20 mW power received at implant. The power transfer efficiency for implant coil sizes of 250 mm2 for a power transmit range of 10 mm was simulated using HFSS to be around 82%.
{"title":"An efficient wireless power link for neural implant","authors":"R. Jegadeesan, Yong-xin Guo, Rui-Feng Xue, M. Je","doi":"10.1109/RFIT.2012.6401634","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401634","url":null,"abstract":"An efficient resonant tuned wireless power transfer (WPT) link using inductive coupling has been proposed for the neural implant application in this work. The power link is optimized for an operating frequency of 10 MHz using coil, load and frequency optimization. The lossy tissue model was used to mimic the power loss in tissue and the simulated (HFSS) peak SAR values were within the allowed limit for 20 mW power received at implant. The power transfer efficiency for implant coil sizes of 250 mm2 for a power transmit range of 10 mm was simulated using HFSS to be around 82%.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132824191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401660
A. Patel, Y. Kosta, N. Chhasatia
A new Nonplanar Left-handed propagating medium consisting of asymmetrically placed obstacles coupled into waveguide resonator that produce a negative dielectric permittivity is presented. The necessary negative magnetic permeability is achieved by introducing capacitive gap along the two post conductor perpendicular to each other inside the waveguide. Its properties are derived from its geometrical constitution and matter used. Its narrowband bandwidth and high Q-factor characteristics are achieving by Introducing posts inside waveguide in our proposed structure, it will generates desired resonance at X band, Ku band and Ka band Frequencies are reported. Simulations results demonstrate the realization of DNGMs matched to free-space as well as having superior insertion loss and better return loss compare to traditional one and having high power handling capacity. This post coupled waveguide resonator (PCWR) characteristic can be widely varied by changing the geometrical structure and conductive properties of the inserted posts. Structure is simulated with Ansoft's finite-element High Frequency Structure Simulator (HFFS) tool to demonstrate the characteristics of this resonator using a rectangular waveguide with center frequency at 11.2GHz.
{"title":"Microwave waveguide resonator based double negative metamaterial","authors":"A. Patel, Y. Kosta, N. Chhasatia","doi":"10.1109/RFIT.2012.6401660","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401660","url":null,"abstract":"A new Nonplanar Left-handed propagating medium consisting of asymmetrically placed obstacles coupled into waveguide resonator that produce a negative dielectric permittivity is presented. The necessary negative magnetic permeability is achieved by introducing capacitive gap along the two post conductor perpendicular to each other inside the waveguide. Its properties are derived from its geometrical constitution and matter used. Its narrowband bandwidth and high Q-factor characteristics are achieving by Introducing posts inside waveguide in our proposed structure, it will generates desired resonance at X band, Ku band and Ka band Frequencies are reported. Simulations results demonstrate the realization of DNGMs matched to free-space as well as having superior insertion loss and better return loss compare to traditional one and having high power handling capacity. This post coupled waveguide resonator (PCWR) characteristic can be widely varied by changing the geometrical structure and conductive properties of the inserted posts. Structure is simulated with Ansoft's finite-element High Frequency Structure Simulator (HFFS) tool to demonstrate the characteristics of this resonator using a rectangular waveguide with center frequency at 11.2GHz.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"31 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113963458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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