Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401621
S. Saisundar, J. Cheong, M. Je
This paper presents a 10-bit, 1MS/s, rail-to-rail successive approximation register analog-to-digital converter (SAR ADC). The ADC uses a bootstrapped sampling switch to achieve better linearity and also adopts a generalized non-binary redundant algorithm and a rail-to-rail dynamic latched comparator to obtain higher Effective Number of Bits (ENOB). This ADC designed and fabricated in 0.18μm CMOS process achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.9dB at 1MS/s which corresponds to an ENOB of 9.5. It also obtains a good linearity (DNL/INL) value of less than ±0.46LSB. At 1.8V supply, the ADC attains a Figure of Merit (FOM) of 181fJ/conversion-step. The ADC also consumes 34.6μW from a 1.2V supply with an ENOB of 8.7 resulting in a FOM of 83fJ/conversion-step.
{"title":"A 1.8V 1MS/s rail-to-rail 10-bit SAR ADC in 0.18μm CMOS","authors":"S. Saisundar, J. Cheong, M. Je","doi":"10.1109/RFIT.2012.6401621","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401621","url":null,"abstract":"This paper presents a 10-bit, 1MS/s, rail-to-rail successive approximation register analog-to-digital converter (SAR ADC). The ADC uses a bootstrapped sampling switch to achieve better linearity and also adopts a generalized non-binary redundant algorithm and a rail-to-rail dynamic latched comparator to obtain higher Effective Number of Bits (ENOB). This ADC designed and fabricated in 0.18μm CMOS process achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.9dB at 1MS/s which corresponds to an ENOB of 9.5. It also obtains a good linearity (DNL/INL) value of less than ±0.46LSB. At 1.8V supply, the ADC attains a Figure of Merit (FOM) of 181fJ/conversion-step. The ADC also consumes 34.6μW from a 1.2V supply with an ENOB of 8.7 resulting in a FOM of 83fJ/conversion-step.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130715636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401671
Bumman Kim, Dongsu Kim, Yungsung Cho, Jooseung Kim
Envelope tracking technique is suitable to the transmitters for mobile handset and becomes a hot research item in recent years. In this paper, we will overview the research trends in this area. The supply modulator handles the modulated signal and the PA works only for RF amplification. Because of the separated functions, the architecture is a favored structure for multimode/multiband operation. The supply modulator is an ideal power management IC for a PA. This technique is perused to improve the efficiency at a high power level as well as at a low power level. Because of the enhanced efficiency at a low power level, the transmitter can provide good performance at a low/high mode PA for handset. These new developments of the ET technology will be introduced.
{"title":"Envelope tracking technique for mobile handset application (Inviter Paper)","authors":"Bumman Kim, Dongsu Kim, Yungsung Cho, Jooseung Kim","doi":"10.1109/RFIT.2012.6401671","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401671","url":null,"abstract":"Envelope tracking technique is suitable to the transmitters for mobile handset and becomes a hot research item in recent years. In this paper, we will overview the research trends in this area. The supply modulator handles the modulated signal and the PA works only for RF amplification. Because of the separated functions, the architecture is a favored structure for multimode/multiband operation. The supply modulator is an ideal power management IC for a PA. This technique is perused to improve the efficiency at a high power level as well as at a low power level. Because of the enhanced efficiency at a low power level, the transmitter can provide good performance at a low/high mode PA for handset. These new developments of the ET technology will be introduced.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128739779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401640
Xiaofei Pu, Lei Wan, Yun Sheng, P. Chiang, Yajie Qin, Zhiliang Hong
A wireless 8-channel biopotential acquisition system for capturing electrocardiogram (ECG) using dry electrodes is presented. The ECG system consists of copper electrodes, a micropowered 8-channel custom ASIC, and an off-the-shelf microprocessor and bluetooth radio. Each analog channel of the custom ECG front-end is composed of a chopper-modulated instrumentation amplifier (CMIA) with chopping spike filter (CSF), a programmable gain amplifier (PGA), and a output buffer. Implemented in standard a 0.35 μm CMOS technology, the ECG front-end consumes 101 μA from a 2.7 V supply, occupying 5 mm2 of chip area. Measurement results show an input impedance of 1 G Ω, an input-referred noise of 0.97 μVrms (0.5 ~ 100 Hz), and a CMRR of 114 dB. Finally, a complete wireless 8-channel ECG monitoring system incorporating this analog front-end is demonstrated, showing successful recordings of a capture ECG waveform using a smart phone.
{"title":"A wireless 8-channel ECG biopotential acquisition system for dry electrodes","authors":"Xiaofei Pu, Lei Wan, Yun Sheng, P. Chiang, Yajie Qin, Zhiliang Hong","doi":"10.1109/RFIT.2012.6401640","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401640","url":null,"abstract":"A wireless 8-channel biopotential acquisition system for capturing electrocardiogram (ECG) using dry electrodes is presented. The ECG system consists of copper electrodes, a micropowered 8-channel custom ASIC, and an off-the-shelf microprocessor and bluetooth radio. Each analog channel of the custom ECG front-end is composed of a chopper-modulated instrumentation amplifier (CMIA) with chopping spike filter (CSF), a programmable gain amplifier (PGA), and a output buffer. Implemented in standard a 0.35 μm CMOS technology, the ECG front-end consumes 101 μA from a 2.7 V supply, occupying 5 mm2 of chip area. Measurement results show an input impedance of 1 G Ω, an input-referred noise of 0.97 μVrms (0.5 ~ 100 Hz), and a CMRR of 114 dB. Finally, a complete wireless 8-channel ECG monitoring system incorporating this analog front-end is demonstrated, showing successful recordings of a capture ECG waveform using a smart phone.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401654
S. Khandelwal, F. M. Yigletu, B. Iñíguez, T. Fjeldly
We present an analytical calculation for the surface-potential and a surface-potential-based drain current model in AlGaAs/GaAs HEMT devices. We have developed a precise analytical calculation for the position of the Fermi level Ef in these devices from a consistent solution of Schrödinger's and Poisson's equations. The accuracy of our calculation is of the order of pico-volts. Ef is used to define the surface-potential ψ and subsequently derive the drain current Id. Real device effects like mobility degradation, velocity-saturation, channel-length modulation and self-heating are included in the model. The model is in excellent agreement with experimental data.
{"title":"Analytical modeling of surface-potential and drain current in AlGaAs/GaAs HEMT devices","authors":"S. Khandelwal, F. M. Yigletu, B. Iñíguez, T. Fjeldly","doi":"10.1109/RFIT.2012.6401654","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401654","url":null,"abstract":"We present an analytical calculation for the surface-potential and a surface-potential-based drain current model in AlGaAs/GaAs HEMT devices. We have developed a precise analytical calculation for the position of the Fermi level Ef in these devices from a consistent solution of Schrödinger's and Poisson's equations. The accuracy of our calculation is of the order of pico-volts. Ef is used to define the surface-potential ψ and subsequently derive the drain current Id. Real device effects like mobility degradation, velocity-saturation, channel-length modulation and self-heating are included in the model. The model is in excellent agreement with experimental data.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123939516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401602
Yuan Bing, Lai Xin-quan, Shi Lingfeng
A switch size control circuit for hybrid mode DC-DC buck converter is presented. Detecting the output of error amplifier by a comparator, the circuit can select appropriate switch size according to load current for high efficiency. The threshold level of the comparator varies with respect to the amount of slope compensation, which maintains a substantially constant switch size changing point. A monolithic DC-DC buck converter with 5A load current using the proposed circuit has been fabricated with a 0.5μm CMOS process for validation. The switch size is 1/4 of the maximum value when load current is below 1A with 500mA hysteresis. The measured efficiency is up to 96%.
{"title":"Novel switch size control circuit in high efficiency hybrid mode DC-DC buck converter","authors":"Yuan Bing, Lai Xin-quan, Shi Lingfeng","doi":"10.1109/RFIT.2012.6401602","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401602","url":null,"abstract":"A switch size control circuit for hybrid mode DC-DC buck converter is presented. Detecting the output of error amplifier by a comparator, the circuit can select appropriate switch size according to load current for high efficiency. The threshold level of the comparator varies with respect to the amount of slope compensation, which maintains a substantially constant switch size changing point. A monolithic DC-DC buck converter with 5A load current using the proposed circuit has been fabricated with a 0.5μm CMOS process for validation. The switch size is 1/4 of the maximum value when load current is below 1A with 500mA hysteresis. The measured efficiency is up to 96%.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116647269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401633
A. Huynh, B. Sedighi, H. T. Duong, H. V. Le, E. Skafidas
This paper presents a high-speed clocked regenerative comparator designed in 65-nm CMOS process. The kickback noise caused by large variations at the regeneration nodes is suppressed using an intermediate stage. An extra switch is added between regeneration nodes to further equate their voltages when the comparator is at reset phase. The measured results show that the proposed comparator is able to achieve a Bit Error Rate (BER) of 2 × 10-9 at a sensitivity of 12 mV at 1.4 GHz and 30 mV at 3 GHz. The power consumption of the proposed comparator is 75 μW at 500 MHz and 400 μW at 3 GHz.
{"title":"A 400-μW 3-GHz comparator in 65-nm CMOS","authors":"A. Huynh, B. Sedighi, H. T. Duong, H. V. Le, E. Skafidas","doi":"10.1109/RFIT.2012.6401633","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401633","url":null,"abstract":"This paper presents a high-speed clocked regenerative comparator designed in 65-nm CMOS process. The kickback noise caused by large variations at the regeneration nodes is suppressed using an intermediate stage. An extra switch is added between regeneration nodes to further equate their voltages when the comparator is at reset phase. The measured results show that the proposed comparator is able to achieve a Bit Error Rate (BER) of 2 × 10-9 at a sensitivity of 12 mV at 1.4 GHz and 30 mV at 3 GHz. The power consumption of the proposed comparator is 75 μW at 500 MHz and 400 μW at 3 GHz.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116946490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fully integrated 5-GHz PLL frequency synthesizer for WSN applications has been designed and implemented in 0.18μm CMOS technology. With automatic current calibration technique (ACC), the VCO could maintain a good performance under a small current consumption of about 0.3mA. Phase switching technique is used in the frequency divider to reduce power consumption. Using a 1.8V supply voltage, the measured power consumption is 12mW and the phase noise is -111.13dBc/Hz at 1MHz offset.
采用0.18μm CMOS技术设计并实现了用于WSN应用的全集成5 ghz锁相环频率合成器。采用自动电流校准技术(automatic current calibration technology, ACC)， VCO在0.3mA的小电流消耗下仍能保持良好的工作性能。分频器采用相开关技术来降低功耗。在1.8V电源电压下，测量功耗为12mW，相位噪声为-111.13dBc/Hz。
{"title":"Design of a low power 5-GHz frequency synthesizer for WSN applications","authors":"Zhiqun Li, Q. Cao, Xiaodong Qi, Shuangshuang Zheng","doi":"10.1109/RFIT.2012.6401669","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401669","url":null,"abstract":"A fully integrated 5-GHz PLL frequency synthesizer for WSN applications has been designed and implemented in 0.18μm CMOS technology. With automatic current calibration technique (ACC), the VCO could maintain a good performance under a small current consumption of about 0.3mA. Phase switching technique is used in the frequency divider to reduce power consumption. Using a 1.8V supply voltage, the measured power consumption is 12mW and the phase noise is -111.13dBc/Hz at 1MHz offset.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123235849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401659
Yutong Ying, Lu Huang, Li Cai, F. Lin
A 4.06-4.89 GHz, low phase noise symmetric complementary voltage controlled oscillator (VCO), which features an optimized capacitive feedback technique combined with RC source degeneration, is presented in this paper. Fabricated in 180nm CMOS technology, the proposed VCO obtained a measured corner frequency of 15-80 KHz. The measured phase noise at 1MHz offset from the 4.89GHz carrier is -119dBc/Hz. Occupying 0.15mm2 in 180nm CMOS technology under 2.5mW power consumption, an area-normalized figure-of-merit (FOMA) of 197.1dBc/Hz has been achieved.
{"title":"A 4.89-GHz low-phase-noise VCO in CMOS technology","authors":"Yutong Ying, Lu Huang, Li Cai, F. Lin","doi":"10.1109/RFIT.2012.6401659","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401659","url":null,"abstract":"A 4.06-4.89 GHz, low phase noise symmetric complementary voltage controlled oscillator (VCO), which features an optimized capacitive feedback technique combined with RC source degeneration, is presented in this paper. Fabricated in 180nm CMOS technology, the proposed VCO obtained a measured corner frequency of 15-80 KHz. The measured phase noise at 1MHz offset from the 4.89GHz carrier is -119dBc/Hz. Occupying 0.15mm2 in 180nm CMOS technology under 2.5mW power consumption, an area-normalized figure-of-merit (FOMA) of 197.1dBc/Hz has been achieved.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123689443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401612
G. Chaudhary, P. Kim, Y. Jeong, Jongsik Lim
This paper presents a compact dual-mode tunable bandpass filter (BPF) with independently tunable center frequencies and bandwidths based on varactor loaded transmission line dual-mode resonator. The center frequency can be controlled by tuning the even-mode and odd-mode resonant frequencies of the dual-mode resonator. The bandwidth of passband can be tuned by fixing the odd-mode and changing the even-mode resonant frequency. To validate the proposed structure, two-pole microstrip tunable BPF is presented and experimentally verified.
{"title":"Dual-mode bandpass filter with independently tunable center frequency and bandwidth","authors":"G. Chaudhary, P. Kim, Y. Jeong, Jongsik Lim","doi":"10.1109/RFIT.2012.6401612","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401612","url":null,"abstract":"This paper presents a compact dual-mode tunable bandpass filter (BPF) with independently tunable center frequencies and bandwidths based on varactor loaded transmission line dual-mode resonator. The center frequency can be controlled by tuning the even-mode and odd-mode resonant frequencies of the dual-mode resonator. The bandwidth of passband can be tuned by fixing the odd-mode and changing the even-mode resonant frequency. To validate the proposed structure, two-pole microstrip tunable BPF is presented and experimentally verified.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124855292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401613
Junhyung Jeong, Sungdoo Park, G. Chaudhary, Y. Jeong
In this paper, a design of tunable microstrip transmission line negative group delay circuit (NGDC) using p-i-n diodes is proposed. The design was based on reflective parallel R-L-C circuit and group delay (GD) can be varied with help of variable resistance. To get the variable resistance, the transmission line (TL) terminated with p-i-n diode is used. The GD is varied with help of bias voltages of p-i-n diodes. Both design equations and design procedures are presented. The measured GD time variation range is 0 ~ -20 ns and well agreed with simulation results.
{"title":"Design of tunable negative group delay circuit for communication systems","authors":"Junhyung Jeong, Sungdoo Park, G. Chaudhary, Y. Jeong","doi":"10.1109/RFIT.2012.6401613","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401613","url":null,"abstract":"In this paper, a design of tunable microstrip transmission line negative group delay circuit (NGDC) using p-i-n diodes is proposed. The design was based on reflective parallel R-L-C circuit and group delay (GD) can be varied with help of variable resistance. To get the variable resistance, the transmission line (TL) terminated with p-i-n diode is used. The GD is varied with help of bias voltages of p-i-n diodes. Both design equations and design procedures are presented. The measured GD time variation range is 0 ~ -20 ns and well agreed with simulation results.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123667185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：