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2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)最新文献

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Shape enhancement and size reduction of UWB printed monopole antenna 超宽带印刷单极天线的形状增强和尺寸减小
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401665
A. Munir, F. Oktafiani, A. Izzuddin
An ultra wideband (UWB) antenna in enhanced shape and reduced size is proposed for investigation and characterization. The proposed antenna which is intended for surface penetrating radar (SPR) application requiring a narrow period pulse is a monopole type antenna and printed on a dielectric substrate. Based on parametrical studies, the octahedral shape is chosen as it is able to enhance the performance as well as to reduce the size of antenna. The antenna is constructed based on a rectangular microstrip antenna fed by a symmetric T-shaped. Some attempts to investigate and characterize the physical parameter including octahedral patch resizing, transition angle, length of arm, and resistive loading are conducted to achieve the required characteristics and the compactness. From the investigation and characterization results, it shows that the proposed antenna which is deployed on FR-4 Epoxy substrate (relative permittivity of 4.3 and thickness of 1.6mm) with a 50Ω microstrip line feeding technique has the overall size of 50mm × 50mm and satisfies with the operating bandwidth required by the application, i.e. frequency range of 50-5000MHz.
提出了一种增强形状和减小尺寸的超宽带(UWB)天线,用于研究和表征。所提出的用于需要窄周期脉冲的表面穿透雷达(SPR)应用的天线是印刷在介电衬底上的单极型天线。在参数化研究的基础上,选择八面体结构既能提高天线的性能,又能减小天线的尺寸。该天线是基于对称t形馈电的矩形微带天线结构。对八面体贴片调整尺寸、过渡角、臂长、电阻加载等物理参数进行了研究和表征,以达到所需的特性和致密性。研究和表征结果表明,采用50Ω微带馈线技术部署在FR-4环氧基板(相对介电常数为4.3,厚度为1.6mm)上的天线总体尺寸为50mm × 50mm,满足应用所需的工作带宽,即频率范围为50-5000MHz。
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引用次数: 11
SiP-based 60GHz transmitter in LTCC LTCC中基于sip的60GHz发射机
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401598
M. K. Karim, M. Sun, L. Ong, Y. X. Guo, F. Lin, B. Luo
A 60GHz 4×4 circular polarized (CP) patch array antenna with a 90nm CMOS OOK modulator are integrated in low temperature co-fired ceramic (LTCC) substrate to form a SiP transmitter. The CP array shows a 3dB axial ratio (AR) bandwidth of over 8GHz. It has a 3dB beamwidth of 20° and a peak gain of 16.8dBi. Device modeling at 60GHz is done to accurately simulate the lumped components. The CMOS modulator includes a 60GHz oscillator and switchable amplifiers to provide the OOK modulation. The final fabricated 60GHz SiP transmitter prototype measures only 22×13×1.4mm3.
将60GHz 4×4圆极化(CP)贴片阵列天线与90nm CMOS OOK调制器集成在低温共烧陶瓷(LTCC)衬底中形成SiP发射机。CP阵列显示出超过8GHz的3dB轴比(AR)带宽。它具有20°的3dB波束宽度和16.8dBi的峰值增益。在60GHz下进行器件建模,以准确模拟集总元件。CMOS调制器包括一个60GHz振荡器和可切换放大器,以提供OOK调制。最终制造的60GHz SiP发射机原型测量只有22×13×1.4mm3。
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引用次数: 1
A polymorphic 15GHz/mW inductorless frequency prescaler using implication logic in 0.13μm CMOS 一种在0.13μm CMOS中使用隐含逻辑的多态15GHz/mW无电感频率预分频器
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401617
E. Roa, Wu-Hsin Chen, B. Jung
This paper describes a power-efficient frequency prescaler operating at maximum frequency of 12.3GHz without using inductors. A novel logic concept and reconfigurable technique is presented to achieve two division factors by using just one single-phase clock flip-flop. The prescaler is implemented in 0.13μm CMOS technology. It occupies 14×12μm2 and consumes 817μW at maximum frequency. Experimental results indicate a power efficient and compact frequency divider working in wide frequency range from 5GHz to 12.3GHz.
本文介绍了一种不使用电感,工作在12.3GHz最高频率的节能型频率预分频器。提出了一种新颖的逻辑概念和可重构技术,利用一个单相时钟触发器实现两个除法因子。该预缩放器采用0.13μm CMOS技术。占用14×12μm2,最大频率消耗817μW。实验结果表明,该分频器工作在5GHz ~ 12.3GHz的宽频率范围内,功耗低,结构紧凑。
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引用次数: 2
Optimization of injection locked frequency divider with tunable active inductor 可调谐有源电感注入锁定分频器的优化设计
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401618
Jian Kang, Xiaopeng Yu, Jianjun J. Zhou
This paper presents an optimized injection locked frequency divider (ILFD) with multiple division ratios. The divider core is composed of a tunable active inductor (TAI) and cross-coupled transistors. Different tuning voltages are applied to control the impedance of this TAI hence to achieve multi-division ratios of 2, 3, 4 and 5. Key considerations such as operating frequency, locking range, power consumption and input sensitivity of this ILFD are analyzed in detail, based on which an optimized ILFD is designed and fabricated in TSMC 65nm CMOS technology. Measurement results show the proposed design exhibits a high figure of merit.
提出了一种优化的多分频比注入锁定分频器。分压器核心由可调谐有源电感(TAI)和交叉耦合晶体管组成。应用不同的调谐电压来控制该TAI的阻抗,从而实现2、3、4和5的多分比。详细分析了该ILFD的工作频率、锁定范围、功耗和输入灵敏度等关键考虑因素,并在此基础上采用台积电65nm CMOS工艺设计和制作了优化后的ILFD。测量结果表明,所提出的设计具有很高的性能。
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引用次数: 1
Compact true time delay line with partially shielded coplanar waveguide transmission lines 紧凑的真时间延迟线与部分屏蔽共面波导传输线
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401614
H. Lim, G. Ng, Y. Leong
This paper presents a method to attain a compact true time delay line with a partially shielded coplanar waveguide transmission line. Closely spaced air bridges were utilized to reduce the coupling effects between neighboring coplanar waveguide transmission lines. The proposed method is compatible with foundry's GaAs standard process and allows the transmission line to be compact and achieve a small sized true time delay line circuit. A true time delay line of approximately 85ps was fabricated and tested.
本文提出了一种用部分屏蔽共面波导传输线实现紧凑真时间延迟线的方法。采用紧密间隔的空气桥来减小相邻共面波导传输线之间的耦合效应。该方法与铸造厂的GaAs标准工艺兼容,使传输线紧凑,实现了小尺寸的真延时线路电路。制作并测试了约85ps的延时线。
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引用次数: 6
A V-band power amplifier with 11.9 dB gain in CMOS 90-nm process technology 基于CMOS 90纳米工艺的增益11.9 dB的v波段功率放大器
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401600
M. Wu, Yen-Chung Chiang
In this paper, a three-stage power amplifier (PA) designed for V-band applications is presented. The proposed PA adopts common-source topology for each stage and is implemented in the CMOS 90-nm process technology. This V-band PA achieves a small signal gain of 11.9dB and a saturated output power of 7.6dBm at the 60GHz operating frequency. The measured peak power added efficiency (PAE) is 4.77%, and its OP1dB is 5dBm. The power consumption of the proposed PA is 97mW from the 1.2V voltage supply.
本文介绍了一种专为v波段应用而设计的三级功率放大器。所提出的PA各级采用共源拓扑,采用CMOS 90纳米制程技术实现。该v波段扩音器在60GHz工作频率下实现了11.9dB的小信号增益和7.6dBm的饱和输出功率。测量的峰值功率附加效率(PAE)为4.77%,其OP1dB为5dBm。在1.2V电压下,所提出的PA的功耗为97mW。
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引用次数: 1
Investigation of the mutual effect between power link and data link for biomedicai applications 生物医学应用中电源链路与数据链路相互作用的研究
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401666
Z. Duan, Yong-xin Guo, Rui-Feng Xue, M. Je, D. Kwong
For implantable applications, the wireless communication link between implanted devices and external apparatus are often realized by separate links, the power link and the data link. Due to the possible close distance between the power link and the data link, the performance of each will be affected. This study aims to investigate the interference between power link and data link immersed in human tissue.
对于植入式应用,植入式设备与外部设备之间的无线通信链路通常通过单独的链路,电源链路和数据链路来实现。由于电源链路和数据链路之间可能距离较近,因此会影响各自的性能。本研究旨在探讨人体组织中电力链路与数据链路之间的干扰。
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引用次数: 0
A 5-GHz fully integrated CMOS class-E power amplifier using self-biasing technique with cascaded class-D drivers 采用级联d类驱动器的自偏置技术的5 ghz全集成CMOS e类功率放大器
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401672
Yuki Yamashita, D. Kanemoto, H. Kanaya, Ramesh K. Pokharel, K. Yoshida
This paper describes the design of 5-GHz fully integrated CMOS class-E single-ended power amplifier (PA) for wireless transmitter applications in a 0.18-μm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3 mm2. The measurement results indicate that the PA delivers 16.4 dBm output power and 35.4 % power-added efficiency with 2.3 V power supply voltage into a 50 Ω load.
介绍了一种基于0.18 μm CMOS技术的5 ghz全集成CMOS e类单端功率放大器(PA)的设计。所提出的e类PA采用级联码拓扑和自偏置技术来减少器件应力。三个级联的d类驱动放大器用于实现e类功率级的急剧开关。所有器件集成在芯片上,芯片面积为1.0×1.3 mm2。测量结果表明,在2.3 V电源电压下,PA在50 Ω负载下的输出功率为16.4 dBm,功率增益效率为35.4%。
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引用次数: 11
A technology-independent table-based model for advanced GaN Schottky barrier diodes 先进GaN肖特基势垒二极管的技术独立表格模型
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401649
Z. Zhong, Yong-xin Guo
In this paper, a novel non-quasi-static table-based model has been developed for advanced Gallium Nitride (GaN) Schottky barrier diodes, which are widely used in current RF energy harvesting and wireless power transmission (WPT) applications. This novel table-based model can be simply built based on the measured S-parameters and I-V characteristics of these GaN diodes. In contrast with many complicated traditional models, this technology-independent modeling method includes no ambiguous curve fitting and de-embedding processes. Furthermore, this large-signal model is theoretically suitable for all kinds of diodes and could be easily imported into the computer-aided design (CAD) software. To verify its accuracy, measured and modeled results of different kinds of GaN diodes are compared and excellent agreement has been obtained.
针对目前广泛应用于射频能量收集和无线电力传输(WPT)领域的先进氮化镓(GaN)肖特基势垒二极管,建立了一种新的非准静态表模型。基于测量到的氮化镓二极管的s参数和I-V特性,可以简单地建立这种新的基于表格的模型。与许多复杂的传统模型相比,这种不依赖技术的建模方法不包括模糊曲线拟合和去嵌入过程。此外,该大信号模型理论上适用于各种二极管,并且易于导入计算机辅助设计(CAD)软件。为了验证其准确性,比较了不同类型GaN二极管的测量结果和建模结果,得到了很好的一致性。
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引用次数: 2
A hardware-efficient all-digital transmitter architecture for acoustic borehole telemetry systems 一种用于声波井眼遥测系统的硬件高效全数字发射机架构
Pub Date : 2012-11-01 DOI: 10.1109/RFIT.2012.6401608
P. Acharya, W. Goh, M. A. Arasu, Jun Yu, M. Je
This manuscript presents the architecture of a hardware-efficient all-digital acoustic borehole telemetry transmitter for use in the Measurement While Drilling (MWD) systems that are intended for the oil drilling service industry. The transmitter employs Direct Digital Synthesis (DDS) for carrier generation to mitigate the effects of carrier generation using analog approach, which is more susceptible to changes in device characteristics in high temperature environment. A hardware-efficient implementation of a Pulse Width Modulator (PWM) is presented to minimize silicon area as typically, the 0.8-/1-μm SOI-CMOS technology is adopted for high temperature electronics.
本文介绍了一种硬件高效的全数字声学井眼遥测变送器的结构,该变送器用于石油钻井服务行业的随钻测量(MWD)系统。发射机采用直接数字合成(Direct Digital Synthesis, DDS)进行载波生成,以减轻高温环境下采用模拟方式产生载波对器件特性变化的影响。本文提出了一种高效硬件实现的脉冲宽度调制器(PWM),以最大限度地减少硅面积,通常,高温电子器件采用0.8-/1-μm SOI-CMOS技术。
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引用次数: 4
期刊
2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
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