Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193165
C. Sia, K. S. Yeo, S. Chu, Z. Zeng, T. H. Lee
The impacts of metallization proximity for copper spiral inductors on silicon have been investigated in this paper. Performance of the spiral inductor versus area consumption trade-off with respect to its core diameter is evaluated qualitatively for the first time. Effects of the inductor's proximate grounded metallization on its overall inductive performance are also analyzed.
{"title":"Metallization proximity studies for copper spiral inductors on silicon","authors":"C. Sia, K. S. Yeo, S. Chu, Z. Zeng, T. H. Lee","doi":"10.1109/ICMTS.2002.1193165","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193165","url":null,"abstract":"The impacts of metallization proximity for copper spiral inductors on silicon have been investigated in this paper. Performance of the spiral inductor versus area consumption trade-off with respect to its core diameter is evaluated qualitatively for the first time. Effects of the inductor's proximate grounded metallization on its overall inductive performance are also analyzed.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122874729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193173
S. Ehrich, R. Bertenburg, M. Agethen, A. Brennemann, W. Brockerhoff, F. Tegude
For simulation of digital circuits realized in Direct Coupled FET Logic (DCFL) using depletion-type as well as enhancement-type Heterostructure-Field Effect Transistors (HFET) a consistent model that is able to describe both types of transistors is necessary. The developed analytical PSPICE model takes into account all relevant intrinsic and parasitic effects. This model can be used for dc- as well as rf-simulations and is scaleable with respect to gate-width as well as gate-length.
{"title":"A consistent and scalable PSPICE HFET-Model for DC- and S-parameter-simulation","authors":"S. Ehrich, R. Bertenburg, M. Agethen, A. Brennemann, W. Brockerhoff, F. Tegude","doi":"10.1109/ICMTS.2002.1193173","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193173","url":null,"abstract":"For simulation of digital circuits realized in Direct Coupled FET Logic (DCFL) using depletion-type as well as enhancement-type Heterostructure-Field Effect Transistors (HFET) a consistent model that is able to describe both types of transistors is necessary. The developed analytical PSPICE model takes into account all relevant intrinsic and parasitic effects. This model can be used for dc- as well as rf-simulations and is scaleable with respect to gate-width as well as gate-length.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115150100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193164
R. Havens, L. Tiemeijer, L. Garnbus
We demonstrate that the quality factors measured on on-wafer (spiral) inductor test-structures are largely influenced by the choice between ground-signal and ground-signal-ground probe configuration. In particular when the SOLT network analyzer calibration technique is used in combination with ground-signal probing, the quality factor value can be overestimated significantly.
{"title":"Impact of probe configuration and calibration techniques on quality factor determination of on-wafer inductors for GHz applications","authors":"R. Havens, L. Tiemeijer, L. Garnbus","doi":"10.1109/ICMTS.2002.1193164","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193164","url":null,"abstract":"We demonstrate that the quality factors measured on on-wafer (spiral) inductor test-structures are largely influenced by the choice between ground-signal and ground-signal-ground probe configuration. In particular when the SOLT network analyzer calibration technique is used in combination with ground-signal probing, the quality factor value can be overestimated significantly.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129705481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193162
S. Smith, M. Mccallum, A. Walton, J. Stevenson
Many of the recent advances in optical lithography have been driven by the utilisation of complex photomasks using Optical Proximity Correction (OPC) or phase shifting technologies. These masks are difficult and expensive to manufacture so the ability to test and characterise the mask making process is very important. This paper examines the issues involved in the use of relatively low cost Electrical Critical Dimension (ECD) measurement of mask features. Modified cross-bridge test structures have been designed to allow the on-mask measurement of dense and isolated, binary and phase shifted layouts. The results of electrical and Critical Dimension Scanning Electron Microscope (CD-SEM) testing of these structures are presented and indicate the lower variability associated with ECD measurements. In particular the adverse effect of phase shifting elements on the accuracy of SEM measurements is highlighted.
{"title":"Electrical CD characterisation of binary and alternating aperture phase shifting masks","authors":"S. Smith, M. Mccallum, A. Walton, J. Stevenson","doi":"10.1109/ICMTS.2002.1193162","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193162","url":null,"abstract":"Many of the recent advances in optical lithography have been driven by the utilisation of complex photomasks using Optical Proximity Correction (OPC) or phase shifting technologies. These masks are difficult and expensive to manufacture so the ability to test and characterise the mask making process is very important. This paper examines the issues involved in the use of relatively low cost Electrical Critical Dimension (ECD) measurement of mask features. Modified cross-bridge test structures have been designed to allow the on-mask measurement of dense and isolated, binary and phase shifted layouts. The results of electrical and Critical Dimension Scanning Electron Microscope (CD-SEM) testing of these structures are presented and indicate the lower variability associated with ECD measurements. In particular the adverse effect of phase shifting elements on the accuracy of SEM measurements is highlighted.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131172018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193199
G. Betta, N. Zorzi, Pierluigi Bellutti, M. Boscardin, G. Soncini
We show that a triple-junction photosensor can been obtained within a CMOS n-well technology with no additional process steps but a simple layout modification of the p-channel-stop mask. Results from the electrooptical characterisation of a specially designed test chip proved that the wavelength selectivity of the sensor can be used for colour detection and confirmed the device full compatibility with CMOS technology.
{"title":"Triple-junction colour sensor fully compatible with CMOS technology: results of a test chip","authors":"G. Betta, N. Zorzi, Pierluigi Bellutti, M. Boscardin, G. Soncini","doi":"10.1109/ICMTS.2002.1193199","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193199","url":null,"abstract":"We show that a triple-junction photosensor can been obtained within a CMOS n-well technology with no additional process steps but a simple layout modification of the p-channel-stop mask. Results from the electrooptical characterisation of a specially designed test chip proved that the wavelength selectivity of the sensor can be used for colour detection and confirmed the device full compatibility with CMOS technology.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193182
D. Souil, G. Guégan, G. Bertrand, O. Faynot, S. Deleonibs, G. Ghibaudo
For the first time, DC characteristics of conventional 50 nm MOSFETs have been correctly simulated by a BSIM4.1 model. This paper briefly describes the conventional architecture of the devices, and then the related strategy for parameter extraction is depicted. Typical simulation results are shown, illustrating that reverse short channel and 2D charge sharing effects are well fitted by this compact model.
{"title":"BSIM4.1 DC parameter extraction on 50 nm n-pMOSFETs","authors":"D. Souil, G. Guégan, G. Bertrand, O. Faynot, S. Deleonibs, G. Ghibaudo","doi":"10.1109/ICMTS.2002.1193182","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193182","url":null,"abstract":"For the first time, DC characteristics of conventional 50 nm MOSFETs have been correctly simulated by a BSIM4.1 model. This paper briefly describes the conventional architecture of the devices, and then the related strategy for parameter extraction is depicted. Typical simulation results are shown, illustrating that reverse short channel and 2D charge sharing effects are well fitted by this compact model.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122344669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193193
A. Skumanich, E. Ryabova
A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies for optical capture and SEM review.
{"title":"Methodology for defect impact studies under conditions of low electrical testing coverage","authors":"A. Skumanich, E. Ryabova","doi":"10.1109/ICMTS.2002.1193193","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193193","url":null,"abstract":"A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies for optical capture and SEM review.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121274461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193197
M. Hill, C. O’Mahony, P. Hughes, B. Lane, A. Mathewson
A low-thermal budget (<450/spl deg/C), multilayer CMOS compatible, surface micromachining process has been developed to fabricate IR bolometers and microswitches for RF and automatic test equipment applications. While there is a significant body of literature on the characterisation of thin films of materials for MEMS applications, the published work deals mainly with films or structures of one material. This paper describes the work undertaken to characterise the elastic modulus and residual stress in films of individual dielectric and metal layers and results on composites of dielectric and metal. This paper considers the results obtained for structures composed of oxide, oxide-aluminium/silicon-titanium, oxide-titanium and titanium layers. Material properties are measured using cantilever and fixed beam arrays fabricated in oxide, metal and composite metal/oxide films. The parameters extracted are residual stress, stress gradient and elastic modulus.
{"title":"Test structures for a MEMS SiO/sub x//metal process","authors":"M. Hill, C. O’Mahony, P. Hughes, B. Lane, A. Mathewson","doi":"10.1109/ICMTS.2002.1193197","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193197","url":null,"abstract":"A low-thermal budget (<450/spl deg/C), multilayer CMOS compatible, surface micromachining process has been developed to fabricate IR bolometers and microswitches for RF and automatic test equipment applications. While there is a significant body of literature on the characterisation of thin films of materials for MEMS applications, the published work deals mainly with films or structures of one material. This paper describes the work undertaken to characterise the elastic modulus and residual stress in films of individual dielectric and metal layers and results on composites of dielectric and metal. This paper considers the results obtained for structures composed of oxide, oxide-aluminium/silicon-titanium, oxide-titanium and titanium layers. Material properties are measured using cantilever and fixed beam arrays fabricated in oxide, metal and composite metal/oxide films. The parameters extracted are residual stress, stress gradient and elastic modulus.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115999642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193190
C. Hess, B. Stine, L. Weiland, T. Mitchell, M. Karnett, K. Gardner
Complexity of integrated circuits has led to many millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of < 10 faults per billion which requires test structures with huge chains of 1 million or more contact and vias. At the same time contacts and vias are getting smaller and thus their resistance is increasing for every new technology node. Consequently, the resistance of such chains becomes impossible to measure. To overcome this limit without increasing the number of measurement pads, we are proposing a Passive Multiplexer Array of via chains, which breaks up a huge contact/via chain in many individually measurable sub-chains. Accuracy of fail rates will be increased, since the fail rate can be determined based on many sub-chains, instead of being determined based on one huge chain only. Furthermore, this test structure better supports failure analysis, since it is faster to locate a faulty contact or via. No additional devices or process steps are required which allows implementation as short flows for fast process problem debugging.
{"title":"Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation","authors":"C. Hess, B. Stine, L. Weiland, T. Mitchell, M. Karnett, K. Gardner","doi":"10.1109/ICMTS.2002.1193190","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193190","url":null,"abstract":"Complexity of integrated circuits has led to many millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of < 10 faults per billion which requires test structures with huge chains of 1 million or more contact and vias. At the same time contacts and vias are getting smaller and thus their resistance is increasing for every new technology node. Consequently, the resistance of such chains becomes impossible to measure. To overcome this limit without increasing the number of measurement pads, we are proposing a Passive Multiplexer Array of via chains, which breaks up a huge contact/via chain in many individually measurable sub-chains. Accuracy of fail rates will be increased, since the fail rate can be determined based on many sub-chains, instead of being determined based on one huge chain only. Furthermore, this test structure better supports failure analysis, since it is faster to locate a faulty contact or via. No additional devices or process steps are required which allows implementation as short flows for fast process problem debugging.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"111 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114100560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193171
K. Doong, S. Hsieh, S.C. Lin, L. Hung, R.J. Wang, Binson Shen, J.W. Hisa, J. Guo, I. Chen, K. L. Young, C. Hsu
A novel methodology of physical and electrical design rule based statistical process monitoring and modeling (PEDR-SPMM) was proposed. By the aid of principal component analysis, the correlated physical and electrical parameters are decomposed into an independent variable set. The key parameters of multiple products mixed-run could be formulated by the independent variable set, which reduce the modeling complexity, and also provide a way to get a comparison between different technology nodes.
{"title":"An assessment of physical and electrical design rule based statistical process monitoring and modeling (PEDR-SPMM): for foundry manufacturing line of multiple-product mixed-run","authors":"K. Doong, S. Hsieh, S.C. Lin, L. Hung, R.J. Wang, Binson Shen, J.W. Hisa, J. Guo, I. Chen, K. L. Young, C. Hsu","doi":"10.1109/ICMTS.2002.1193171","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193171","url":null,"abstract":"A novel methodology of physical and electrical design rule based statistical process monitoring and modeling (PEDR-SPMM) was proposed. By the aid of principal component analysis, the correlated physical and electrical parameters are decomposed into an independent variable set. The key parameters of multiple products mixed-run could be formulated by the independent variable set, which reduce the modeling complexity, and also provide a way to get a comparison between different technology nodes.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"731 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133094352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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