Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193201
S.B. Yeo, J. Bordelon, S. Chu, M.F. Li, B. Tranchina, M. Harward, L. Chan, A. See
A robust addressable array test structure is presented, which allows automated characterization of the MOSFET's matching, with high area and time efficiency, accuracy and repeatability. It features CMOS switches to ensure a full test operation range, and prevent gate oxide breakdown of individual DUTs from destroying the functionality of the whole test structure. The test structure provides superior isolation to minimize cross talk while providing greater flexibility in testing. The testing result (Id mismatch) on wafers of 0.18 /spl mu/m technology is presented.
{"title":"A robust and production worthy addressable array architecture for deep sub-micron MOSFET's matching characterization","authors":"S.B. Yeo, J. Bordelon, S. Chu, M.F. Li, B. Tranchina, M. Harward, L. Chan, A. See","doi":"10.1109/ICMTS.2002.1193201","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193201","url":null,"abstract":"A robust addressable array test structure is presented, which allows automated characterization of the MOSFET's matching, with high area and time efficiency, accuracy and repeatability. It features CMOS switches to ensure a full test operation range, and prevent gate oxide breakdown of individual DUTs from destroying the functionality of the whole test structure. The test structure provides superior isolation to minimize cross talk while providing greater flexibility in testing. The testing result (Id mismatch) on wafers of 0.18 /spl mu/m technology is presented.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130623329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193188
M. O’Shea, D. McCarthy, R. Duane, K. McCarthy, A. Concannon, A. Mathewson
An accurate SPICE compatible model for a novel flash memory device, the Top Floating Gate (TFG) cell, is described. This device can be integrated into CMOS processes with minimal disruption to the standard process. The cell is programmed and erased by Fowler Nordheim tunnelling, which is a low power operation thereby complying with a major requirement of system-on-chip applications. The development of an accurate model for flash memory is complicated by the variable nature of the cell. In standard flash memory, the threshold voltage and, therefore, the drain current of the cell vary as the cell is programmed or erased. In the TFG case, both the threshold voltage and series resistance vary which further complicates the model development. Our model has been found to be accurate over the full range of floating gate charge.
{"title":"Compact model development for a new non-volatile memory cell architecture","authors":"M. O’Shea, D. McCarthy, R. Duane, K. McCarthy, A. Concannon, A. Mathewson","doi":"10.1109/ICMTS.2002.1193188","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193188","url":null,"abstract":"An accurate SPICE compatible model for a novel flash memory device, the Top Floating Gate (TFG) cell, is described. This device can be integrated into CMOS processes with minimal disruption to the standard process. The cell is programmed and erased by Fowler Nordheim tunnelling, which is a low power operation thereby complying with a major requirement of system-on-chip applications. The development of an accurate model for flash memory is complicated by the variable nature of the cell. In standard flash memory, the threshold voltage and, therefore, the drain current of the cell vary as the cell is programmed or erased. In the TFG case, both the threshold voltage and series resistance vary which further complicates the model development. Our model has been found to be accurate over the full range of floating gate charge.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193200
H. P. Tuinhout, G. Hoogzaad, M. Vertregt, R. Roovers, C. Erdmann
A new sub-site stepped multi-resistor test structure for characterising small resistance mismatch effects in resistor ladders is introduced. Using a Kelvin measurement method and a statistical data evaluation technique, this approach enables identification of very small (<0.05%) systematic mismatch patterns, which are associated with local mechanical stress as well as nanometre scale mask writing artifacts.
{"title":"Design and characterisation of a high precision resistor ladder test structure","authors":"H. P. Tuinhout, G. Hoogzaad, M. Vertregt, R. Roovers, C. Erdmann","doi":"10.1109/ICMTS.2002.1193200","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193200","url":null,"abstract":"A new sub-site stepped multi-resistor test structure for characterising small resistance mismatch effects in resistor ladders is introduced. Using a Kelvin measurement method and a statistical data evaluation technique, this approach enables identification of very small (<0.05%) systematic mismatch patterns, which are associated with local mechanical stress as well as nanometre scale mask writing artifacts.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124815530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193175
N. Nenadovic, L. Nanver, H. Schellevis, D. D. de Mooij, V. Zieren, J. Slotboom
A sensitive measurement method is used to discern between the thermal effects of very small changes in device surroundings and to extract high thermal resistance values. The description of electro-thermal behavior is complemented by nematic liquid crystal imaging and FEM simulations of the heat spreading around the device.
{"title":"Sensitive measurement method for evaluation of high thermal resistance in bipolar transistors","authors":"N. Nenadovic, L. Nanver, H. Schellevis, D. D. de Mooij, V. Zieren, J. Slotboom","doi":"10.1109/ICMTS.2002.1193175","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193175","url":null,"abstract":"A sensitive measurement method is used to discern between the thermal effects of very small changes in device surroundings and to extract high thermal resistance values. The description of electro-thermal behavior is complemented by nematic liquid crystal imaging and FEM simulations of the heat spreading around the device.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124247300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193163
R. Allen, M. Cresswell, C. E. Murabito, W. Guthrie, L. W. Linholm, C. Ellenwood, E. Hal Bogardus
A technique has been developed to determine the linewidths of the features of a prototype reference material for the calibration of CD (Critical-Dimension) metrology instruments. The reference features are fabricated in monocrystalline-silicon with the sidewalls aligned to the [111] lattice planes. A two-step measurement procedure is used to determine the CDs. The primary measurement is via lattice-plane counting of selected samples using High-Resolution Transmission Electron Microscopy (HRTEM); the transfer calibration is via Electrical CD (ECD) test-structure metrology. Samples of these prototype reference materials were measured and provided, as NIST Reference Material RM8110, to International SEMATECH for evaluation by its member companies. In this paper, we will describe the measurement procedure and show how the combined uncertainty of less than 15 nm was derived.
{"title":"Test structures for referencing electrical linewidth measurements to silicon lattice parameters using HRTEM","authors":"R. Allen, M. Cresswell, C. E. Murabito, W. Guthrie, L. W. Linholm, C. Ellenwood, E. Hal Bogardus","doi":"10.1109/ICMTS.2002.1193163","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193163","url":null,"abstract":"A technique has been developed to determine the linewidths of the features of a prototype reference material for the calibration of CD (Critical-Dimension) metrology instruments. The reference features are fabricated in monocrystalline-silicon with the sidewalls aligned to the [111] lattice planes. A two-step measurement procedure is used to determine the CDs. The primary measurement is via lattice-plane counting of selected samples using High-Resolution Transmission Electron Microscopy (HRTEM); the transfer calibration is via Electrical CD (ECD) test-structure metrology. Samples of these prototype reference materials were measured and provided, as NIST Reference Material RM8110, to International SEMATECH for evaluation by its member companies. In this paper, we will describe the measurement procedure and show how the combined uncertainty of less than 15 nm was derived.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134584723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193179
H. Lue, T. Tseng, G. Huang
We have developed a new method to investigate the dielectric and interfacial properties of gate dielectric thin films by microwave measurement. BST thin films were deposited on 10 /spl Omega/-cm (normal) and 10 k/spl Omega/-cm (high-resistivity, HR) silicon substrates at the same time by RF magnetron sputtering. For the BST/HR-silicon, coplanar waveguides (CPW) were fabricated and measured at microwave frequencies with Thru-Reflect-Line (TRL) calibration while CV measurements were carried out for BST/normal-silicon. From the phase change of CPW transmission line and the maximum capacitance in CV measurement, the dielectric constants of both the BST thin film and interface layer can be determined. Furthermore, the behaviors of insertion loss versus bias voltage were found to be correlated with the trap states density. The results indicate that our method can provide useful information to study the dielectric and interfacial properties of metal-insulator-semiconductor (MIS) structures.
{"title":"A novel method to characterize the dielectric and interfacial properties of Ba/sub 0.5/Sr/sub 0.5/TiO/sub 3/ (BST)/Si by microwave measurement","authors":"H. Lue, T. Tseng, G. Huang","doi":"10.1109/ICMTS.2002.1193179","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193179","url":null,"abstract":"We have developed a new method to investigate the dielectric and interfacial properties of gate dielectric thin films by microwave measurement. BST thin films were deposited on 10 /spl Omega/-cm (normal) and 10 k/spl Omega/-cm (high-resistivity, HR) silicon substrates at the same time by RF magnetron sputtering. For the BST/HR-silicon, coplanar waveguides (CPW) were fabricated and measured at microwave frequencies with Thru-Reflect-Line (TRL) calibration while CV measurements were carried out for BST/normal-silicon. From the phase change of CPW transmission line and the maximum capacitance in CV measurement, the dielectric constants of both the BST thin film and interface layer can be determined. Furthermore, the behaviors of insertion loss versus bias voltage were found to be correlated with the trap states density. The results indicate that our method can provide useful information to study the dielectric and interfacial properties of metal-insulator-semiconductor (MIS) structures.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116377688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193191
R. Ashton
Test structures intended for performance verification of transmission line pulse (TLP) systems have been designed and tested. They consist of simple resistors in either copper or silicide clad polysilicon. The copper structures proved unsuitable due to excess heating and melting of any reasonable geometry. The silicide clad polysilicon proved more successful. A simple model of resistive heating accounts for observed non-linearity in the structures under high current stress.
{"title":"Verification structures for transmission line pulse measurements","authors":"R. Ashton","doi":"10.1109/ICMTS.2002.1193191","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193191","url":null,"abstract":"Test structures intended for performance verification of transmission line pulse (TLP) systems have been designed and tested. They consist of simple resistors in either copper or silicide clad polysilicon. The copper structures proved unsuitable due to excess heating and melting of any reasonable geometry. The silicide clad polysilicon proved more successful. A simple model of resistive heating accounts for observed non-linearity in the structures under high current stress.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"40 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121675150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193167
Jeonghu Han, M. Je, Hyungcheol Shin
This paper proposes a simple and accurate method for extracting substrate resistance of an RF MOSFET from the measured network parameters. The extraction results for 0.18-/spl mu/m MOSFETs are presented for various bias conditions and devices with different geometries.
{"title":"Extraction method for substrate resistance of RF MOSFETs","authors":"Jeonghu Han, M. Je, Hyungcheol Shin","doi":"10.1109/ICMTS.2002.1193167","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193167","url":null,"abstract":"This paper proposes a simple and accurate method for extracting substrate resistance of an RF MOSFET from the measured network parameters. The extraction results for 0.18-/spl mu/m MOSFETs are presented for various bias conditions and devices with different geometries.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122108887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193192
J. Ellis
Polysilicon field transistors are traditionally overlapped onto thin oxide regions to connect to the source and drain of a transistor. Submicron processes have gate oxides with breakdown voltages below the field threshold and the traditional layout is not suitable. It is however necessary to maintain a channel to the source and drain, but this can be accomplished using a field plate device. By placing a metal gate over the poly gate, and biasing the metal gate into strong inversion, it is possible for the polysilicon gate to control the transistor current. In fact with this one structure both the polysilicon and metal field threshold voltages can be ascertained.
{"title":"Direct measurement of field transistor threshold voltages using inversion layer fed transistors in deep submicron processes","authors":"J. Ellis","doi":"10.1109/ICMTS.2002.1193192","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193192","url":null,"abstract":"Polysilicon field transistors are traditionally overlapped onto thin oxide regions to connect to the source and drain of a transistor. Submicron processes have gate oxides with breakdown voltages below the field threshold and the traditional layout is not suitable. It is however necessary to maintain a channel to the source and drain, but this can be accomplished using a field plate device. By placing a metal gate over the poly gate, and biasing the metal gate into strong inversion, it is possible for the polysilicon gate to control the transistor current. In fact with this one structure both the polysilicon and metal field threshold voltages can be ascertained.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122616349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193204
S. Hausser, S. Majoni, H. Schligtenhorst, G. Kolwe
During the qualification of a 0.35/spl mu/m CMOS process, it was observed that diffusion resistors showed a systematic mismatch, depending on the position on the wafer. The mismatch increased from the center of the wafer to the outer regions. Various experiments showed that the mismatch was caused by spinning the wafer during the resist development process. Changing this process eliminated the systematic diffusion resistor mismatch.
{"title":"Systematic mismatch in diffusion resistors caused by photolithography","authors":"S. Hausser, S. Majoni, H. Schligtenhorst, G. Kolwe","doi":"10.1109/ICMTS.2002.1193204","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193204","url":null,"abstract":"During the qualification of a 0.35/spl mu/m CMOS process, it was observed that diffusion resistors showed a systematic mismatch, depending on the position on the wafer. The mismatch increased from the center of the wafer to the outer regions. Various experiments showed that the mismatch was caused by spinning the wafer during the resist development process. Changing this process eliminated the systematic diffusion resistor mismatch.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117061758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：