Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241600
K. Itoh
Forefront of the silicon quantum computer development is described.
介绍了硅量子计算机发展的前沿。
{"title":"1-1 Forefront of Silicon Quantum Computing","authors":"K. Itoh","doi":"10.23919/SISPAD49475.2020.9241600","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241600","url":null,"abstract":"Forefront of the silicon quantum computer development is described.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122653053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241623
Junbeom Seo, M. Shin
We have demonstrated the dependence of the atomic terminations on ferroelectric tunnel junctions (FTJs) based on ferroelectric HfO2 using density functional theory calculation. The atomistic structures of HfO2 FTJs with various interfaces are constructed and their device performances are calculated. We have found that the potential barrier is significantly tailored by atomic species of the terminating atom of HfO2. In particular, the atomistic effect contributes to the electric field across the tunnel barrier, which leads to asymmetric behavior. We demonstrate that the ON/OFF current ratio of FTJs can be improved by adjusting the atomic terminations, albeit without the external asymmetric structure such as dissimilar metal electrodes and additional composite layers.
{"title":"Effect of Atomic Interface on Tunnel Barrier in Ferroelectric HfO2 Tunnel Junctions","authors":"Junbeom Seo, M. Shin","doi":"10.23919/SISPAD49475.2020.9241623","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241623","url":null,"abstract":"We have demonstrated the dependence of the atomic terminations on ferroelectric tunnel junctions (FTJs) based on ferroelectric HfO2 using density functional theory calculation. The atomistic structures of HfO2 FTJs with various interfaces are constructed and their device performances are calculated. We have found that the potential barrier is significantly tailored by atomic species of the terminating atom of HfO2. In particular, the atomistic effect contributes to the electric field across the tunnel barrier, which leads to asymmetric behavior. We demonstrate that the ON/OFF current ratio of FTJs can be improved by adjusting the atomic terminations, albeit without the external asymmetric structure such as dissimilar metal electrodes and additional composite layers.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116007609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241628
M. Kobayashi
Negative capacitance FET is a promising CMOS technology booster which may break the limit of 60mV/dec in subthreshold swing (SS) without degrading performance. We investigated the physical mechanism of negative capacitance in ferroelectric FET (FeFET) by considering the dynamics of the polarization in ferroelectric gate insulator: transient negative capacitance (TNC). Polarization switching and depolarization effect are essential to cause negative capacitance effect, that is, apparent surface potential amplification in deep subthreshold region with small depletion layer capacitance. Moreover, unique features of reverse DIBL and negative differential resistance (NDR) are also reproduced by the transient negative capacitance theory. Modeling charged defect in FeFET, hysteresis-free sub-60mV/dec SS can be realized. TNC theory is regarded as a comprehensive framework to model subthreshold characteristics of FeFET.
{"title":"On the Physical Mechanism of Negative Capacitance Effect in Ferroelectric FET","authors":"M. Kobayashi","doi":"10.23919/SISPAD49475.2020.9241628","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241628","url":null,"abstract":"Negative capacitance FET is a promising CMOS technology booster which may break the limit of 60mV/dec in subthreshold swing (SS) without degrading performance. We investigated the physical mechanism of negative capacitance in ferroelectric FET (FeFET) by considering the dynamics of the polarization in ferroelectric gate insulator: transient negative capacitance (TNC). Polarization switching and depolarization effect are essential to cause negative capacitance effect, that is, apparent surface potential amplification in deep subthreshold region with small depletion layer capacitance. Moreover, unique features of reverse DIBL and negative differential resistance (NDR) are also reproduced by the transient negative capacitance theory. Modeling charged defect in FeFET, hysteresis-free sub-60mV/dec SS can be realized. TNC theory is regarded as a comprehensive framework to model subthreshold characteristics of FeFET.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126305864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241677
V. Georgiev, A. Sengupta, P. Maciazek, O. Badami, C. Medina-Bailón, T. Dutta, F. Adamu-Lema, A. Asenov
In this work, we report simulations on a GaAs-AlGaAs gated nanowire resonant tunneling diode (RTD) for tunable terahertz communication applications. All calculations are performed with the self-consistent Non-Equilibrium Green’s Function (NEGF) quantum transport formalism implemented in our in-house Nano-Electronic Simulation Software (NESS). Our simulations successfully capture the detailed picture of the quantum mechanical effects such as quantum confinement and resonant tunneling of electrons through barriers in such structures. Moreover, we report for the first time the correlation between the gate-bias voltage and the position of the resonant peak (VR) in the current - voltage characteristics. Such Vr, which is associated with tunneling effects in RTD, could lead to tunable terahertz generation and detection for communication applications.
{"title":"Simulation of gated GaAs-AlGaAs resonant tunneling diodes for tunable terahertz communication applications","authors":"V. Georgiev, A. Sengupta, P. Maciazek, O. Badami, C. Medina-Bailón, T. Dutta, F. Adamu-Lema, A. Asenov","doi":"10.23919/SISPAD49475.2020.9241677","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241677","url":null,"abstract":"In this work, we report simulations on a GaAs-AlGaAs gated nanowire resonant tunneling diode (RTD) for tunable terahertz communication applications. All calculations are performed with the self-consistent Non-Equilibrium Green’s Function (NEGF) quantum transport formalism implemented in our in-house Nano-Electronic Simulation Software (NESS). Our simulations successfully capture the detailed picture of the quantum mechanical effects such as quantum confinement and resonant tunneling of electrons through barriers in such structures. Moreover, we report for the first time the correlation between the gate-bias voltage and the position of the resonant peak (VR) in the current - voltage characteristics. Such Vr, which is associated with tunneling effects in RTD, could lead to tunable terahertz generation and detection for communication applications.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128318747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241603
S. Kola, Yiming Li, Narasimhulu Thoti
We estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes. Devices with various dielectric spacers from low- to high-κ including asymmetric dual spacers (ADS) are considered. More than 31% boost on the normalized on-state currents is observed for the explored devices with high-κ and ADS spacers. Similarly, for the normalized off-state currents, more than 50% reduction is achieved. The largest magnitude of the RTN (ΔID/ID×100%) is 6.7% for the nominal GAA Si NS MOSFET with an effective channel width of 40-nm.
我们估计了栅极全能(GAA)硅纳米线(NW)和纳米片(NS)金属氧化物半导体场效应晶体管(mosfet)在亚5nm节点上的直流特性和单电荷阱(SCT)诱导的随机电报噪声(RTN)。考虑了具有从低到高-κ的各种介电间隔器的器件，包括不对称双间隔器(ADS)。对于具有高κ和ADS间隔的探索器件，可以观察到超过31%的归一化导通电流升压。同样，对于归一化的非状态电流，可以实现50%以上的降低。对于标称GAA Si NS MOSFET，有效通道宽度为40 nm, RTN的最大幅度(ΔID/ID×100%)为6.7%。
{"title":"Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers","authors":"S. Kola, Yiming Li, Narasimhulu Thoti","doi":"10.23919/SISPAD49475.2020.9241603","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241603","url":null,"abstract":"We estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes. Devices with various dielectric spacers from low- to high-κ including asymmetric dual spacers (ADS) are considered. More than 31% boost on the normalized on-state currents is observed for the explored devices with high-κ and ADS spacers. Similarly, for the normalized off-state currents, more than 50% reduction is achieved. The largest magnitude of the RTN (ΔID/ID×100%) is 6.7% for the nominal GAA Si NS MOSFET with an effective channel width of 40-nm.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128634347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241665
T. Iizuka, D. Navarro, M. Miura-Mattausch, Hidenori Kikuchihara, H. Mattausch, Daniela Rus
Further compact-model development for LDMOS is reported, enabling concurrent device and circuit optimizations by only varying the ratio between gate-overlap length $(L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}})$ and resistive-drift length $(L_{mathrm{drift}})$. Different from the conventional carrier-dynamics understanding within these two regions, LDMOS shows abnormal characteristics during such a ratio variation. The pinch-off condition occurs under the gate overlap region, and the pinch-off point is found to move along $L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}}$ with increased drain voltage, even under the accumulation condition. This means that carrier conductivity is no longer controlled by the gate voltage but by the drain voltage. The precise pinch-off condition is determined by the field balancing within gate-overlap and resistive-drift regions. The pinch-off length $(Delta L)$ within $L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}}$ sustains $V_{mathrm{ds}}$ together with $L_{mathrm{drift}}$. Thus, the pinch-off region contributes as a part of $L_{mathrm{drift}}$ and improves the device’s high-voltage applicability. A new model is developed to describe this balancing phenomenon analytically, where the key physical quantity is $Delta L$. The developed $Delta L$ model considers the potential distribution along $L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}}$ together with $L_{mathrm{drift}}$. At the pinch-off point, the field induced by $V_{mathrm{g}s}$ and that by $V_{mathrm{ds}}$ are assumed to be equal, which derives an analytical description for $Delta L$. Evaluation results with the developed model are verified with 2D-numerical-device-simulation results.
{"title":"Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap-Length Modification","authors":"T. Iizuka, D. Navarro, M. Miura-Mattausch, Hidenori Kikuchihara, H. Mattausch, Daniela Rus","doi":"10.23919/SISPAD49475.2020.9241665","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241665","url":null,"abstract":"Further compact-model development for LDMOS is reported, enabling concurrent device and circuit optimizations by only varying the ratio between gate-overlap length $(L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}})$ and resistive-drift length $(L_{mathrm{drift}})$. Different from the conventional carrier-dynamics understanding within these two regions, LDMOS shows abnormal characteristics during such a ratio variation. The pinch-off condition occurs under the gate overlap region, and the pinch-off point is found to move along $L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}}$ with increased drain voltage, even under the accumulation condition. This means that carrier conductivity is no longer controlled by the gate voltage but by the drain voltage. The precise pinch-off condition is determined by the field balancing within gate-overlap and resistive-drift regions. The pinch-off length $(Delta L)$ within $L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}}$ sustains $V_{mathrm{ds}}$ together with $L_{mathrm{drift}}$. Thus, the pinch-off region contributes as a part of $L_{mathrm{drift}}$ and improves the device’s high-voltage applicability. A new model is developed to describe this balancing phenomenon analytically, where the key physical quantity is $Delta L$. The developed $Delta L$ model considers the potential distribution along $L_{mathrm{o}mathrm{v}mathrm{e}mathrm{r}}$ together with $L_{mathrm{drift}}$. At the pinch-off point, the field induced by $V_{mathrm{g}s}$ and that by $V_{mathrm{ds}}$ are assumed to be equal, which derives an analytical description for $Delta L$. Evaluation results with the developed model are verified with 2D-numerical-device-simulation results.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128646761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241682
A. Oshiyama, K. Bui, M. Boero, Y. Kangawa, K. Shiraishi
We report first-principles calculations based on the density-functional theory that clarify atomic reactions of ammonia decomposition and subsequent nitrogen incorporation during GaN epitaxial growth. We find that Ga-Ga weak bonds are ubiquitous on Ga-rich growing surface and responsible for the growth reactions. Furthermore, Car-Parrinello Molecular Dynamics simulations predict the existence of 2-dimensional Ga liquid phase, providing new insight into the epitaxial growth. The obtained results are expected to become basics for multi-scale growth simulations in future.
{"title":"Computics Approach toward Clarification of Atomic Reactions during Epitaxial Growth of GaN","authors":"A. Oshiyama, K. Bui, M. Boero, Y. Kangawa, K. Shiraishi","doi":"10.23919/SISPAD49475.2020.9241682","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241682","url":null,"abstract":"We report first-principles calculations based on the density-functional theory that clarify atomic reactions of ammonia decomposition and subsequent nitrogen incorporation during GaN epitaxial growth. We find that Ga-Ga weak bonds are ubiquitous on Ga-rich growing surface and responsible for the growth reactions. Furthermore, Car-Parrinello Molecular Dynamics simulations predict the existence of 2-dimensional Ga liquid phase, providing new insight into the epitaxial growth. The obtained results are expected to become basics for multi-scale growth simulations in future.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130103328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241673
G. Atmaca, M. Jaud, Julien Buckley Jérôme, A. Yvon, E. Collard
In lateral power diodes, the conductivity modulation mechanism can pave the way to the demonstration of surge current capability. In a Hybrid Anode Diode concept with a p-GaN layer, an anode contact on p-GaN layer can be a source of hole injection that increases the electron density at AlGaN/GaN interface. The role of p-GaN layer on the surge current capability and its demonstration are investigated through TCAD simulations that explain the role of hole barrier tunneling at anode metal/p-GaN interface. These simulations show that surge current can occur in case of Ohmic p-GaN contact as the injected holes can lead to create additional electron density in the channel as well as a hole current to support the total diode current.
{"title":"Surge Current Capability in lateral AlGaN/GaN Hybrid Anode Diodes with p-GaN/Schottky Anode","authors":"G. Atmaca, M. Jaud, Julien Buckley Jérôme, A. Yvon, E. Collard","doi":"10.23919/SISPAD49475.2020.9241673","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241673","url":null,"abstract":"In lateral power diodes, the conductivity modulation mechanism can pave the way to the demonstration of surge current capability. In a Hybrid Anode Diode concept with a p-GaN layer, an anode contact on p-GaN layer can be a source of hole injection that increases the electron density at AlGaN/GaN interface. The role of p-GaN layer on the surge current capability and its demonstration are investigated through TCAD simulations that explain the role of hole barrier tunneling at anode metal/p-GaN interface. These simulations show that surge current can occur in case of Ohmic p-GaN contact as the injected holes can lead to create additional electron density in the channel as well as a hole current to support the total diode current.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241616
Yuhei Suzuki, Y. Fujita, K. Fauziah, T. Nogita, H. Ikeda, Takanobu Watanabe, Y. Kamakura
A phonon transport in Si wire structures were simulated based on a Monte Carlo method to clarify the influence of the wire geometry and the surface roughness on thermal conductivity and the phonon-drag component of Seebeck coefficient. The mean free path (MFP) spectrum was estimated by tracing the simulated phonons. The MFPs of 1 THz phonons which mainly contribute to Seebeck coefficient become shorter with a decrease of the wire width for rough surfaces. This agrees with experimental observation of Seebeck coefficient. The MFPs of 3 THz phonons which mainly contribute to thermal conductivity were influenced even by small-roughness surfaces.
{"title":"Estimation of Phonon Mean Free Path in Small-Scaled Si Wire by Monte Carlo Simulation","authors":"Yuhei Suzuki, Y. Fujita, K. Fauziah, T. Nogita, H. Ikeda, Takanobu Watanabe, Y. Kamakura","doi":"10.23919/SISPAD49475.2020.9241616","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241616","url":null,"abstract":"A phonon transport in Si wire structures were simulated based on a Monte Carlo method to clarify the influence of the wire geometry and the surface roughness on thermal conductivity and the phonon-drag component of Seebeck coefficient. The mean free path (MFP) spectrum was estimated by tracing the simulated phonons. The MFPs of 1 THz phonons which mainly contribute to Seebeck coefficient become shorter with a decrease of the wire width for rough surfaces. This agrees with experimental observation of Seebeck coefficient. The MFPs of 3 THz phonons which mainly contribute to thermal conductivity were influenced even by small-roughness surfaces.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130936694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241591
Narasimhulu Thoti, Yiming Li, S. Kola, S. Samukawa
Nanosheet line tunnel-field effect transistors (NLTFETs) are for the first time proposed by utilizing the advantages of ferroelectricity through HZO materials. Three ferroelectric line TFETs have been proposed and investigated. Among these, the metal-ferroelectric-semiconductor (MFS) structure has shown superior performance than the other two variants. The factors of electric field and electron barrier tunneling have been addressed to govern the performance of these structures. In addition, the effects of the ferroelectric (Hf0.5 Zr0.5 O2) thickness (tFE) and the dielectric constant have been discussed. The MFS NLTFETs can effectively utilize the advantages of ferroelectric than the other variants. High on-current of 175.6 $mu mathrm{A}/mu mathrm{m}$ and low off-current of 38.4 aA/$mu mathrm{m}$ are achieved at tFE of 4 nm through proper utilization of gate-overlap on to the drain side. Furthermore, the proposed MFS structure successfully delivers low average and minimum subthreshold swings even at very thin tFE.
{"title":"High-Performance Metal-Ferroeletric-Semiconductor Nanosheet Line Tunneling Field Effect Transistors with Strained SiGe","authors":"Narasimhulu Thoti, Yiming Li, S. Kola, S. Samukawa","doi":"10.23919/SISPAD49475.2020.9241591","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241591","url":null,"abstract":"Nanosheet line tunnel-field effect transistors (NLTFETs) are for the first time proposed by utilizing the advantages of ferroelectricity through HZO materials. Three ferroelectric line TFETs have been proposed and investigated. Among these, the metal-ferroelectric-semiconductor (MFS) structure has shown superior performance than the other two variants. The factors of electric field and electron barrier tunneling have been addressed to govern the performance of these structures. In addition, the effects of the ferroelectric (Hf0.5 Zr0.5 O2) thickness (tFE) and the dielectric constant have been discussed. The MFS NLTFETs can effectively utilize the advantages of ferroelectric than the other variants. High on-current of 175.6 $mu mathrm{A}/mu mathrm{m}$ and low off-current of 38.4 aA/$mu mathrm{m}$ are achieved at tFE of 4 nm through proper utilization of gate-overlap on to the drain side. Furthermore, the proposed MFS structure successfully delivers low average and minimum subthreshold swings even at very thin tFE.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132283417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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