Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852628
R. Bergamaschi, William R. Lee, Duane E. Richardson, S. Bhattacharya, Michael Muhlada, Ronaldo Wagner, Arthur Weiner, Foster White
The reuse of pre-designed and pre-verified IP blocks or cores has been touted as the enabler of large systems-on-chip designs. However, the lack of appropriate tools and the increasing complexity of such cores makes them inherently difficult and error-prone to use. This paper presents a new tool, "Coral", for the design of systems using cores. Coral is based on a new synthesizable virtual design representation which is automatically synthesized to a real design. Novel algorithms are presented to interconnect cores automatically as well as configure system parameters, such as interrupt maps, DMA channel assignments, etc. Coral significantly reduces the time, complexity and potential for errors associated with SoC integration.
{"title":"Coral-automating the design of systems-on-chip using cores","authors":"R. Bergamaschi, William R. Lee, Duane E. Richardson, S. Bhattacharya, Michael Muhlada, Ronaldo Wagner, Arthur Weiner, Foster White","doi":"10.1109/CICC.2000.852628","DOIUrl":"https://doi.org/10.1109/CICC.2000.852628","url":null,"abstract":"The reuse of pre-designed and pre-verified IP blocks or cores has been touted as the enabler of large systems-on-chip designs. However, the lack of appropriate tools and the increasing complexity of such cores makes them inherently difficult and error-prone to use. This paper presents a new tool, \"Coral\", for the design of systems using cores. Coral is based on a new synthesizable virtual design representation which is automatically synthesized to a real design. Novel algorithms are presented to interconnect cores automatically as well as configure system parameters, such as interrupt maps, DMA channel assignments, etc. Coral significantly reduces the time, complexity and potential for errors associated with SoC integration.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"79 1","pages":"109-112"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79149367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852621
Y. Makris, A. Orailoglu, P. Vishakantaiah
We introduce a hierarchical test generation methodology for modular designs, employing exclusively gate-level ATPG. Based on the notion of modular transparency, the search space of the design is reduced to alleviate the complexity of gate-level test generation. Although ATPG is applied at the full circuit, faults in each module are targeted individually, while the surrounding modules are replaced by their much simpler, transparency-equivalent logic. As analyzed theoretically and as demonstrated through a set of experimental data, the proposed methodology results in significant test generation speed-up, while preserving comparable fault coverage and vector count to full-circuit gate-level ATPG.
{"title":"Modular test generation and concurrent transparency-based test translation using gate-level ATPG","authors":"Y. Makris, A. Orailoglu, P. Vishakantaiah","doi":"10.1109/CICC.2000.852621","DOIUrl":"https://doi.org/10.1109/CICC.2000.852621","url":null,"abstract":"We introduce a hierarchical test generation methodology for modular designs, employing exclusively gate-level ATPG. Based on the notion of modular transparency, the search space of the design is reduced to alleviate the complexity of gate-level test generation. Although ATPG is applied at the full circuit, faults in each module are targeted individually, while the surrounding modules are replaced by their much simpler, transparency-equivalent logic. As analyzed theoretically and as demonstrated through a set of experimental data, the proposed methodology results in significant test generation speed-up, while preserving comparable fault coverage and vector count to full-circuit gate-level ATPG.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"14 1","pages":"75-78"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76261223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852699
M. Allam, M. Elmasry
This paper presents a new logic style DyCML for low-power high-performance VLSI applications. The new logic family combines the speed, low supply voltage and noise immunity advantages of MCML circuits while achieving the low standby current and design simplicity features of dynamic circuits. Simulation results show that DyCML circuits are superior to CMOS and DCVS logic styles in terms of power and delay. A 16 bit DyCML Carry Look Ahead Adder (CLA) fabricated in 0.6 /spl mu/m achieves a delay of 1.1 ns while dissipating 21.2 mW at 400 MHz.
{"title":"Dynamic current mode logic (DyCML), a new low-power high-performance logic family","authors":"M. Allam, M. Elmasry","doi":"10.1109/CICC.2000.852699","DOIUrl":"https://doi.org/10.1109/CICC.2000.852699","url":null,"abstract":"This paper presents a new logic style DyCML for low-power high-performance VLSI applications. The new logic family combines the speed, low supply voltage and noise immunity advantages of MCML circuits while achieving the low standby current and design simplicity features of dynamic circuits. Simulation results show that DyCML circuits are superior to CMOS and DCVS logic styles in terms of power and delay. A 16 bit DyCML Carry Look Ahead Adder (CLA) fabricated in 0.6 /spl mu/m achieves a delay of 1.1 ns while dissipating 21.2 mW at 400 MHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"15 1","pages":"421-424"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77122747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852645
O. Shana'a, I. Linscott, L. Tyler
A highly-optimized SiGe RF bipolar front-end design is proposed. The optimum noise figure (NF/sub opt/) of a bipolar device is introduced in contrast with the minimum noise figure (NF/sub min/). An analytical method to design the low noise amplifier (LNA) at the optimum noise figure point is derived. The optimized LNA design scales linearly with frequency for multi-band RF front-end design. The optimization method is extended to the design of an improved Gilbert cell active mixer. The technique was demonstrated on a 1800 MHz SiGe bipolar RF front-end whose LNA achieves a 1.3 dB NF at a bias current of 4.5 mA while the mixer achieves a single-sideband noise figure (SSB NF) of 6.5 dB at only 4.8 mA.
{"title":"Frequency-scalable SiGe bipolar RFIC front-end design","authors":"O. Shana'a, I. Linscott, L. Tyler","doi":"10.1109/CICC.2000.852645","DOIUrl":"https://doi.org/10.1109/CICC.2000.852645","url":null,"abstract":"A highly-optimized SiGe RF bipolar front-end design is proposed. The optimum noise figure (NF/sub opt/) of a bipolar device is introduced in contrast with the minimum noise figure (NF/sub min/). An analytical method to design the low noise amplifier (LNA) at the optimum noise figure point is derived. The optimized LNA design scales linearly with frequency for multi-band RF front-end design. The optimization method is extended to the design of an improved Gilbert cell active mixer. The technique was demonstrated on a 1800 MHz SiGe bipolar RF front-end whose LNA achieves a 1.3 dB NF at a bias current of 4.5 mA while the mixer achieves a single-sideband noise figure (SSB NF) of 6.5 dB at only 4.8 mA.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"263 1","pages":"183-186"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80095048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852694
T. Reimann, F. Krummenacher, B. Willing, P. Muralt, M. Declercq
A 16-channel readout circuit able to process low frequency modulated (1-10 hertz) current signals in the pico-ampere range from a thin film pyroelectric array detector has been integrated in a 0.7 /spl mu/m CMOS technology. Each channel consists of a high gain (14 G/spl Omega/) transimpedance preamplifier having an input-referred current noise spectral density of 1.5 fA//spl radic/Hz at 10 Hz. A multiplier for demodulating the signal follows the preamplifier (chopper frequency fixed at 10 Hz). Finally, the signal is integrated over 8 periods before being converted by a 12-bit A/D converter. The multiplication, the integration and the A/D conversion are implemented within a single block using a first-order switched-capacitor incremental A/D converter architecture.
{"title":"A CMOS readout circuit for pico-ampere thin film pyroelectric array detectors","authors":"T. Reimann, F. Krummenacher, B. Willing, P. Muralt, M. Declercq","doi":"10.1109/CICC.2000.852694","DOIUrl":"https://doi.org/10.1109/CICC.2000.852694","url":null,"abstract":"A 16-channel readout circuit able to process low frequency modulated (1-10 hertz) current signals in the pico-ampere range from a thin film pyroelectric array detector has been integrated in a 0.7 /spl mu/m CMOS technology. Each channel consists of a high gain (14 G/spl Omega/) transimpedance preamplifier having an input-referred current noise spectral density of 1.5 fA//spl radic/Hz at 10 Hz. A multiplier for demodulating the signal follows the preamplifier (chopper frequency fixed at 10 Hz). Finally, the signal is integrated over 8 periods before being converted by a 12-bit A/D converter. The multiplication, the integration and the A/D conversion are implemented within a single block using a first-order switched-capacitor incremental A/D converter architecture.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"46 1","pages":"395-398"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78436998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852706
J. Phillips
Model reduction is a popular approach for incorporating detailed physical effects into high level simulations. In this paper the author presents a simple method for automatically extracting macromodels of nonlinear circuits with time-varying operating points. The models generated are truly "reduced" meaning that the complexity of macromodel evaluation is not strongly dependent on the size or complexity of the original detailed circuit description.
{"title":"Automated extraction of nonlinear circuit macromodels","authors":"J. Phillips","doi":"10.1109/CICC.2000.852706","DOIUrl":"https://doi.org/10.1109/CICC.2000.852706","url":null,"abstract":"Model reduction is a popular approach for incorporating detailed physical effects into high level simulations. In this paper the author presents a simple method for automatically extracting macromodels of nonlinear circuits with time-varying operating points. The models generated are truly \"reduced\" meaning that the complexity of macromodel evaluation is not strongly dependent on the size or complexity of the original detailed circuit description.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"1966 1","pages":"451-454"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91341374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852673
J. Kenney, Faramarz Sabouri, V. Leung, J. Guido, E. Zimany, A. Agrillo, J. Trackim, J. Khoury, Reza Shariatdous
This chip integrates a 4 channel analog front-end for central office ADSL modems. The receive path has a programmable gain amplifier (PGA) with 30 dB of range followed by a fourth-order 2-bit sigma-delta modulator clocking at 35 MHz. The transmit path uses a 14-bit current steering D/A converter followed by a fourth-order low-pass filter. The device is implemented in 0.35 /spl mu/m CMOS and consumes less than 160 mW per channel. It is packaged in a 100 pin MQFP package.
{"title":"A 4 channel analog front end for central office ADSL modems","authors":"J. Kenney, Faramarz Sabouri, V. Leung, J. Guido, E. Zimany, A. Agrillo, J. Trackim, J. Khoury, Reza Shariatdous","doi":"10.1109/CICC.2000.852673","DOIUrl":"https://doi.org/10.1109/CICC.2000.852673","url":null,"abstract":"This chip integrates a 4 channel analog front-end for central office ADSL modems. The receive path has a programmable gain amplifier (PGA) with 30 dB of range followed by a fourth-order 2-bit sigma-delta modulator clocking at 35 MHz. The transmit path uses a 14-bit current steering D/A converter followed by a fourth-order low-pass filter. The device is implemented in 0.35 /spl mu/m CMOS and consumes less than 160 mW per channel. It is packaged in a 100 pin MQFP package.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"105 ","pages":"307-310"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91451245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852675
J. Guinea, L. Tomasini, Santo Maggio, Massimiliano Rutar
The 155 Mbps (STM-l electrical) transceiver complies with the relevant ITU-T recommendations. The transmit channel features CMI transmission (transformerless) with specified jitter-generation. On the receiver side, jitter-tolerance and bit error rate performance is attained. A cable equalizer supports 13.7 dB loss (Nyquist-frequency) and has an eye-closure less than 600 psec. The device uses one master-clock (155 MHz) and a DLL for both TX and RX synchronization. Targeted crosstalk isolation performance is achieved with a 0.35 /spl mu/m BiCMOS technology. The TQFP48 IC powered from 3.3 V consumes 390 mW.
{"title":"A single chip 155 Mbps/140 Mbps SDH/PDH transceiver","authors":"J. Guinea, L. Tomasini, Santo Maggio, Massimiliano Rutar","doi":"10.1109/CICC.2000.852675","DOIUrl":"https://doi.org/10.1109/CICC.2000.852675","url":null,"abstract":"The 155 Mbps (STM-l electrical) transceiver complies with the relevant ITU-T recommendations. The transmit channel features CMI transmission (transformerless) with specified jitter-generation. On the receiver side, jitter-tolerance and bit error rate performance is attained. A cable equalizer supports 13.7 dB loss (Nyquist-frequency) and has an eye-closure less than 600 psec. The device uses one master-clock (155 MHz) and a DLL for both TX and RX synchronization. Targeted crosstalk isolation performance is achieved with a 0.35 /spl mu/m BiCMOS technology. The TQFP48 IC powered from 3.3 V consumes 390 mW.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"137 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75505452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852642
Alain-Serge Porret, T. Melly, D. Python, C. Enz, E. Vittoz
A broad range of new high-volume consumer applications require the availability of low-power, battery operated, wireless microsystems and sensors. For such applications, a fully integrated receiver based on a direct conversion architecture was designed and realized in a standard 0.5 /spl mu/m digital CMOS process with 0.6 V threshold voltage. It uses FSK modulation in the 434 MHz ISM band, and operates with only 1 V supply, allowing it to be powered by a single battery cell. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s and an ultralow power consumption of only 1 mW.
{"title":"A 1 V, 1 mW, 434 MHz FSK receiver fully integrated in a standard digital CMOS process","authors":"Alain-Serge Porret, T. Melly, D. Python, C. Enz, E. Vittoz","doi":"10.1109/CICC.2000.852642","DOIUrl":"https://doi.org/10.1109/CICC.2000.852642","url":null,"abstract":"A broad range of new high-volume consumer applications require the availability of low-power, battery operated, wireless microsystems and sensors. For such applications, a fully integrated receiver based on a direct conversion architecture was designed and realized in a standard 0.5 /spl mu/m digital CMOS process with 0.6 V threshold voltage. It uses FSK modulation in the 434 MHz ISM band, and operates with only 1 V supply, allowing it to be powered by a single battery cell. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s and an ultralow power consumption of only 1 mW.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"10 1","pages":"171-174"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75588596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852639
Steven K. Knapp, D. Tavana
Time to market pressures, increasing system complexity, and smaller process geometries, are creating a market vacuum that will be increasingly addressed by an important emerging category of devices: the Configurable System-on-Chip (CsoC). These application specific programmable parts (ASPP) are single chip combinations of microprocessors, memory, dedicated peripheral functions, and embedded programmable logic. They provide unprecedented time-to-market benefits and field customization for the electronic systems of this upcoming decade. Integration of microprocessors, memory, peripherals, and programmable logic is made possible with a new bus architecture called the Configurable System Interconnect Bus (CSI). The Configurable System Interconnect Bus was specifically designed to facilitate re-use, guarantee timing, increase system throughput, and reduce system debug time in applications that require intense time-to-market and field upgrade.
{"title":"Field configurable system-on-chip device architecture","authors":"Steven K. Knapp, D. Tavana","doi":"10.1109/CICC.2000.852639","DOIUrl":"https://doi.org/10.1109/CICC.2000.852639","url":null,"abstract":"Time to market pressures, increasing system complexity, and smaller process geometries, are creating a market vacuum that will be increasingly addressed by an important emerging category of devices: the Configurable System-on-Chip (CsoC). These application specific programmable parts (ASPP) are single chip combinations of microprocessors, memory, dedicated peripheral functions, and embedded programmable logic. They provide unprecedented time-to-market benefits and field customization for the electronic systems of this upcoming decade. Integration of microprocessors, memory, peripherals, and programmable logic is made possible with a new bus architecture called the Configurable System Interconnect Bus (CSI). The Configurable System Interconnect Bus was specifically designed to facilitate re-use, guarantee timing, increase system throughput, and reduce system debug time in applications that require intense time-to-market and field upgrade.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"6 1","pages":"155-158"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75654487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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