Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852723
A. Ranjit, P. Ramkumar, V. Noel
This paper addresses the need to develop firm intellectual properties (IPs) with a standard set of deliverables so they can be integrated with very little effort. We have presented the design flow used for developing a firm IP. A DMA controller is used as an example. The paper highlights the deliverables from a IP vendor/user perspective to proliferate the acceptance and usage of the IP.
{"title":"Firm IP development: methodology and deliverables","authors":"A. Ranjit, P. Ramkumar, V. Noel","doi":"10.1109/CICC.2000.852723","DOIUrl":"https://doi.org/10.1109/CICC.2000.852723","url":null,"abstract":"This paper addresses the need to develop firm intellectual properties (IPs) with a standard set of deliverables so they can be integrated with very little effort. We have presented the design flow used for developing a firm IP. A DMA controller is used as an example. The paper highlights the deliverables from a IP vendor/user perspective to proliferate the acceptance and usage of the IP.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"80 1","pages":"529-532"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83846464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852629
C. Ouyang, Kyungsuk Ryu, H. Heineken, Jitu Khare, S. Shaikh, M. d'Abreu
In this paper, a wire planning strategy at the layout stage is proposed. The strategy addresses deep sub-micron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitivity to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.
{"title":"Wire planning for performance and yield enhancement","authors":"C. Ouyang, Kyungsuk Ryu, H. Heineken, Jitu Khare, S. Shaikh, M. d'Abreu","doi":"10.1109/CICC.2000.852629","DOIUrl":"https://doi.org/10.1109/CICC.2000.852629","url":null,"abstract":"In this paper, a wire planning strategy at the layout stage is proposed. The strategy addresses deep sub-micron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitivity to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"61 1","pages":"113-116"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86004330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852623
M. Hafed, G. Roberts
An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.
{"title":"A stand-alone integrated excitation/extraction system for analog BIST applications","authors":"M. Hafed, G. Roberts","doi":"10.1109/CICC.2000.852623","DOIUrl":"https://doi.org/10.1109/CICC.2000.852623","url":null,"abstract":"An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"10 1","pages":"83-86"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79202249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852678
N. Kanekawa, Y. Kojima, S. Yukutake, M. Nemoto, T. Iwasaki, Kazuhisa Takami, Y. Takeuchi, Atsuko Yano, Yasuo Shima
This paper presents an isolated analog front-end (I-AFE) LSI with built-in isolation function for V.90, 56 kbps modems. The LSI has 1.5 kVrms. AC isolation and analog front-end functions within a 5 mm/spl times/4.5 mm die with 0.4 /spl mu/m SOI CMOS process and a 50 pin TSOP package. The on-chip isolation approach eliminates external isolation devices such as transformers or photo-couplers. A 100 Mbps transmission rate is attained by the on-chip isolator.
{"title":"An analog front-end LSI with on-chip isolator for V.90 56 kbps modems","authors":"N. Kanekawa, Y. Kojima, S. Yukutake, M. Nemoto, T. Iwasaki, Kazuhisa Takami, Y. Takeuchi, Atsuko Yano, Yasuo Shima","doi":"10.1109/CICC.2000.852678","DOIUrl":"https://doi.org/10.1109/CICC.2000.852678","url":null,"abstract":"This paper presents an isolated analog front-end (I-AFE) LSI with built-in isolation function for V.90, 56 kbps modems. The LSI has 1.5 kVrms. AC isolation and analog front-end functions within a 5 mm/spl times/4.5 mm die with 0.4 /spl mu/m SOI CMOS process and a 50 pin TSOP package. The on-chip isolation approach eliminates external isolation devices such as transformers or photo-couplers. A 100 Mbps transmission rate is attained by the on-chip isolator.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"60 1","pages":"327-330"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82341058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852680
F. Huang, K. O. Kenneth
A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-dB insertion loss and a 17-dBm P/sub 1dB/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 dB compression point is achieved by DC biasing the input and output nodes.
{"title":"A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-/spl mu/m CMOS process","authors":"F. Huang, K. O. Kenneth","doi":"10.1109/CICC.2000.852680","DOIUrl":"https://doi.org/10.1109/CICC.2000.852680","url":null,"abstract":"A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-dB insertion loss and a 17-dBm P/sub 1dB/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 dB compression point is achieved by DC biasing the input and output nodes.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"78 1","pages":"341-344"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82362301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852637
Tarachand Pagarani, F. Kocan, D. Saab, J. Abraham
In this paper, we present different architectures and implementation for solving the general SATisfiability (SAT) problem on reconfigurable devices. In particular, we address the solution of this basic and important problem using multiple small FPGAs. Our approach utilizes partitioning and decomposition to map any large SAT problem on more than one small FPGA. First, a SAT problem is decomposed into several independent sub-problems. This way, all sub-problems may be solved on different FPGAs simultaneously. If any of the sub-problems can not fit on a single FPGA, then a second technique is used to divide the sub-problem into dependent parts. We compute the solution time and hardware resources for both approaches and also compare our results with the previously published results.
{"title":"Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA","authors":"Tarachand Pagarani, F. Kocan, D. Saab, J. Abraham","doi":"10.1109/CICC.2000.852637","DOIUrl":"https://doi.org/10.1109/CICC.2000.852637","url":null,"abstract":"In this paper, we present different architectures and implementation for solving the general SATisfiability (SAT) problem on reconfigurable devices. In particular, we address the solution of this basic and important problem using multiple small FPGAs. Our approach utilizes partitioning and decomposition to map any large SAT problem on more than one small FPGA. First, a SAT problem is decomposed into several independent sub-problems. This way, all sub-problems may be solved on different FPGAs simultaneously. If any of the sub-problems can not fit on a single FPGA, then a second technique is used to divide the sub-problem into dependent parts. We compute the solution time and hardware resources for both approaches and also compare our results with the previously published results.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"56 1","pages":"147-150"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87836098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852670
D. Malone, Paul Bunce, Joe DellaPietro, John Davis, J. Dawson, T. Knips, D. Plass, Phil Pritzlaff, Kenneth Reyer
This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (a) SRAM operability in product-like clocking and ABIST environments, (b) Demonstration of yield using 2 dimensional redundancy, (c) Characterization of SRAM signals used in the macro timing rules, (d) Obtain high volume pre-product manufacturing test data, (e) Verify SRAM functionality at technology stress test conditions.
{"title":"Design validation of .18 /spl mu/m 1 GHz cache and register arrays","authors":"D. Malone, Paul Bunce, Joe DellaPietro, John Davis, J. Dawson, T. Knips, D. Plass, Phil Pritzlaff, Kenneth Reyer","doi":"10.1109/CICC.2000.852670","DOIUrl":"https://doi.org/10.1109/CICC.2000.852670","url":null,"abstract":"This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (a) SRAM operability in product-like clocking and ABIST environments, (b) Demonstration of yield using 2 dimensional redundancy, (c) Characterization of SRAM signals used in the macro timing rules, (d) Obtain high volume pre-product manufacturing test data, (e) Verify SRAM functionality at technology stress test conditions.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"57 1","pages":"295-298"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77762789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852660
R. Taft, M. R. Tursi
A 100-MSPS 8-bit ADC obtains very low supply voltage operation with four circuit techniques: differential T-gate boosting, a unified coarse/fine analog channel with dual gain, a supply independent delay generator, and a delay-lock loop digital output driver. A maximum DNL below 0.5 LSB and 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained down to 2.2 V, 84 mW.
{"title":"A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V","authors":"R. Taft, M. R. Tursi","doi":"10.1109/CICC.2000.852660","DOIUrl":"https://doi.org/10.1109/CICC.2000.852660","url":null,"abstract":"A 100-MSPS 8-bit ADC obtains very low supply voltage operation with four circuit techniques: differential T-gate boosting, a unified coarse/fine analog channel with dual gain, a supply independent delay generator, and a delay-lock loop digital output driver. A maximum DNL below 0.5 LSB and 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained down to 2.2 V, 84 mW.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"103 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75931702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852688
David J. Foley, M. Flynn
This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85/spl deg/C. The circuits were fabricated on a generic 0.5 /spl mu/m digital CMOS process.
{"title":"CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator","authors":"David J. Foley, M. Flynn","doi":"10.1109/CICC.2000.852688","DOIUrl":"https://doi.org/10.1109/CICC.2000.852688","url":null,"abstract":"This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85/spl deg/C. The circuits were fabricated on a generic 0.5 /spl mu/m digital CMOS process.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"15 1","pages":"371-374"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73281692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852638
K. Furuta, T. Fujii, M. Motomura, K. Wakabayashi, M. Yamashina
We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power /spl mu/P in both performance and energy consumption. We believe DRLE's scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs.
{"title":"Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI","authors":"K. Furuta, T. Fujii, M. Motomura, K. Wakabayashi, M. Yamashina","doi":"10.1109/CICC.2000.852638","DOIUrl":"https://doi.org/10.1109/CICC.2000.852638","url":null,"abstract":"We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power /spl mu/P in both performance and energy consumption. We believe DRLE's scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"1 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73667125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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