Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852633
Jason P. Clifford, S. Wilton
Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.
{"title":"Architecture of cluster-based FPGAs with memory","authors":"Jason P. Clifford, S. Wilton","doi":"10.1109/CICC.2000.852633","DOIUrl":"https://doi.org/10.1109/CICC.2000.852633","url":null,"abstract":"Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"17 1","pages":"131-134"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74731221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852733
F. Herzel, Heide Erzgraeber, N. Ilkov
We describe a new approach to fully integrated CMOS LC-oscillators with very large tuning range. An experimental oscillator is tunable from 1.34 GHz to 2.14 GHz. The standard deviation of the oscillation period due to thermal device noise is below 250 ppm. Potential applications include wideband RF systems and clock generation in microprocessors.
{"title":"A new approach to fully integrated CMOS LC-oscillators with a very large tuning range","authors":"F. Herzel, Heide Erzgraeber, N. Ilkov","doi":"10.1109/CICC.2000.852733","DOIUrl":"https://doi.org/10.1109/CICC.2000.852733","url":null,"abstract":"We describe a new approach to fully integrated CMOS LC-oscillators with very large tuning range. An experimental oscillator is tunable from 1.34 GHz to 2.14 GHz. The standard deviation of the oscillation period due to thermal device noise is below 250 ppm. Potential applications include wideband RF systems and clock generation in microprocessors.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"3 1","pages":"573-576"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79087608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852613
Y. Fujimoto, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz
A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of /spl Delta//spl Sigma/ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-/spl mu/m double-metal double-poly CMOS process, the chip occupies 2.28 mm/sup 2/ and dissipates 3.7 mW with a supply voltage of 2 V.
{"title":"A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator","authors":"Y. Fujimoto, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz","doi":"10.1109/CICC.2000.852613","DOIUrl":"https://doi.org/10.1109/CICC.2000.852613","url":null,"abstract":"A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of /spl Delta//spl Sigma/ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-/spl mu/m double-metal double-poly CMOS process, the chip occupies 2.28 mm/sup 2/ and dissipates 3.7 mW with a supply voltage of 2 V.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"72 1","pages":"35-38"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89837369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852653
L. Bolcioni, R. Guerrieri
The design flow and implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation, on a programmable architecture, of a compression algorithm capable of encoding up to 15 black & white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The system has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25 /spl mu/m, 6-metal standard-cell CMOS technology and works at 40 MHz, 2.5 V power supply. The adoption of IP reusable cores has allowed the system to be completed in 1 man-year time from idea to physical implementation.
{"title":"A low-power system-on-chip for the documentation of road accidents","authors":"L. Bolcioni, R. Guerrieri","doi":"10.1109/CICC.2000.852653","DOIUrl":"https://doi.org/10.1109/CICC.2000.852653","url":null,"abstract":"The design flow and implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation, on a programmable architecture, of a compression algorithm capable of encoding up to 15 black & white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The system has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25 /spl mu/m, 6-metal standard-cell CMOS technology and works at 40 MHz, 2.5 V power supply. The adoption of IP reusable cores has allowed the system to be completed in 1 man-year time from idea to physical implementation.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"7 1","pages":"223-226"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91030747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852711
T. Kamemaru, H. Ohira, H. Suzuki, K. Asano, M. Yoshimoto, Tokumichi Murakami
We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively.
{"title":"Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video","authors":"T. Kamemaru, H. Ohira, H. Suzuki, K. Asano, M. Yoshimoto, Tokumichi Murakami","doi":"10.1109/CICC.2000.852711","DOIUrl":"https://doi.org/10.1109/CICC.2000.852711","url":null,"abstract":"We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"69 1","pages":"473-476"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85062300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852655
S. Kozu, T. Aramaki, C. Ikeda, Yasuaki Kuroda, S. Kawanago, Mitsuji Okada, H. Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii
In this paper, an access network controller for ADSL (asymmetric digital subscriber line) is described. It consists of a VR4120 MPU core, a system controller, an Ethernet controller, an ATM (asynchronous transfer mode) cell processor, a USB (universal serial bus interface) controller, and other blocks. This controller, along with ADSL PHY devices, can provide a total solution for ADSL modem and ADSL router.
{"title":"A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home","authors":"S. Kozu, T. Aramaki, C. Ikeda, Yasuaki Kuroda, S. Kawanago, Mitsuji Okada, H. Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii","doi":"10.1109/CICC.2000.852655","DOIUrl":"https://doi.org/10.1109/CICC.2000.852655","url":null,"abstract":"In this paper, an access network controller for ADSL (asymmetric digital subscriber line) is described. It consists of a VR4120 MPU core, a system controller, an Ethernet controller, an ATM (asynchronous transfer mode) cell processor, a USB (universal serial bus interface) controller, and other blocks. This controller, along with ADSL PHY devices, can provide a total solution for ADSL modem and ADSL router.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"1 1","pages":"231-234"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84897419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852650
O. C. Gouveia-Filho, A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro
This paper introduces the advanced compact MOSFET (ACM) model, a physically based model of the MOS transistor, derived from the long-channel transistor model presented by Cunha et al. (1998). The ACM model is composed of very simple expressions, is valid for any inversion level, conserves charge and preserves the source-drain symmetry of the transistor. Short-channel effects are included using a compact and physical approach. The performance of the ACM model in benchmark tests demonstrates its suitability for circuit simulation.
{"title":"Advanced compact model for short-channel MOS transistors","authors":"O. C. Gouveia-Filho, A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/CICC.2000.852650","DOIUrl":"https://doi.org/10.1109/CICC.2000.852650","url":null,"abstract":"This paper introduces the advanced compact MOSFET (ACM) model, a physically based model of the MOS transistor, derived from the long-channel transistor model presented by Cunha et al. (1998). The ACM model is composed of very simple expressions, is valid for any inversion level, conserves charge and preserves the source-drain symmetry of the transistor. Short-channel effects are included using a compact and physical approach. The performance of the ACM model in benchmark tests demonstrates its suitability for circuit simulation.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"19 1","pages":"209-212"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84215550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852730
Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, I. Park
This paper describes a single-chip high definition television (HDTV) decoder which performs system parsing, video decoding, audio decoding and resolution conversion. To process a huge amount of data and deal with various standards in the decoder, a multi-thread processor architecture is proposed to minimize the overhead cycles of task-switching. The features of parallelism and conditional branches in MPEG2 video decoding algorithm are considered to enhance the performance of the embedded processor and to reduce the size of code memory. Experimental results show that the proposed processor architecture is 5.3 times faster than a scalar processor at the cost of negligible increase of code memory.
{"title":"Multi-thread VLIW processor architecture for HDTV decoding","authors":"Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, I. Park","doi":"10.1109/CICC.2000.852730","DOIUrl":"https://doi.org/10.1109/CICC.2000.852730","url":null,"abstract":"This paper describes a single-chip high definition television (HDTV) decoder which performs system parsing, video decoding, audio decoding and resolution conversion. To process a huge amount of data and deal with various standards in the decoder, a multi-thread processor architecture is proposed to minimize the overhead cycles of task-switching. The features of parallelism and conditional branches in MPEG2 video decoding algorithm are considered to enhance the performance of the embedded processor and to reduce the size of code memory. Experimental results show that the proposed processor architecture is 5.3 times faster than a scalar processor at the cost of negligible increase of code memory.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"16 1","pages":"559-562"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77486072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852718
Yonghee Im, K. Roy
Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. Those goals have been accomplished mainly by deep sub-micron technology along with voltage scaling. However, scaling down feature size causes larger interwire capacitance which is responsible for large crosstalk between concerned interconnects. We are currently facing signal integrity problems never experienced before, such that accurate function predictability of circuits under certain input conditions may be questionable, not to mention performance and power dissipation predictability. In this paper we suggest a novel predictable circuit architecture, named optimized overlaying array based architecture (O/sup 2/ABA), especially suited for the deep sub-micron regime. O/sup 2/ABA achieves reduction of crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of unit cell leads to high regularity, which makes the performance predictable even before layout, and shortens time-to-design. O/sup 2/ABA is compared with other design styles, such as custom design, PLA and Weinberger array, to show its advantages.
{"title":"A novel high-performance predictable circuit architecture for the deep sub-micron era","authors":"Yonghee Im, K. Roy","doi":"10.1109/CICC.2000.852718","DOIUrl":"https://doi.org/10.1109/CICC.2000.852718","url":null,"abstract":"Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. Those goals have been accomplished mainly by deep sub-micron technology along with voltage scaling. However, scaling down feature size causes larger interwire capacitance which is responsible for large crosstalk between concerned interconnects. We are currently facing signal integrity problems never experienced before, such that accurate function predictability of circuits under certain input conditions may be questionable, not to mention performance and power dissipation predictability. In this paper we suggest a novel predictable circuit architecture, named optimized overlaying array based architecture (O/sup 2/ABA), especially suited for the deep sub-micron regime. O/sup 2/ABA achieves reduction of crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of unit cell leads to high regularity, which makes the performance predictable even before layout, and shortens time-to-design. O/sup 2/ABA is compared with other design styles, such as custom design, PLA and Weinberger array, to show its advantages.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"26 1","pages":"503-506"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78089551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852705
Lin Wu, Huawen Jin, W. Black
This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.
{"title":"Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems","authors":"Lin Wu, Huawen Jin, W. Black","doi":"10.1109/CICC.2000.852705","DOIUrl":"https://doi.org/10.1109/CICC.2000.852705","url":null,"abstract":"This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"120 1","pages":"447-450"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74653889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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