Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012761
B. D. Smedt, G. Gielen
Through the use of multi-objective genetic optimization and radial basis functions fitting, a novel method has been developed which presents to the designer the hypersurface of Pareto-optimal design points. For the first time it is now possible to characterize the design space boundaries of a circuit topology over a broad range of design specifications, all within transistor-level accuracy. This technique is illustrated with the presentation of the design space for two different types of circuits: a Miller-compensated operational transconductance amplifier, and an LC-tank voltage-controlled oscillator.
{"title":"WATSON: a multi-objective design space exploration tool for analog and RF IC design","authors":"B. D. Smedt, G. Gielen","doi":"10.1109/CICC.2002.1012761","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012761","url":null,"abstract":"Through the use of multi-objective genetic optimization and radial basis functions fitting, a novel method has been developed which presents to the designer the hypersurface of Pareto-optimal design points. For the first time it is now possible to characterize the design space boundaries of a circuit topology over a broad range of design specifications, all within transistor-level accuracy. This technique is illustrated with the presentation of the design space for two different types of circuits: a Miller-compensated operational transconductance amplifier, and an LC-tank voltage-controlled oscillator.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012882
S. Lung, D. Lin, S. S. Chen, G. Weng, C. L. Liu, S. Lai, C. Tsai, T. B. Wu, Ru-Gun Liu
Embedded FeRAM module is achieved by a low temperature capacitor-over-interconnect (COI) process. A conductive perovskite LaNiO/sub 3/ (LNO) bottom electrode is used as seed layer, the crystallization temperature of in-situ sputter deposited PZT is greatly reduced from 600/spl deg/C to 350 /spl deg/C/spl sim/400/spl deg/C LNO's near-perfect lattice match with PZT allows PZT to growth epitaxially at low temperature. When LNO is used as top electrode of the ferroelectric capacitor, the fatigue performance is greatly improved. The COI LNO/PZT/LNO FeRAM structure achieved by this low temperature process is completely modular and is ideal for advanced Cu/low-K SOC application.
{"title":"Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application","authors":"S. Lung, D. Lin, S. S. Chen, G. Weng, C. L. Liu, S. Lai, C. Tsai, T. B. Wu, Ru-Gun Liu","doi":"10.1109/CICC.2002.1012882","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012882","url":null,"abstract":"Embedded FeRAM module is achieved by a low temperature capacitor-over-interconnect (COI) process. A conductive perovskite LaNiO/sub 3/ (LNO) bottom electrode is used as seed layer, the crystallization temperature of in-situ sputter deposited PZT is greatly reduced from 600/spl deg/C to 350 /spl deg/C/spl sim/400/spl deg/C LNO's near-perfect lattice match with PZT allows PZT to growth epitaxially at low temperature. When LNO is used as top electrode of the ferroelectric capacitor, the fatigue performance is greatly improved. The COI LNO/PZT/LNO FeRAM structure achieved by this low temperature process is completely modular and is ideal for advanced Cu/low-K SOC application.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114069726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012811
L. Portmann, H. Ballan, M. Declercq
The design of a 5 Volts fully integrated magnetic sensor able to operate up to 270/spl deg/C is presented. Fabricated in a Partially Depleted (PD) 1 /spl mu/m SOI process, this monolithic sensor comprises a resistive Hall plate, an amplifier stage and an A/D converter delivering a temperature stabilized 8-bit digital readout of the magnetic field. This circuit uses analog techniques for continuous compensation of temperature. Design issues inherent to partially depleted SOI, as well as constraints due to high temperature, are discussed.
{"title":"SOI Hall effect sensor operating up to 270/spl deg/C","authors":"L. Portmann, H. Ballan, M. Declercq","doi":"10.1109/CICC.2002.1012811","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012811","url":null,"abstract":"The design of a 5 Volts fully integrated magnetic sensor able to operate up to 270/spl deg/C is presented. Fabricated in a Partially Depleted (PD) 1 /spl mu/m SOI process, this monolithic sensor comprises a resistive Hall plate, an amplifier stage and an A/D converter delivering a temperature stabilized 8-bit digital readout of the magnetic field. This circuit uses analog techniques for continuous compensation of temperature. Design issues inherent to partially depleted SOI, as well as constraints due to high temperature, are discussed.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114084875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012786
Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa
"Burst mode" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.
{"title":"Burst mode: a new acceleration mode for 128-bit block ciphers","authors":"Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa","doi":"10.1109/CICC.2002.1012786","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012786","url":null,"abstract":"\"Burst mode\" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121763319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012833
J. Ramos, M. Steyaert
A CMOS opamp that can drive large capacitive loads is presented. The technique employs a positive feedback compensation (PFC) to improve frequency response as compared to nested Miller compensation (NMC), allowing the circuit to occupy less silicon area and straightforward design. At 1.5 V, the circuit dissipates 275 /spl mu/W, has more than 100 dB gain, a gain bandwidth of 2.7 MHz and 1.0 V//spl mu/s average slew rate while driving a 130 pF load.
{"title":"Three stage amplifier with positive feedback compensation scheme","authors":"J. Ramos, M. Steyaert","doi":"10.1109/CICC.2002.1012833","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012833","url":null,"abstract":"A CMOS opamp that can drive large capacitive loads is presented. The technique employs a positive feedback compensation (PFC) to improve frequency response as compared to nested Miller compensation (NMC), allowing the circuit to occupy less silicon area and straightforward design. At 1.5 V, the circuit dissipates 275 /spl mu/W, has more than 100 dB gain, a gain bandwidth of 2.7 MHz and 1.0 V//spl mu/s average slew rate while driving a 130 pF load.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132806758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012857
J. Chang, S. Ravi, A. Raghunathan
Crossbar based switching fabrics form a critical component of many modern high-performance electronic systems, including network routers and switches, multi-processor computing systems, and high-end application-specific integrated circuits (ASICs). This paper describes a simple, yet effective, hardware modification to enhance the performance and utilization of a generic crossbar. The proposed structure, called FLEXBAR, is based on the addition of lightweight, configurable, input and output hardware layers that exploit unutilized switching paths to provide additional data transfer capability for highly loaded paths. FLEXBAR has been implemented and evaluated as a network switch fabric. Extensive system simulations under various traffic scenarios indicate that latency reduces by up to 70%, and peak throughput of highly loaded ports can increase by over 100%. A full-custom design of FLEXBAR in 0.35 micron technology requires marginal area and performance overheads (4.47% and 8.23%, respectively, for a typical configuration) compared to a conventional crossbar.
{"title":"FLEXBAR: A crossbar switching fabric with improved performance and utilization","authors":"J. Chang, S. Ravi, A. Raghunathan","doi":"10.1109/CICC.2002.1012857","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012857","url":null,"abstract":"Crossbar based switching fabrics form a critical component of many modern high-performance electronic systems, including network routers and switches, multi-processor computing systems, and high-end application-specific integrated circuits (ASICs). This paper describes a simple, yet effective, hardware modification to enhance the performance and utilization of a generic crossbar. The proposed structure, called FLEXBAR, is based on the addition of lightweight, configurable, input and output hardware layers that exploit unutilized switching paths to provide additional data transfer capability for highly loaded paths. FLEXBAR has been implemented and evaluated as a network switch fabric. Extensive system simulations under various traffic scenarios indicate that latency reduces by up to 70%, and peak throughput of highly loaded ports can increase by over 100%. A full-custom design of FLEXBAR in 0.35 micron technology requires marginal area and performance overheads (4.47% and 8.23%, respectively, for a typical configuration) compared to a conventional crossbar.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131690498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012823
Bernhard Birkl, B. Hooser, M. Janssens, F. Lenke, Vlado Vorisek
This paper describes the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip. Due to a very tight development cycle we decided to use state of the art methodology for integration, verification, and design for test (DFT) in order to minimize risk and problem areas. The combination of a top-down integration flow, strong focus on constraint driven timing analysis, a modular simulation environment, and leading edge DFT solutions led to an implementation cycle of only 8 weeks. The chip is realized in an 0.18 /spl mu/m technology using 5 layers of metal, achieving a final die size of 16 mm/sup 2/. The central processor runs at a minimal speed of 140 MHz.
{"title":"Design integration, DFT, and verification methodology for an MPEG 1/2 audio layer 3 (MP3) SoC device","authors":"Bernhard Birkl, B. Hooser, M. Janssens, F. Lenke, Vlado Vorisek","doi":"10.1109/CICC.2002.1012823","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012823","url":null,"abstract":"This paper describes the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip. Due to a very tight development cycle we decided to use state of the art methodology for integration, verification, and design for test (DFT) in order to minimize risk and problem areas. The combination of a top-down integration flow, strong focus on constraint driven timing analysis, a modular simulation environment, and leading edge DFT solutions led to an implementation cycle of only 8 weeks. The chip is realized in an 0.18 /spl mu/m technology using 5 layers of metal, achieving a final die size of 16 mm/sup 2/. The central processor runs at a minimal speed of 140 MHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130746403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012861
D. Cassan, J. Long
A low-noise amplifier employing transformer feedback for 5-6 GHz WLAN applications operates from a 1 V supply and achieves a measured gain of 14.2 dB, noise figure (NF) of 0.9 dB, and IIP3 of +0.9 dBm, while consuming 16 mW. We benchmark the feedback design to a cascode topology fabricated in the same technology that realizes 14.1 dB gain, 1.8 dB NF, and IIP3 of +4.2 dBm while dissipating 21.6 mW at 1.8 V. Both designs are fully-differential and are implemented in 0.18 /spl mu/m CMOS.
{"title":"A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 /spl mu/m CMOS","authors":"D. Cassan, J. Long","doi":"10.1109/CICC.2002.1012861","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012861","url":null,"abstract":"A low-noise amplifier employing transformer feedback for 5-6 GHz WLAN applications operates from a 1 V supply and achieves a measured gain of 14.2 dB, noise figure (NF) of 0.9 dB, and IIP3 of +0.9 dBm, while consuming 16 mW. We benchmark the feedback design to a cascode topology fabricated in the same technology that realizes 14.1 dB gain, 1.8 dB NF, and IIP3 of +4.2 dBm while dissipating 21.6 mW at 1.8 V. Both designs are fully-differential and are implemented in 0.18 /spl mu/m CMOS.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An NECoBus (internal code name), a bus architecture designed for creating portable yet high-throughput SOCs, is described. Its distinguishing feature is a wrapper-based NECoBus Core Interface (NCI) mechanism: an IP core is designed to communicate with another through the NCI, where the NECoBus includes wrappers to hide bus protocols and the wiring delay from the IP core. Importantly, the NECoBus wrapper employs several latency reduction techniques that can effectively remove the latency penalty induced in the conventional wrapper-based bus design: (1) retry encapsulation, (2) write-buffer switching, (3) early bus request and (4) converter-based multiple bit-width connection. The first implementation of the 32/64 bit NECoBus that has been targeted at a 200-MHz bus cycle using the 0.13-/spl mu/m CMOS processes is described in this paper. Evaluation results demonstrate a 16% throughput improvement, and a 15% and 40% read/write latency reduction by those newly developed techniques.
{"title":"NECoBus: a high-end SOC bus with a portable and low-latency wrapper-based interface mechanism","authors":"K. Anjo, Atsushi Okamura, Tomoharu Kajiwarat, Noriko Mizushima, Masafumi Omori, Yasuaki Kuroda","doi":"10.1109/CICC.2002.1012827","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012827","url":null,"abstract":"An NECoBus (internal code name), a bus architecture designed for creating portable yet high-throughput SOCs, is described. Its distinguishing feature is a wrapper-based NECoBus Core Interface (NCI) mechanism: an IP core is designed to communicate with another through the NCI, where the NECoBus includes wrappers to hide bus protocols and the wiring delay from the IP core. Importantly, the NECoBus wrapper employs several latency reduction techniques that can effectively remove the latency penalty induced in the conventional wrapper-based bus design: (1) retry encapsulation, (2) write-buffer switching, (3) early bus request and (4) converter-based multiple bit-width connection. The first implementation of the 32/64 bit NECoBus that has been targeted at a 200-MHz bus cycle using the 0.13-/spl mu/m CMOS processes is described in this paper. Evaluation results demonstrate a 16% throughput improvement, and a 15% and 40% read/write latency reduction by those newly developed techniques.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114449228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012757
M. Borgatti, F. Lertora, B. Forêt, L. Cali
A system-chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA. Application-specific bus-mapped coprocessors and flexible I/O peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customisation. The silicon area required by the system is 20 mm/sup 2/ in a 0.18 /spl mu/m CMOS technology. The embedded FPGA accounts for about 40% of the system area.
{"title":"A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O","authors":"M. Borgatti, F. Lertora, B. Forêt, L. Cali","doi":"10.1109/CICC.2002.1012757","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012757","url":null,"abstract":"A system-chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA. Application-specific bus-mapped coprocessors and flexible I/O peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customisation. The silicon area required by the system is 20 mm/sup 2/ in a 0.18 /spl mu/m CMOS technology. The embedded FPGA accounts for about 40% of the system area.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129889177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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