Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012791
H. Cloetens, R. Hahn, B. Hooser, F. Lenke
The system design and the chip implementation aspects of an MPEG1/2 audio layer 3 (MP3) decoder chip suitable for Compact Disc (CD) based systems is discussed. A new innovative chip architecture is presented which addresses the low-power requirements of portable applications. This utilizes an optimum split between control processing tasks and signal processing code. The architecture was implemented using a synthesizable System-on-a-Chip approach. The chip has been fabricated in 0.18 /spl mu/m CMOS technology. The silicon area is 16 mm/sup 2/ and operates at a minimum of 140 MHz, achieving up to 80 hours of playtime. This low-power approach outperforms other commercially available solutions.
讨论了一种适用于CD系统的MPEG1/2音频三层(MP3)解码器芯片的系统设计和芯片实现。提出了一种新颖的芯片结构，以满足便携式应用的低功耗要求。这利用了控制处理任务和信号处理代码之间的最佳分割。该体系结构采用可合成的片上系统方法实现。该芯片采用0.18 /spl μ m CMOS工艺制造。硅面积为16 mm/sup 2/，工作频率最低为140 MHz，可实现长达80小时的播放时间。这种低功耗方法优于其他商业上可用的解决方案。
{"title":"A low-power highly-integrated MPEG1/2 audio layer 3 (MP3) decoder for CD-based systems","authors":"H. Cloetens, R. Hahn, B. Hooser, F. Lenke","doi":"10.1109/CICC.2002.1012791","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012791","url":null,"abstract":"The system design and the chip implementation aspects of an MPEG1/2 audio layer 3 (MP3) decoder chip suitable for Compact Disc (CD) based systems is discussed. A new innovative chip architecture is presented which addresses the low-power requirements of portable applications. This utilizes an optimum split between control processing tasks and signal processing code. The architecture was implemented using a synthesizable System-on-a-Chip approach. The chip has been fabricated in 0.18 /spl mu/m CMOS technology. The silicon area is 16 mm/sup 2/ and operates at a minimum of 140 MHz, achieving up to 80 hours of playtime. This low-power approach outperforms other commercially available solutions.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"21 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130783944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012760
L. Lemaitre, C. McAndrew, Steve J. Hamm
This paper presents ADMS, a new open-source tool that supports automatic synthesis of compact models into circuit simulators. ADMS takes as input Verilog-AMS compact model descriptions and generates C code that conforms to circuit simulator interfaces. ADMS supports the simulators Mica, Spectre, and HSIM, and has been used to implement the SP and SSIM MOSFET models, the VBIC BJT model, and the R3 resistor model, the last two including self-heating.
{"title":"ADMS-automatic device model synthesizer","authors":"L. Lemaitre, C. McAndrew, Steve J. Hamm","doi":"10.1109/CICC.2002.1012760","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012760","url":null,"abstract":"This paper presents ADMS, a new open-source tool that supports automatic synthesis of compact models into circuit simulators. ADMS takes as input Verilog-AMS compact model descriptions and generates C code that conforms to circuit simulator interfaces. ADMS supports the simulators Mica, Spectre, and HSIM, and has been used to implement the SP and SSIM MOSFET models, the VBIC BJT model, and the R3 resistor model, the last two including self-heating.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124545556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012794
José B. Silva, Xuesheng Wang, P. Kiss, U. Moon, G. Temes
Two digital techniques are described in this tutorial, both aimed at improving the accuracy of delta-sigma data converters. The first one corrects adaptively for mismatch errors in a MASH ADC, while the other acquires and then corrects for the nonlinearity of the internal multibit DAC used in the ADC.
{"title":"Digital techniques for improved /spl Delta//spl Sigma/ data conversion","authors":"José B. Silva, Xuesheng Wang, P. Kiss, U. Moon, G. Temes","doi":"10.1109/CICC.2002.1012794","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012794","url":null,"abstract":"Two digital techniques are described in this tutorial, both aimed at improving the accuracy of delta-sigma data converters. The first one corrects adaptively for mismatch errors in a MASH ADC, while the other acquires and then corrects for the nonlinearity of the internal multibit DAC used in the ADC.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124199072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012892
A. Dounavis, R. Achar, M. Nakhla
This paper presents a closed-form passive time-domain macromodeling algorithm for multiport distributed RC interconnect networks. The method offers an efficient means to discretize RC distributed interconnects compared to the conventional lumped discretization while preserving the passivity of the macromodel. In the proposed method, coefficients describing the discrete time-domain macromodel are computed using closed-form matrix rational approximation of exponential matrices and can be computed a priori. The proposed model is suitable for inclusion in general purpose circuit simulators such as SPICE and overcomes the mixed frequency/time simulation difficulties encountered during transient analysis.
{"title":"Passive closed-form time-domain macromodels for on-chip distributed RC interconnects","authors":"A. Dounavis, R. Achar, M. Nakhla","doi":"10.1109/CICC.2002.1012892","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012892","url":null,"abstract":"This paper presents a closed-form passive time-domain macromodeling algorithm for multiport distributed RC interconnect networks. The method offers an efficient means to discretize RC distributed interconnects compared to the conventional lumped discretization while preserving the passivity of the macromodel. In the proposed method, coefficients describing the discrete time-domain macromodel are computed using closed-form matrix rational approximation of exponential matrices and can be computed a priori. The proposed model is suitable for inclusion in general purpose circuit simulators such as SPICE and overcomes the mixed frequency/time simulation difficulties encountered during transient analysis.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132948241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012793
T. Salo, S. Lindfors, K. Halonen
A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.
{"title":"An 80 MHz 8th-order bandpass /spl Delta//spl Sigma/-modulator with a 75 dB SNDR for IS-95","authors":"T. Salo, S. Lindfors, K. Halonen","doi":"10.1109/CICC.2002.1012793","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012793","url":null,"abstract":"A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125083527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012780
Byung‐Do Yang, L. Kim
A new ROM compression method for continuous data is proposed. The proposed method is based on two proposed algorithms. The first one is a region select ROM compression algorithm which stores only regions including data after dividing data into many small regions by magnitude and address. The second is a quantization ROM and error ROM compression algorithm which divides data into quantized data and their errors. Using these algorithms, 40/spl sim/60% ROM size reductions are achieved for various continuous data.
{"title":"A ROM compression method for continuous data","authors":"Byung‐Do Yang, L. Kim","doi":"10.1109/CICC.2002.1012780","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012780","url":null,"abstract":"A new ROM compression method for continuous data is proposed. The proposed method is based on two proposed algorithms. The first one is a region select ROM compression algorithm which stores only regions including data after dividing data into many small regions by magnitude and address. The second is a quantization ROM and error ROM compression algorithm which divides data into quantized data and their errors. Using these algorithms, 40/spl sim/60% ROM size reductions are achieved for various continuous data.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115671280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012817
R. Frye, S. Kapur, R. Melville
We have derived a lumped-element circuit from its coupled line counterpart for a 90/spl deg/, 3dB hybrid coupler. We discuss the uses, design, and characteristics of such circuits in CMOS technology. We show measured characteristics of an example 50/spl Omega/, 2GHz coupler with 65dB of image rejection, 18dB of directivity and a 4.7dB noise figure.
{"title":"A 2GHz quadrature hybrid implemented in CMOS technology","authors":"R. Frye, S. Kapur, R. Melville","doi":"10.1109/CICC.2002.1012817","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012817","url":null,"abstract":"We have derived a lumped-element circuit from its coupled line counterpart for a 90/spl deg/, 3dB hybrid coupler. We discuss the uses, design, and characteristics of such circuits in CMOS technology. We show measured characteristics of an example 50/spl Omega/, 2GHz coupler with 65dB of image rejection, 18dB of directivity and a 4.7dB noise figure.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127213124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012759
Krishnasis Chakraborty, D. Long, J. Fishburn, K. Singhal, Lun Ye, C. Ortiz
Buffer insertion can be used very successfully for mitigation of crosstalk noise while simultaneously optimizing the effect of the insertion on the path delay. A vast majority of nets with crosstalk problems can be fixed by adding only a few buffers. This causes negligible place-and-route perturbations and allows for a convergent noise-loop closure methodology. This paper presents a novel algorithm for combining signal-integrity analysis with buffer insertion for noise and delay optimization after place-and-route.
{"title":"A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization","authors":"Krishnasis Chakraborty, D. Long, J. Fishburn, K. Singhal, Lun Ye, C. Ortiz","doi":"10.1109/CICC.2002.1012759","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012759","url":null,"abstract":"Buffer insertion can be used very successfully for mitigation of crosstalk noise while simultaneously optimizing the effect of the insertion on the path delay. A vast majority of nets with crosstalk problems can be fixed by adding only a few buffers. This causes negligible place-and-route perturbations and allows for a convergent noise-loop closure methodology. This paper presents a novel algorithm for combining signal-integrity analysis with buffer insertion for noise and delay optimization after place-and-route.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"486 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012767
H. Schmit, David Whelihan, Andrew Tsai, M. Moe, B. Levine, R. Taylor
PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.
{"title":"PipeRench: A virtualized programmable datapath in 0.18 micron technology","authors":"H. Schmit, David Whelihan, Andrew Tsai, M. Moe, B. Levine, R. Taylor","doi":"10.1109/CICC.2002.1012767","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012767","url":null,"abstract":"PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114622842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012889
M. Nagata, T. Morie, A. Iwata
A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in the time domain. The simulation of a 0.25-/spl mu/m z80 microcontroller with 62.5-MHz clock frequency costs less than 10 sec per a clock cycle including the model generation. Simulated substrate noise compares well with 200-ps 100-/spl mu/V resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows a peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.
{"title":"Modeling substrate noise generation in CMOS digital integrated circuits","authors":"M. Nagata, T. Morie, A. Iwata","doi":"10.1109/CICC.2002.1012889","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012889","url":null,"abstract":"A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in the time domain. The simulation of a 0.25-/spl mu/m z80 microcontroller with 62.5-MHz clock frequency costs less than 10 sec per a clock cycle including the model generation. Simulated substrate noise compares well with 200-ps 100-/spl mu/V resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows a peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131517933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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