M. Koch, M. Russew, Ludwig Scharfenberg, A. Benker, A. Schleunitz, G. Grützner
Hybrid Polymers are a material class established in the industry for manufacturing of high-performance optical components, mainly patterned by (nano)imprint processes. Recently, the application range of Hybrid Polymers has been extended into bonding and passivation. In this context, patterning by classical UV-lithography has come into focus as an alternative patterning method to (nano)imprinting. By applying a two-stage curing process with a high intensity, low dose patterning step and a high dose flood exposure after development, it is possible to realize previously unattainable resolutions limits for Hybrid Polymers of 6μm L/S and aspect ratios of more than 3.
{"title":"Advancing high resolution photolithography with hybrid polymers for wafer-scale manufacture of micro-optics and patterned passivation layers","authors":"M. Koch, M. Russew, Ludwig Scharfenberg, A. Benker, A. Schleunitz, G. Grützner","doi":"10.1117/12.2658408","DOIUrl":"https://doi.org/10.1117/12.2658408","url":null,"abstract":"Hybrid Polymers are a material class established in the industry for manufacturing of high-performance optical components, mainly patterned by (nano)imprint processes. Recently, the application range of Hybrid Polymers has been extended into bonding and passivation. In this context, patterning by classical UV-lithography has come into focus as an alternative patterning method to (nano)imprinting. By applying a two-stage curing process with a high intensity, low dose patterning step and a high dose flood exposure after development, it is possible to realize previously unattainable resolutions limits for Hybrid Polymers of 6μm L/S and aspect ratios of more than 3.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"12497 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Laulagnet, Jacques-Alexandre Dallery, L. Pain, M. May, Béatrice Hémard, Franck Garlet, I. Servin, C. Sabbione
Electron Beam Direct Write (EBDW or E-Beam) Lithography is a worldwide reference technology used in laboratories, universities and pilot line facilities for Research and Developments. Due to its low writing speed, E-Beam direct write has never been recognized as an acceptable industrial solution, exception made for optical mask manufacturing. Nevertheless, its natural high-resolution capability allows low-cost patterning of advanced or innovative devices ahead of their high-volume manufacturing ramp-up. Thanks to its full versatility with almost all type of chemically amplified resists, EBDW is a perfect complementary solution to optical lithography. This paper demonstrates the compatibility of EBDW lithography with advanced Negative Tone Development (NTD) resist and the possibility to set-up an hybrid E-Beam/193i lithography process flow with high performances in terms of resolution and mix & match overlay. This high-end lithography strategy alliance offers flexibility and cost advantages for device development R&D but also powerful possibilities for specific applications such circuit encryption as discussed at the end of this work-study.
{"title":"E-beam direct write lithography: the versatile ally of optical lithography","authors":"F. Laulagnet, Jacques-Alexandre Dallery, L. Pain, M. May, Béatrice Hémard, Franck Garlet, I. Servin, C. Sabbione","doi":"10.1117/12.2658273","DOIUrl":"https://doi.org/10.1117/12.2658273","url":null,"abstract":"Electron Beam Direct Write (EBDW or E-Beam) Lithography is a worldwide reference technology used in laboratories, universities and pilot line facilities for Research and Developments. Due to its low writing speed, E-Beam direct write has never been recognized as an acceptable industrial solution, exception made for optical mask manufacturing. Nevertheless, its natural high-resolution capability allows low-cost patterning of advanced or innovative devices ahead of their high-volume manufacturing ramp-up. Thanks to its full versatility with almost all type of chemically amplified resists, EBDW is a perfect complementary solution to optical lithography. This paper demonstrates the compatibility of EBDW lithography with advanced Negative Tone Development (NTD) resist and the possibility to set-up an hybrid E-Beam/193i lithography process flow with high performances in terms of resolution and mix & match overlay. This high-end lithography strategy alliance offers flexibility and cost advantages for device development R&D but also powerful possibilities for specific applications such circuit encryption as discussed at the end of this work-study.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In 2019, finally, extreme ultraviolet (EUV) lithography has been applied to high volume manufacturing (HVM). However, the performance of EUV resist materials are still not enough for the expected HVM requirements, even by using the latest qualifying EUV resist materials. The critical issues are the stochastic issues, which will become ‘defectivity’. The analyzing summary of the stochastic factors in EUV lithography was reported, which described 2 (two) major stochastic issues, which are ‘Photon stochastic’ and ‘Chemical stochastic’. In the past, speaking of the stochastic issue was basically considered from low photon number from EUV light source, which means ‘photon shot noise’. It was still critical concerning point, even with recent progress on source power improvement. However, the stochastic issue is not only from them but also from EUV materials and processes, called ‘Chemical stochastic’. The ‘Chemical stochastic’ means caused from resist materials and processes for lithography, materials uniformity in the film, reactive uniformity in the film, and dissolving behavior with the developer. In this paper, we will focus on ‘Chemical stochastic’ improvement, especially, the dissolving behavior by using negative-tone imaging (NTI, using organic solvent-based developer) with EUV exposure (EUV-NTI). EUV-NTI had a potential for improving ‘Chemical stochastic’ because of their properties, which were low swelling and smooth dissolving behavior. However, the pattern collapse was easily observed for preparing fine patterns with the standard developer. Newly proposed novel formulated organic solvent-based developer will be expected to improve the patter collapse issue and ‘Chemical stochastic’. Lithographic performance will also be reported.
{"title":"A novel formulated developer for negative-tone imaging with EUV exposure to improve chemical stochastic","authors":"Keiyu Ou, Naohiro Tango, Nishiki Fujimaki, Kazuhiro Marumo, Nobuhiro Hiura, Satomi Takahashi, Toru Fujimori","doi":"10.1117/12.2657421","DOIUrl":"https://doi.org/10.1117/12.2657421","url":null,"abstract":"In 2019, finally, extreme ultraviolet (EUV) lithography has been applied to high volume manufacturing (HVM). However, the performance of EUV resist materials are still not enough for the expected HVM requirements, even by using the latest qualifying EUV resist materials. The critical issues are the stochastic issues, which will become ‘defectivity’. The analyzing summary of the stochastic factors in EUV lithography was reported, which described 2 (two) major stochastic issues, which are ‘Photon stochastic’ and ‘Chemical stochastic’. In the past, speaking of the stochastic issue was basically considered from low photon number from EUV light source, which means ‘photon shot noise’. It was still critical concerning point, even with recent progress on source power improvement. However, the stochastic issue is not only from them but also from EUV materials and processes, called ‘Chemical stochastic’. The ‘Chemical stochastic’ means caused from resist materials and processes for lithography, materials uniformity in the film, reactive uniformity in the film, and dissolving behavior with the developer. In this paper, we will focus on ‘Chemical stochastic’ improvement, especially, the dissolving behavior by using negative-tone imaging (NTI, using organic solvent-based developer) with EUV exposure (EUV-NTI). EUV-NTI had a potential for improving ‘Chemical stochastic’ because of their properties, which were low swelling and smooth dissolving behavior. However, the pattern collapse was easily observed for preparing fine patterns with the standard developer. Newly proposed novel formulated organic solvent-based developer will be expected to improve the patter collapse issue and ‘Chemical stochastic’. Lithographic performance will also be reported.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123343449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.
{"title":"Enabling process technologies for advanced logic devices beyond FinFET era","authors":"Tomonari Yamamoto","doi":"10.1117/12.2660290","DOIUrl":"https://doi.org/10.1117/12.2660290","url":null,"abstract":"This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128707276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Maskless grayscale lithography is a key technology to create structured surfaces in photoresist, especially for micro-optic applications. It uses spatially modulated light intensity to expose a layer of low-contrast positive resist. A digital design that contains gray values or height information, corresponding to a certain target depth in the photoresist, can conveniently be exposed with a DWL 66+ from Heidelberg Instruments. Processes are well known for thicknesses up to 60 μm. The possibility to fabricate taller structures, are of great interest in the micro-fabrication world. Two experimental and one commercial resists have been compared to reach and exceed the 100 μm symbolic height. After a validating experiment in a single coated layer of an experimental DNQ-based photoresist, we doubled and tripled the coating cycles at relatively low velocity and quickly obtained promising results. The triple-coated film while enabling the possibility to fabricate structures 100 μm high showed some sort of delamination in the deepest region of the layer, close to the substrate’s surface. The delamination indicates the formation of N2 bubbles, a disadvantage of DNQ-based photoresists that release nitrogen when exposed to light. Experiments with a commercially available resist seems to show similar behavior for thicknesses above 80 μm. Recent experiments using a second experimental resist, from a different supplier, showed some promising results: structures slightly higher than 100 μm without visible defect caused by nitrogen have been fabricated. Another advantage is that overall dose required to reach this depth was significantly lower than in the previous test.
{"title":"Ultra-thick positive photoresist layers for maskless grayscale lithography","authors":"Dominique Collé, G. Ekindorf","doi":"10.1117/12.2658355","DOIUrl":"https://doi.org/10.1117/12.2658355","url":null,"abstract":"Maskless grayscale lithography is a key technology to create structured surfaces in photoresist, especially for micro-optic applications. It uses spatially modulated light intensity to expose a layer of low-contrast positive resist. A digital design that contains gray values or height information, corresponding to a certain target depth in the photoresist, can conveniently be exposed with a DWL 66+ from Heidelberg Instruments. Processes are well known for thicknesses up to 60 μm. The possibility to fabricate taller structures, are of great interest in the micro-fabrication world. Two experimental and one commercial resists have been compared to reach and exceed the 100 μm symbolic height. After a validating experiment in a single coated layer of an experimental DNQ-based photoresist, we doubled and tripled the coating cycles at relatively low velocity and quickly obtained promising results. The triple-coated film while enabling the possibility to fabricate structures 100 μm high showed some sort of delamination in the deepest region of the layer, close to the substrate’s surface. The delamination indicates the formation of N2 bubbles, a disadvantage of DNQ-based photoresists that release nitrogen when exposed to light. Experiments with a commercially available resist seems to show similar behavior for thicknesses above 80 μm. Recent experiments using a second experimental resist, from a different supplier, showed some promising results: structures slightly higher than 100 μm without visible defect caused by nitrogen have been fabricated. Another advantage is that overall dose required to reach this depth was significantly lower than in the previous test.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"60 29","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120929399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ashley Moore, Julia Modl, Zhong Li, Hung-Yang Chen, Chunwei Chen, A. Behrendt, Katharina Schmoelzer
Despite their long history in the electronics industry, copper metal layers remain important components as interconnection layers in IC fabrication due to their higher thermal and electrical conductivity as well as their higher electromigration resistance. Structuring the copper metal layer via wet chemical etching places demands on the photoresist mask, requiring resistance to harsh etch chemistry and good adhesion to the substrate to prevent delamination and defects. The photoresist formulation AZ® TD-2010 is a positive-tone, DNQ-based i-line photoresist that incorporates an additional surface-grafting component to deliver improved etch performance via enhanced photoresist adhesion on metal substrates. The in-situ priming of the photoresist formulation during the patterning process leads to a greater interfacial adhesion, resulting in steep sidewalls, with a greater than 20° increase in etch angle over formulations without adhesion promoter, while maintaining undercut depth and Cu CD. The AZ®TD-2010 photoresist can also be used at high thickness to cover topography steps formed from underlying layers, while also exhibiting high enough photospeed to maintain production throughput standards for IC manufacturing.
{"title":"Profile control in conductor metal wet etch with advanced photoresists","authors":"Ashley Moore, Julia Modl, Zhong Li, Hung-Yang Chen, Chunwei Chen, A. Behrendt, Katharina Schmoelzer","doi":"10.1117/12.2657687","DOIUrl":"https://doi.org/10.1117/12.2657687","url":null,"abstract":"Despite their long history in the electronics industry, copper metal layers remain important components as interconnection layers in IC fabrication due to their higher thermal and electrical conductivity as well as their higher electromigration resistance. Structuring the copper metal layer via wet chemical etching places demands on the photoresist mask, requiring resistance to harsh etch chemistry and good adhesion to the substrate to prevent delamination and defects. The photoresist formulation AZ® TD-2010 is a positive-tone, DNQ-based i-line photoresist that incorporates an additional surface-grafting component to deliver improved etch performance via enhanced photoresist adhesion on metal substrates. The in-situ priming of the photoresist formulation during the patterning process leads to a greater interfacial adhesion, resulting in steep sidewalls, with a greater than 20° increase in etch angle over formulations without adhesion promoter, while maintaining undercut depth and Cu CD. The AZ®TD-2010 photoresist can also be used at high thickness to cover topography steps formed from underlying layers, while also exhibiting high enough photospeed to maintain production throughput standards for IC manufacturing.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115073558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Aryal, Ravi Kiran Chityala, I. Stricklin, Sidhant Tiwari, A. Siddiqui, T. Busani
In this work, Lamb Wave Resonators (LWRs) based on 2 μm thin Y-cut LiNbO3 films have been fabricated using integrated fabrication process that defines IDTs (Inter Digital Transducers) on top surface and a partial Si cavity for a sacrificial layer on the bottom surface. We discuss the etch quality and its effects on the device's performance. For the first time, we present an optimized high-quality etched MEMS (Micro-electromechanical Systems) Resonator with smooth and vertical sidewalls on this material system, reporting the maximum Q-factor of 2500 at 846 MHz frequency. We observed that the resonator system has a Q-factor of 480 over the same frequency range when the etched surface has significant roughness and non-verticality. Q values of the device are greatly diminished by the presence of surface roughness and non-verticality of the etched edges. This truly highlights how important it is to have a high-quality etch profile for a piezoelectric material system like this so that the designed resonators can perform at their best.
{"title":"Realization of high-Q Lamb wave resonator with smooth vertical etching profile for thin film lithium niobate","authors":"A. Aryal, Ravi Kiran Chityala, I. Stricklin, Sidhant Tiwari, A. Siddiqui, T. Busani","doi":"10.1117/12.2665860","DOIUrl":"https://doi.org/10.1117/12.2665860","url":null,"abstract":"In this work, Lamb Wave Resonators (LWRs) based on 2 μm thin Y-cut LiNbO3 films have been fabricated using integrated fabrication process that defines IDTs (Inter Digital Transducers) on top surface and a partial Si cavity for a sacrificial layer on the bottom surface. We discuss the etch quality and its effects on the device's performance. For the first time, we present an optimized high-quality etched MEMS (Micro-electromechanical Systems) Resonator with smooth and vertical sidewalls on this material system, reporting the maximum Q-factor of 2500 at 846 MHz frequency. We observed that the resonator system has a Q-factor of 480 over the same frequency range when the etched surface has significant roughness and non-verticality. Q values of the device are greatly diminished by the presence of surface roughness and non-verticality of the etched edges. This truly highlights how important it is to have a high-quality etch profile for a piezoelectric material system like this so that the designed resonators can perform at their best.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"12497 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129599700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi
In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO2 dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO2 is developed. This patterning sequence consists of SiO2 etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)
{"title":"Middle-of-line plasma dry etch challenges for CFET integration","authors":"D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi","doi":"10.1117/12.2659095","DOIUrl":"https://doi.org/10.1117/12.2659095","url":null,"abstract":"In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO2 dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO2 is developed. This patterning sequence consists of SiO2 etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Reche, Api Warsono, Anaïs De Lehelle D'Affroux, Jonas Khan, S. Haumann, A. Kneidinger
Since its beginning in the 90’s NanoImprint Lithography (NIL) has been continuously improved to target the different industry requirements. Using an intermediate soft stamp media was one of the main improvements and has now become a standard technology. Based on that technology, EVG introduces a full wafer imprinting solution, whereas the size of the stamp corresponds to the size of the wafer to imprint. Results obtained at CEA-Leti using this solution, with respect to uniformity, sub-50nm resolution, repeatability, and high aspect ratio patterns, are today state of the art and allow NIL to be considered as an HVM technology. Nevertheless, further development is carried out on different aspects such as overlay (OVL) which is the scope of this work. Different contributors of OVL as translation, rotation but also distortion are dissociated and analyzed. Alignment repeatability is studied. Additionally, imprint to imprint OVL correction terms are applied. A dedicated methodology has been established and allows to obtain global OVL signature. According to the above, main process contributors are highlighted and studied in the paper to separate influence of each of them. Finally, different ways to improve overlay are discussed and some of them - which could be linked to hardware, process or both - are evaluated. Overall, the OVL status obtained and first improvements bring NIL technology closer to the alignment requirements of the industry.
{"title":"Overlay performances of wafer scale nanoimprint lithography","authors":"J. Reche, Api Warsono, Anaïs De Lehelle D'Affroux, Jonas Khan, S. Haumann, A. Kneidinger","doi":"10.1117/12.2655105","DOIUrl":"https://doi.org/10.1117/12.2655105","url":null,"abstract":"Since its beginning in the 90’s NanoImprint Lithography (NIL) has been continuously improved to target the different industry requirements. Using an intermediate soft stamp media was one of the main improvements and has now become a standard technology. Based on that technology, EVG introduces a full wafer imprinting solution, whereas the size of the stamp corresponds to the size of the wafer to imprint. Results obtained at CEA-Leti using this solution, with respect to uniformity, sub-50nm resolution, repeatability, and high aspect ratio patterns, are today state of the art and allow NIL to be considered as an HVM technology. Nevertheless, further development is carried out on different aspects such as overlay (OVL) which is the scope of this work. Different contributors of OVL as translation, rotation but also distortion are dissociated and analyzed. Alignment repeatability is studied. Additionally, imprint to imprint OVL correction terms are applied. A dedicated methodology has been established and allows to obtain global OVL signature. According to the above, main process contributors are highlighted and studied in the paper to separate influence of each of them. Finally, different ways to improve overlay are discussed and some of them - which could be linked to hardware, process or both - are evaluated. Overall, the OVL status obtained and first improvements bring NIL technology closer to the alignment requirements of the industry.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131971564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Park, E. Aqad, Yinjie Cen, S. Coley, Li Cui, Conner A. Hoelzel, Benjamin Naab, Choong-Bong Lee, Rochelle Rena, Philjae Kang, Y. Shin, David Limberg, Lei Zhang
Extreme ultraviolet (EUV) lithography technology empowers integrated circuit industry to mass produce chips with smaller pitches and higher density. Along with EUV tool advancement, significant progress has also been made in the development and advancement of EUV chemically amplified resist (CAR) materials, which allows for the improvement of resolution, line edge roughness, and sensitivity (RLS) trade-off. The scarce number of EUV photons has triggered the development of resist material with high absorption at 13.5 nm. However, a review of open literature reveals very limited reports on the effect of high EUV absorption elements on etch properties of advanced EUV resist. To ensure Moore’s Law continues to move forward, further resist performance improvement is required. In this regard, stochastic defects originating from photon shot noise, materials, and processing variabilities present a unique challenge for the extension of CAR platform for the patterning of smaller nodes. Notably, less attention has been paid to defects formed during the etching process used for pattern transfer. In this paper, we report on the relationship between resist make-up and etch properties. In particular, the effect of incorporation of EUV high absorbing elements are examined. New resist material design strategies for continuous improvement of EUV CAR lithographic performance will be discussed.
{"title":"Understanding etch properties of advanced chemically amplified EUV resist","authors":"J. Park, E. Aqad, Yinjie Cen, S. Coley, Li Cui, Conner A. Hoelzel, Benjamin Naab, Choong-Bong Lee, Rochelle Rena, Philjae Kang, Y. Shin, David Limberg, Lei Zhang","doi":"10.1117/12.2659178","DOIUrl":"https://doi.org/10.1117/12.2659178","url":null,"abstract":"Extreme ultraviolet (EUV) lithography technology empowers integrated circuit industry to mass produce chips with smaller pitches and higher density. Along with EUV tool advancement, significant progress has also been made in the development and advancement of EUV chemically amplified resist (CAR) materials, which allows for the improvement of resolution, line edge roughness, and sensitivity (RLS) trade-off. The scarce number of EUV photons has triggered the development of resist material with high absorption at 13.5 nm. However, a review of open literature reveals very limited reports on the effect of high EUV absorption elements on etch properties of advanced EUV resist. To ensure Moore’s Law continues to move forward, further resist performance improvement is required. In this regard, stochastic defects originating from photon shot noise, materials, and processing variabilities present a unique challenge for the extension of CAR platform for the patterning of smaller nodes. Notably, less attention has been paid to defects formed during the etching process used for pattern transfer. In this paper, we report on the relationship between resist make-up and etch properties. In particular, the effect of incorporation of EUV high absorbing elements are examined. New resist material design strategies for continuous improvement of EUV CAR lithographic performance will be discussed.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133199241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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