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Understanding etch properties of advanced chemically amplified EUV resist 了解先进化学放大EUV抗蚀剂的蚀刻性能
Pub Date : 2023-05-01 DOI: 10.1117/12.2659178
J. Park, E. Aqad, Yinjie Cen, S. Coley, Li Cui, Conner A. Hoelzel, Benjamin Naab, Choong-Bong Lee, Rochelle Rena, Philjae Kang, Y. Shin, David Limberg, Lei Zhang
Extreme ultraviolet (EUV) lithography technology empowers integrated circuit industry to mass produce chips with smaller pitches and higher density. Along with EUV tool advancement, significant progress has also been made in the development and advancement of EUV chemically amplified resist (CAR) materials, which allows for the improvement of resolution, line edge roughness, and sensitivity (RLS) trade-off. The scarce number of EUV photons has triggered the development of resist material with high absorption at 13.5 nm. However, a review of open literature reveals very limited reports on the effect of high EUV absorption elements on etch properties of advanced EUV resist. To ensure Moore’s Law continues to move forward, further resist performance improvement is required. In this regard, stochastic defects originating from photon shot noise, materials, and processing variabilities present a unique challenge for the extension of CAR platform for the patterning of smaller nodes. Notably, less attention has been paid to defects formed during the etching process used for pattern transfer. In this paper, we report on the relationship between resist make-up and etch properties. In particular, the effect of incorporation of EUV high absorbing elements are examined. New resist material design strategies for continuous improvement of EUV CAR lithographic performance will be discussed.
极紫外(EUV)光刻技术使集成电路工业能够批量生产具有更小间距和更高密度的芯片。随着EUV工具的进步,EUV化学放大抗蚀剂(CAR)材料的开发和进步也取得了重大进展,这使得分辨率、线边缘粗糙度和灵敏度(RLS)的权衡得到了改善。由于极紫外光光子的稀少,在13.5 nm处具有高吸收率的抗蚀剂材料得到了发展。然而,对公开文献的回顾显示,关于高EUV吸收元素对高级EUV抗蚀剂腐蚀性能影响的报道非常有限。为了确保摩尔定律继续向前发展,需要进一步改进抗蚀性能。在这方面,由光子噪声、材料和加工变化引起的随机缺陷对CAR平台的扩展提出了独特的挑战,以实现较小节点的图案化。值得注意的是,很少注意到在蚀刻过程中形成的缺陷用于图案转移。本文报道了抗蚀剂补色与蚀刻性能之间的关系。特别考察了加入EUV高吸收元素的影响。本文将讨论持续改善EUV CAR光刻性能的新型抗蚀剂设计策略。
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引用次数: 0
Middle-of-line plasma dry etch challenges for CFET integration 中线等离子体干蚀刻对CFET集成的挑战
Pub Date : 2023-05-01 DOI: 10.1117/12.2659095
D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi
In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO2 dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO2 is developed. This patterning sequence consists of SiO2 etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)
本文介绍了采用与缩放相关的测试载体(CPP48nm)进行单片cefet与纳米片器件集成的中线等离子体刻蚀的开发结果。解决了几个关键的MOL图像化步骤,重点是与底部和顶部器件接触的沟槽(M0)的图像化。在外延源漏极(S/D)上,M0A的图形由SiO2介电层和薄薄的SiN衬里蚀刻层组成。关键的M0蚀刻要求是保留SiN栅极间隔,以避免S/D和栅极之间的短路。由于在工艺流程中实现了无栅塞,因此蚀刻开发必须依赖于非常具有挑战性的小临界尺寸(CD)触点图案,以在金属触点和栅极之间创建足够的介电屏障,并且最好也是非常具有挑战性的是,自对准薄栅极垫片。利用EUV光刻条件的范围,对刻蚀深度的最大刻蚀深度作为刻蚀深度的函数进行了评估,得到了M0刻蚀深度与刻蚀深度的依赖关系。在刻蚀深度范围内,刻蚀深度在~ 13nm和~ 16nm范围内达到了最小刻蚀深度。观察到接触面CD增大的趋势导致更深的蚀刻和工艺均匀性的改善。当最上层M0 CD为bb0 ~ 20nm时,可实现大于100nm的刻蚀深度。开发了在M0 SiO2后进行SiN衬垫沉积,然后进行SiN衬垫蚀刻(间隔层形成)的选择。这个图案序列包括SiO2蚀刻停止在薄SiN上(超过S/D),然后是额外的SiN沉积,最后蚀刻沉积的SiN衬里以及覆盖S/D的SiN衬里。由于额外的SiN介电膜保护栅极,带有SiN间隔层形成的选项最大限度地降低了栅极短路的风险。此外,我们还介绍了另一个关键的MOL图图化步骤,即M0金属化后HAR金属凹槽(AR~11)的结果。
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引用次数: 0
Dissociative photoionization of EUV lithography photoresist models EUV光刻光刻胶模型的解离光电离
Pub Date : 2023-05-01 DOI: 10.1117/12.2657702
M. Gentile, M. Gerlach, R. Richter, M. V. van Setten, J. Petersen, P. van der Heide, F. Holzmeier
The dissociative photoionization of tert-butyl methyl methacrylate, a monomer unit found in many ESCAP resists, was investigated in a gas phase photoelectron photoion coincidence experiment employing extreme ultraviolet (EUV) synchrotron radiation at 13.5 nm. It was found that the interaction of EUV photons with the molecules leads almost exclusively to dissociation. However, the ionization can also directly deprotect the ester function, thus inducing the solubility switch wanted in a resist film. These results serve as a building block to reconstruct the full picture of the mechanism in widely used chemically amplified resist thin films, provide a knob to tailor more performant resist materials, and will aid interpreting advanced ultrafast time-resolved experiments.
采用极紫外光同步辐射13.5 nm气相光电子-光离子重合实验研究了甲基丙烯酸叔丁基甲基丙烯酸甲酯的解离光电离。研究发现,极紫外光子与分子的相互作用几乎完全导致解离。然而,电离也可以直接解除酯功能的保护,从而诱导抗蚀剂膜所需的溶解度开关。这些结果为重建广泛使用的化学放大抗蚀剂薄膜的完整机制提供了基础,为定制更高性能的抗蚀剂材料提供了一个契机,并将有助于解释先进的超快时间分辨实验。
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引用次数: 3
Metallic contamination reduction in polymer solution using membrane purification technology 膜净化技术减少聚合物溶液中的金属污染
Pub Date : 2023-05-01 DOI: 10.1117/12.2657698
P. Muralidhar, A. Ramirez, A. Wu, Lawrence Chen, Yamin Liu, Luxi Shen, Robert F. Blacksmith, Sabrina Wong, Matthew Melanson, A. Rudenko
As the patterning resolution of semiconductor manufacturing increases, so does the need to remove critical defects from the photochemical supply chain. In particular, metallic contaminants have been known to lead to various types of defects such as cone defects that contribute to significant yield loss 1. Hence, control of metallic contaminants is critical for these next generation lithography processes. Previous work has introduced the Purasol™ LS2 solvent purifier, capable of superior metal reduction in a wide range of photochemical solvents 2. Current work focuses on purification of polymer solutions, a key intermediate material in the photochemical ecosystem. We present data detailing the ability of the LS2 purifier to remove metals from a poly-(4-hydroxystyrene) (PHS) polymer solution. Purifier membrane in coupons as well as an LS2 purifier device are used in a series of experiments to investigate the metal removal efficiency in the polymer solution as a function of various experimental parameters. Metal removal is quantified using ICP-MS (inductively coupled plasma mass spectroscopy) measurements. In addition, we also present customer data demonstrating the effectiveness of the LS2 in purifying polymer solutions to reduce defects that degrade yield performance.
随着半导体制造的图形分辨率的提高,从光化学供应链中消除关键缺陷的需求也在增加。特别是,已知金属污染物会导致各种类型的缺陷,如锥体缺陷,从而导致显著的产量损失1。因此,控制金属污染物对这些下一代光刻工艺至关重要。先前的工作介绍了Purasol™LS2溶剂净化器,能够在各种光化学溶剂中进行卓越的金属还原2。目前的工作重点是光化学生态系统中关键的中间材料聚合物溶液的纯化。我们提供的数据详细说明了LS2净化器从聚(4-羟基苯乙烯)(PHS)聚合物溶液中去除金属的能力。通过一系列实验,研究了聚合物溶液中金属的去除效率与各种实验参数的关系。金属去除是用电感耦合等离子体质谱(电感耦合等离子体质谱)测量定量。此外,我们还提供了客户数据,证明了LS2在净化聚合物溶液中减少降低良率性能的缺陷的有效性。
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引用次数: 0
Thin underlayer materials for metal oxide resist patterning 金属氧化物抗图案化的薄底层材料
Pub Date : 2023-05-01 DOI: 10.1117/12.2657918
Satoshi Dei, Yuya Hayashi, S. Akita, Shuhei Yamada, K. Sakai, Tatsuya Kasai, Akitaka Nii, Ayaka Furusawa, K. Takada, T. Kaneko, Tomoaki Seko, Eiji Yoneda, Tatsuya Sakai
We introduce thin underlayer (UL) materials (<10 nm) for metal oxide resist (MOR) that can support the lithography performance requirements as well as compatible with conventional etching tool and etching process. Thin UL materials for MOR patterning applications required to have chemical moieties with specific functions and excellent physical properties to meet both lithography and etching performance requirements. We investigated the relationship between surface properties of thin UL materials and its effects on MOR sensitivity, pattern collapse, and defects. We also discussed plausible mechanism based on our experimental results. In addition, we have also confirmed the impact of high EUV absorption unit effect in UL materials on MOR sensitivity.
我们推出了用于金属氧化物抗蚀剂(MOR)的薄底层(UL)材料(<10 nm),可以满足光刻性能要求,并与传统的蚀刻工具和蚀刻工艺兼容。用于MOR图案应用的薄UL材料需要具有具有特定功能和优异物理性能的化学成分,以满足光刻和蚀刻性能要求。我们研究了薄UL材料的表面特性及其对MOR灵敏度、图案坍塌和缺陷的影响之间的关系。并根据实验结果讨论了可能的机理。此外,我们还证实了UL材料中高EUV吸收单元效应对MOR灵敏度的影响。
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引用次数: 0
Selective isotropic atomic-layer etching of thin films by using dry chemical removal tool 用干法化学去除工具对薄膜进行选择性各向同性原子层蚀刻
Pub Date : 2023-05-01 DOI: 10.1117/12.2664547
Kazunori Shinoda, Nobuya Miyoshi, Hiroyuki Kobayashi, M. Izawa, K. Ishikawa, M. Hori
There has been considerable interest in the development of isotropic atomic layer etching (ALE) for the conformal removal of thin films. Material selectivity is crucial for the development of isotropic ALE because the next generation of semiconductor devices will be constructed with miniaturized 3D structures using a variety of very thin films. We developed plasma-assisted thermal-cyclic ALE, which is a repetition of surface modification by plasma exposure and removal of the modified surface by infrared heating. We developed a 300-mm tool, namely, dry chemical removal (DCR), which is equipped with an inductively coupled plasma (ICP) source and infrared lamps, to facilitate rapid thermal desorption of the modified surface. An important feature of the plasma-assisted thermal-cyclic ALE is that it has more tuning knobs than that of conventional ALE because it uses two temperatures: a low temperature for surface modification and an elevated temperature for the removal of the modified surface. This paper presents the selective ALE of various materials, i.e., Si3N4, TiN, W, and SiGe using the developed tool. The mechanisms of the selectivity are divided into two categories: formation of an ammonium salt-based modified layer and selectivity control by adjusting the infrared heating time. This paper reviews the selective ALE mechanisms, focusing on the results of in situ analysis of surface reactions, and presents some of the latest findings.
各向同性原子层刻蚀(ALE)技术在薄膜保形去除中的应用引起了广泛的关注。材料选择性对于各向同性ALE的发展至关重要,因为下一代半导体器件将使用各种非常薄的薄膜构建小型化的3D结构。我们开发了等离子体辅助热循环ALE,这是通过等离子体暴露和红外加热去除修饰表面的重复表面修饰。我们开发了一种300毫米的工具,即干法化学去除(DCR),该工具配备了电感耦合等离子体(ICP)源和红外灯,以促进改性表面的快速热解吸。等离子体辅助热循环ALE的一个重要特点是,它比传统ALE有更多的调节旋钮,因为它使用两种温度:低温用于表面修饰,高温用于去除修饰表面。本文介绍了利用开发的工具对Si3N4、TiN、W和SiGe等多种材料的选择性ALE。选择性机理分为两类:铵盐基改性层的形成和通过调节红外加热时间控制选择性。本文综述了选择性ALE机制,重点介绍了表面反应的原位分析结果,并介绍了一些最新发现。
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引用次数: 0
Recent advances in EUV patterning in preparation towards high-NA EUV 高na极紫外制备技术的最新进展
Pub Date : 2023-05-01 DOI: 10.1117/12.2657432
S. Nagahara, Arnaud Dauendorffer, A. Thiam, Xiang Liu, Yuhei Kuwahara, C. Dinh, Soichiro Okada, S. Kawakami, H. Genjima, Noriaki Nagamine, M. Muramatsu, S. Shimura, A. Tsuboi, K. Nafus, Y. Feurprier, M. Demand, R. Ramaneti, P. Foubert, D. De Simone, Geert Vendenberghe
High-NA EUV lithography is currently under development to keep up with device node scaling with smaller feature sizes. In this paper, the most recent advances in EUV patterning using metal oxide resists (MOR) and chemically amplified resists (CAR) are discussed. A newly developed resist development method (ESPERT™) was examined on MOR with 24 nm pitch line and space (L/S) patterns and 32 nm pitch pillars for preparation of high-NA EUV patterning. The patterning results showed improved sensitivity and pattern collapse margin. CAR contact hole patterning at 28 nm pitch was also examined by stochastic lithography simulation. The simulation results indicate that resist film thickness needs to be optimized for target pitches.
高na极紫外光刻技术目前正在开发中,以跟上设备节点缩放的速度,实现更小的特征尺寸。本文讨论了金属氧化物抗蚀剂(MOR)和化学放大抗蚀剂(CAR)在EUV成像中的最新进展。研究了一种新的抗蚀剂显影方法(ESPERT™),采用24 nm间距线和间距(L/S)图和32 nm间距柱在MOR上制备高na EUV图。图案化结果显示灵敏度和图案化塌缩幅度均有提高。采用随机光刻模拟方法研究了28nm间距的CAR接触孔图案。仿真结果表明,抗蚀膜厚度需要根据目标节距进行优化。
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引用次数: 2
Fundamentals of EUV stack for improving patterning performance 提高图案化性能的EUV堆栈基础
Pub Date : 2023-05-01 DOI: 10.1117/12.2657056
Nanoka Miyahara, Soichiro Okada, Hiroyuki Fujii, S. Shimura
Extreme ultraviolet (EUV) lithography has already utilized for high volume manufacturing, and miniaturization by numerical aperture (NA) 0.33 is approaching to the limit. Pitch 24 nm line and space (L/S) resist patterns can be resolved with single exposure at even NA 0.33. However, etch transfer performance to underlayer materials is one of the issues. Especially, in narrow pitch case, it is very difficult to etch due to the lack of resist mask resistance. Therefore, resist pattern thickening process with optimized development process and underlayer state was studied and verified the pattern height impact at our past paper. As a result, it found that combination of the underlayer (UL) kinds and their status was one of the key points to lead high-quality patterns. In this paper, optimized stack structure narrow pitch pattern and lithography performance. As a result, in experiments toward High NA EUV, 24 nm pitch L/S pattern could be patterned (near smallest size by NA 0.33) by selecting the optimal ML/UL combination, and some defect free process windows were kept between defect cliffs.
极紫外(EUV)光刻技术已经被用于大批量生产,而数值孔径(NA) 0.33的微型化已经接近极限。即使在0.33的NA下,单次曝光也可以分辨出间距为24 nm的线和空间(L/S)电阻模式。然而,蚀刻转移性能到底层材料是一个问题。特别是在窄节距情况下,由于缺乏抗蚀掩膜阻力,刻蚀非常困难。因此,我们在过去的论文中研究了优化发展过程和底层状态的抗蚀图案增厚工艺,并验证了图案高度的影响。结果表明,底层(UL)类型的组合及其状态是引领高质量模式的关键之一。本文对叠层结构、窄间距图案和光刻性能进行了优化。结果表明,在高NA EUV实验中,通过选择最佳ML/UL组合可以得到24 nm间距的L/S图案(接近最小尺寸,NA为0.33),并且在缺陷峭壁之间保留了一些无缺陷的工艺窗口。
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引用次数: 1
Computational study of 3-dimensional photo lithography on limitations and possibility for novel structures 三维光刻技术的局限性和新结构的可能性的计算研究
Pub Date : 2023-05-01 DOI: 10.1117/12.2658128
Y. Hirai, Tomoaki Osumi, Toshiaki Tanaka, M. Yasuda, M. Sasago
3D photolithography has been proposed using a built-in lens mask (BILM), which can form an optical image at an arbitrary focal point without using a lens by reproducing the wavefront formed in space by the complex transmittance of a glass mask, a three-dimensional structure can be formed using the multiple focus function. In this method, the 3D structure is decomposed into multiple seed patterns, and the seed images are exposed as a batch. However, the mutual interference of diffracted light to form the seed patterns causes turbulence in the image formation state, necessitating an optimized design of the mask. In this study, we conducted basic verification experiments for 3D imaging, verified the multiple focus function, reviewed the seed design including automatic optimization of the seed placement in order to first realize 3D image formation and then complex 3D image formation and verify the possibility for typical 3-D structures.
提出了一种采用内置透镜掩模(BILM)的三维光刻技术,它可以在不使用透镜的情况下在任意焦点处形成光学图像,通过再现玻璃掩模的复杂透过率在空间中形成的波前,利用多聚焦功能形成三维结构。该方法将三维结构分解为多个种子图案,并将种子图像批量公开。然而,衍射光在形成种子图案时的相互干涉会引起成像状态的湍流,因此需要对掩模进行优化设计。在本研究中,我们进行了三维成像的基础验证实验,验证了多聚焦功能,回顾了种子设计,包括种子放置的自动优化,首先实现了三维成像,然后实现了复杂的三维成像,验证了典型三维结构的可能性。
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引用次数: 0
Establishment of new process technology for EUV lithography EUV光刻新工艺技术的建立
Pub Date : 2023-05-01 DOI: 10.1117/12.2657076
Yuhei Kuwahara, S. Kawakami, Kanzo Kato, Soichiro Okada, Y. Kamei, T. Onitsuka, T. Yamauchi, Nanoka Miyahara, C. Dinh, L. Huli, S. Shimura
Resolution, line edge roughness (LER) and sensitivity (RLS) and defectivity are the well-known critical issues of extreme ultraviolet (EUV) lithography. To break the RLS triangle, metal oxide resist (MOR) is a promising candidate. However, further improvement of MOR process is required for high volume manufacturing to maintain low defectivity. In this paper, conventional and new processes for MOR pitch 32 nm line and space (L/S) and 36 nm pillar patterns was investigated. This new process was able to perform good sensitivity without degrading roughness. In addition, further optimization for underlayer and developer process could mitigate pattern collapses. MOR treatment was evaluated as another technique for roughness improvement. At last, bottom scum defect would be reduced by new process.
分辨率,线边缘粗糙度(LER)和灵敏度(RLS)和缺陷是众所周知的极紫外光刻(EUV)的关键问题。为了打破RLS三角形,金属氧化物抗蚀剂(MOR)是一种很有前途的候选材料。然而,为了保持低缺品率,大批量生产需要进一步改进MOR工艺。本文研究了MOR间距32nm线间距(L/S)和36nm柱间距的传统工艺和新工艺。这种新工艺能够在不降低粗糙度的情况下实现良好的灵敏度。此外,进一步优化底层和开发过程可以减轻模式崩溃。MOR处理被评价为另一种改善粗糙度的技术。最后,采用新工艺可有效减少底浮渣缺陷。
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引用次数: 1
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Advanced Lithography
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