Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716583
Jiewen Fan, Ming Li, Xiaoyan Xu, Ru Huang
As a promising transistors beyond 22nm technology node, Silicon nanowire (Si NW) transistor has attracted a lot of attentions recently [1]-[4]. Due to its unique gate-all-around (GAA) structure, Si NW transistor provides enhanced gate controllability and reduced sub-threshold leakage. However, gate-induced drain leakage (GIDL) as another primary leakage mechanism is still challenging [5][6]. In addition, due to the lateral parasitic bipolar junction transistor (PBJT), GIDL can be further enhanced in floating body transistors including Si NW transistor [7]. Unfortunately, few work on the origin sources and mechanism of GIDL in Si NW transistors have been reported up to now. In this paper, we have successfully fabricated Si NW transistors of high driving current with diameter down to 10nm on SOI substrate. More serious GIDL at low |Vgs| in Si NW transistor is observed compared with planar devices, which results from the strong gate-controlled longitudinal band-to-band tunneling (L-BTBT) of Si NW transistor, rather than traditional vertical BTBT in planar device. The dependence of GIDL on geometry parameters is also evaluated for further optimization.
{"title":"New observation on gate-induced drain leakage in Silicon nanowire transistors with Epi-Free CMOS compatible technology on SOI substrate","authors":"Jiewen Fan, Ming Li, Xiaoyan Xu, Ru Huang","doi":"10.1109/S3S.2013.6716583","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716583","url":null,"abstract":"As a promising transistors beyond 22nm technology node, Silicon nanowire (Si NW) transistor has attracted a lot of attentions recently [1]-[4]. Due to its unique gate-all-around (GAA) structure, Si NW transistor provides enhanced gate controllability and reduced sub-threshold leakage. However, gate-induced drain leakage (GIDL) as another primary leakage mechanism is still challenging [5][6]. In addition, due to the lateral parasitic bipolar junction transistor (PBJT), GIDL can be further enhanced in floating body transistors including Si NW transistor [7]. Unfortunately, few work on the origin sources and mechanism of GIDL in Si NW transistors have been reported up to now. In this paper, we have successfully fabricated Si NW transistors of high driving current with diameter down to 10nm on SOI substrate. More serious GIDL at low |Vgs| in Si NW transistor is observed compared with planar devices, which results from the strong gate-controlled longitudinal band-to-band tunneling (L-BTBT) of Si NW transistor, rather than traditional vertical BTBT in planar device. The dependence of GIDL on geometry parameters is also evaluated for further optimization.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716519
M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, T. Hiramoto
We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of Au/SiO2 at a low temperature of 200°C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.
{"title":"Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding","authors":"M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, T. Hiramoto","doi":"10.1109/S3S.2013.6716519","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716519","url":null,"abstract":"We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of Au/SiO2 at a low temperature of 200°C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115680712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716533
J. Raskin
Systems-on-Chip (SoC) and Systems-in-Package (SiP) are the most feasible solutions to fulfil the requirements of the new communication systems [1]. Both solutions will lead to a fundamental change in the design of analogue front-end architectures. It requires a high performance technology with devices that provide complex digital functionalities and can easily achieve operating frequencies in the GHz range. Therefore, it appears that only the best submicron CMOS technologies could provide a feasible and cost-effective integration of the communication systems. SOI MOSFET technology has demonstrated its potentialities for high frequency reaching cut-off frequencies close to 500 GHz for nMOSFETs [2] and for harsh environments (high temperature, radiations). Partially depleted (PD) SOI is now massively serving the 45-nm digital market where it is seen as a low-cost - low-power alternative to bulk Si. Fully depleted (FD) devices are also widely spread as they outperform existing semiconductor technologies for extremely low power analogue applications [3]. For RF and SoC applications, SOI also presents the major advantage of providing high resistivity (HR) substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 kΩ-cm can easily be achieved and High Resistivity Silicon (HR-Si) is commonly foreseen as a promising substrate for radio frequency integrated circuits (RFIC) and mixed signal applications [4].
{"title":"Is high resistivity SOI wafer the substrate solution for RF System-on-Chip?","authors":"J. Raskin","doi":"10.1109/S3S.2013.6716533","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716533","url":null,"abstract":"Systems-on-Chip (SoC) and Systems-in-Package (SiP) are the most feasible solutions to fulfil the requirements of the new communication systems [1]. Both solutions will lead to a fundamental change in the design of analogue front-end architectures. It requires a high performance technology with devices that provide complex digital functionalities and can easily achieve operating frequencies in the GHz range. Therefore, it appears that only the best submicron CMOS technologies could provide a feasible and cost-effective integration of the communication systems. SOI MOSFET technology has demonstrated its potentialities for high frequency reaching cut-off frequencies close to 500 GHz for nMOSFETs [2] and for harsh environments (high temperature, radiations). Partially depleted (PD) SOI is now massively serving the 45-nm digital market where it is seen as a low-cost - low-power alternative to bulk Si. Fully depleted (FD) devices are also widely spread as they outperform existing semiconductor technologies for extremely low power analogue applications [3]. For RF and SoC applications, SOI also presents the major advantage of providing high resistivity (HR) substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 kΩ-cm can easily be achieved and High Resistivity Silicon (HR-Si) is commonly foreseen as a promising substrate for radio frequency integrated circuits (RFIC) and mixed signal applications [4].","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716528
T. Matthias, T. Uhrmann, V. Dragoi, P. Lindner
Vertical stacking of thin chips combined with Through-Silicon-Vias (TSVs) as interconnects is an attractive path to higher functional density of ICs. Different functional entities of a device are manufactured separately and later integrated by wafer bonding. This enables a modular device architecture and thus a modular manufacturing supply chain. Device manufacturers can focus on their core competence, e.g., designing and building the ASIC, and then add standardized modules, such as logic controllers or memory, from other manufacturers. Stacking dies enables the electrical performance of a system-on-chip, but it reduces the design time, complexity and cost significantly. Wafer bonding is a key manufacturing technology for 3D ICs. Fusion wafer bonding, which was initally developed for SOI wafer manufacturing is the most promising wafer stacking technology for 3D ICs.
{"title":"Opportunities in 3D substrate bonding","authors":"T. Matthias, T. Uhrmann, V. Dragoi, P. Lindner","doi":"10.1109/S3S.2013.6716528","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716528","url":null,"abstract":"Vertical stacking of thin chips combined with Through-Silicon-Vias (TSVs) as interconnects is an attractive path to higher functional density of ICs. Different functional entities of a device are manufactured separately and later integrated by wafer bonding. This enables a modular device architecture and thus a modular manufacturing supply chain. Device manufacturers can focus on their core competence, e.g., designing and building the ASIC, and then add standardized modules, such as logic controllers or memory, from other manufacturers. Stacking dies enables the electrical performance of a system-on-chip, but it reduces the design time, complexity and cost significantly. Wafer bonding is a key manufacturing technology for 3D ICs. Fusion wafer bonding, which was initally developed for SOI wafer manufacturing is the most promising wafer stacking technology for 3D ICs.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128241143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716552
Mingoo Seok, Zhe Cao
We investigate two important performance-enhancing techniques - pipelining and parallelism - in the context of ultra-low voltage digital circuits. The investigation at near and sub-Vt supply voltages shows that pipelining can provide a superior benefit in throughput and energy-efficiency across a wide range of near and sub-Vt supply voltages while parallelism can provide a less amount of benefits only if the utilization of the circuits is high. Based on this investigation, an FFT core has been designed employing (1) an extensive degree of pipelining and (2) the parallelism with maximal utilization in major building blocks. The developed core demonstrates a significant amount of improvement in energy-efficiency and throughput over the existing near/sub-Vt FFT demonstrations.
{"title":"Parallelism and pipelining in ultra low voltage digital circuits","authors":"Mingoo Seok, Zhe Cao","doi":"10.1109/S3S.2013.6716552","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716552","url":null,"abstract":"We investigate two important performance-enhancing techniques - pipelining and parallelism - in the context of ultra-low voltage digital circuits. The investigation at near and sub-Vt supply voltages shows that pipelining can provide a superior benefit in throughput and energy-efficiency across a wide range of near and sub-Vt supply voltages while parallelism can provide a less amount of benefits only if the utilization of the circuits is high. Based on this investigation, an FFT core has been designed employing (1) an extensive degree of pipelining and (2) the parallelism with maximal utilization in major building blocks. The developed core demonstrates a significant amount of improvement in energy-efficiency and throughput over the existing near/sub-Vt FFT demonstrations.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114029678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716516
Kang-wook Lee, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi
Recently, hetero-integrated system (3-D super chip) involving memory, processor, power ICs, sensor, and photonic circuits has attracted attention owing to its high performance, highspeed communication, multi-functionality, and low power consumption . However, heterointegration of devices with different functions has many technical challenges owing to various types of size, thickness, and substrate because they were fabricated by different technologies. In addition, current 3-D integration technologies have another challenge such as high manufacturing cost and long prototyping time to achieve 3-D super chip. To realize 3-D super-chip with low-cost, high flexibility, and rapid prototyping time, we proposed die-level 3-D hetero-integration technology with fine-size backside TSV. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die-level. To fabricate 3-D super chip, each functional chip should be thinned to 10-50μm thickness. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping, local deformation, and residual stress in the stacked die. In addition, the large CTE difference between Si substrate and Cu TSV and μ-bump is posing risks of undesired thermo-mechanical stress generation and Cu contamination. In this paper, we describe new 3-D heterointegration technology with backside TSV for realizing 3-D super chip with low-cost, high flexibility, and rapid prototyping time and address our attention on some of the most potent reliability issues such as thermo-mechanical stress, crystal defects, and Cu contamination introduced in 3-D integration processes.
{"title":"3D hetero-integration technology with backside TSV and reliability challenges","authors":"Kang-wook Lee, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi","doi":"10.1109/S3S.2013.6716516","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716516","url":null,"abstract":"Recently, hetero-integrated system (3-D super chip) involving memory, processor, power ICs, sensor, and photonic circuits has attracted attention owing to its high performance, highspeed communication, multi-functionality, and low power consumption . However, heterointegration of devices with different functions has many technical challenges owing to various types of size, thickness, and substrate because they were fabricated by different technologies. In addition, current 3-D integration technologies have another challenge such as high manufacturing cost and long prototyping time to achieve 3-D super chip. To realize 3-D super-chip with low-cost, high flexibility, and rapid prototyping time, we proposed die-level 3-D hetero-integration technology with fine-size backside TSV. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die-level. To fabricate 3-D super chip, each functional chip should be thinned to 10-50μm thickness. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping, local deformation, and residual stress in the stacked die. In addition, the large CTE difference between Si substrate and Cu TSV and μ-bump is posing risks of undesired thermo-mechanical stress generation and Cu contamination. In this paper, we describe new 3-D heterointegration technology with backside TSV for realizing 3-D super chip with low-cost, high flexibility, and rapid prototyping time and address our attention on some of the most potent reliability issues such as thermo-mechanical stress, crystal defects, and Cu contamination introduced in 3-D integration processes.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716566
Lihua Wu, Guoquan Zhang, Yan Zhao, Xiaowei Han, Bo Yang, Jianzhong Li, Jian Wang, Jiantou Gao, K. Zhao, Ning Li, Fang Yu, Zhong-li Liu
A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low power and radiation-tolerant FPGA circuit design.
{"title":"A low power and radiation-tolerant FPGA implemented in FD SOI process","authors":"Lihua Wu, Guoquan Zhang, Yan Zhao, Xiaowei Han, Bo Yang, Jianzhong Li, Jian Wang, Jiantou Gao, K. Zhao, Ning Li, Fang Yu, Zhong-li Liu","doi":"10.1109/S3S.2013.6716566","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716566","url":null,"abstract":"A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low power and radiation-tolerant FPGA circuit design.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123398843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716586
S. Morohashi, N. Sugii, T. Iwamatsu, S. Kamohara, Y. Kato, C. Pham, K. Ishibashi
Performance, leakage and Emin on 65-nm SOTB and bulk were compared. We evaluated ring oscillators for SOTB and bulk with the same layout pattern. It is shown that operation frequency can be controlled from 6MHz to 40MHz, leakage of sleep mode can be decreased by 3 orders of magnitude on SOTB. By applying adjustable body bias and supply voltage depending on frequency, energy of 50k gates CMOS logic circuit can be minimized to be 4.4pJ/Hz, which corresponds to 44μW at 10MHz. Leakage of the logic gates can be reduced at 4.2nA at sleep mode.
{"title":"A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control","authors":"S. Morohashi, N. Sugii, T. Iwamatsu, S. Kamohara, Y. Kato, C. Pham, K. Ishibashi","doi":"10.1109/S3S.2013.6716586","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716586","url":null,"abstract":"Performance, leakage and Emin on 65-nm SOTB and bulk were compared. We evaluated ring oscillators for SOTB and bulk with the same layout pattern. It is shown that operation frequency can be controlled from 6MHz to 40MHz, leakage of sleep mode can be decreased by 3 orders of magnitude on SOTB. By applying adjustable body bias and supply voltage depending on frequency, energy of 50k gates CMOS logic circuit can be minimized to be 4.4pJ/Hz, which corresponds to 44μW at 10MHz. Leakage of the logic gates can be reduced at 4.2nA at sleep mode.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114870773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716580
G. Suraci, B. Giraud, T. Benoist, A. Makosiej, O. Thomas
This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port SRAM row decoder show 16% and 57% propagation delay reduction at 1V and 0.5V, respectively. The gain obtained at RVT design standby power is enabled by the wide range N-Well back biasing.
{"title":"SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI","authors":"G. Suraci, B. Giraud, T. Benoist, A. Makosiej, O. Thomas","doi":"10.1109/S3S.2013.6716580","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716580","url":null,"abstract":"This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port SRAM row decoder show 16% and 57% propagation delay reduction at 1V and 0.5V, respectively. The gain obtained at RVT design standby power is enabled by the wide range N-Well back biasing.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128162837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716569
R. Doria, R. Trevisoli, M. de Souza, M. Pavanello
This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (junctionless nanowire transistors) of several L. It is shown that, at a fixed input bias VA, HD2 degrades with the raise of L due to lower the effect of RS and at a targeted V0, HD2 improves with L increase owing to the larger AV resulting from the smaller channel length modulation.
{"title":"Harmonic distortion analysis of short channel junctionless nanowire transistors operating as amplifiers","authors":"R. Doria, R. Trevisoli, M. de Souza, M. Pavanello","doi":"10.1109/S3S.2013.6716569","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716569","url":null,"abstract":"This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (junctionless nanowire transistors) of several L. It is shown that, at a fixed input bias V<sub>A</sub>, HD2 degrades with the raise of L due to lower the effect of R<sub>S</sub> and at a targeted V<sub>0</sub>, HD2 improves with L increase owing to the larger A<sub>V</sub> resulting from the smaller channel length modulation.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128073026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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