Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716548
B. Pelloux-Prayer, Milovan Blagojevic, S. Haendler, A. Valentian, A. Amara, P. Flatresse
UTBB FD-SOI technology is able to reach very high speeds thanks to flip-Wells variant which enables low-VT (LVT) tuning. This approach appears to be the best design option to catch high CPU frequencies or/and optimal energy consumption. To save power when logical paths are not critical, regular-VT (RVT) transistors, which seat on classical-Wells, cannot be abutted to LVT transistors because of the Well bias conflicts. To overcome these multi-VT constraints, several innovative cointegration schemes based on single-Well (SW) approaches have been designed in 28nm UTBB FD-SOI technology and validated by silicon results.
{"title":"Performance analysis of multi-VT design solutions in 28nm UTBB FD-SOI technology","authors":"B. Pelloux-Prayer, Milovan Blagojevic, S. Haendler, A. Valentian, A. Amara, P. Flatresse","doi":"10.1109/S3S.2013.6716548","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716548","url":null,"abstract":"UTBB FD-SOI technology is able to reach very high speeds thanks to flip-Wells variant which enables low-VT (LVT) tuning. This approach appears to be the best design option to catch high CPU frequencies or/and optimal energy consumption. To save power when logical paths are not critical, regular-VT (RVT) transistors, which seat on classical-Wells, cannot be abutted to LVT transistors because of the Well bias conflicts. To overcome these multi-VT constraints, several innovative cointegration schemes based on single-Well (SW) approaches have been designed in 28nm UTBB FD-SOI technology and validated by silicon results.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114592218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716568
E. Galembeck, C. Renaux, D. Flandre, S. Gimenez
An experimental comparative study of the high temperature effects between the diamond SOI MOSFET (DSM) and conventional SOI MOSFET (CSM) counterparts is performed. The Diamond layout style has demonstrated better electrical performance in high temperatures environment, mainly for high-frequency analog IC applications, regarding the same gate area, aspect ratio and bias conditions. This can be justified due to the longitudinal corner effect (LCE) and PAMDLE (parallel association of MOSFETS with different channel lengths) effects remain active in the diamond layout style at high temperature.
{"title":"Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment","authors":"E. Galembeck, C. Renaux, D. Flandre, S. Gimenez","doi":"10.1109/S3S.2013.6716568","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716568","url":null,"abstract":"An experimental comparative study of the high temperature effects between the diamond SOI MOSFET (DSM) and conventional SOI MOSFET (CSM) counterparts is performed. The Diamond layout style has demonstrated better electrical performance in high temperatures environment, mainly for high-frequency analog IC applications, regarding the same gate area, aspect ratio and bias conditions. This can be justified due to the longitudinal corner effect (LCE) and PAMDLE (parallel association of MOSFETS with different channel lengths) effects remain active in the diamond layout style at high temperature.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127702800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716525
A. Feki, D. Turgis, Jean-Christophe Lafont, B. Allard
Sub-threshold operation of circuits becomes more and more attractive due to the ultra-low power consumption. Static Random Access Memory (SRAM) faces an important limitation in read access time that prevents high frequency operation and the possible applications. The read access time under ultra-low voltage (ULV) operation is mainly dictated by the read current of the SRAM bit cell and the bit line effective capacitance. The full swing sensing is a practical approach to circumvent the poor performances of sense amplifiers (SA) under ULV operation. This paper details first the optimization of a differential voltage-sense amplifier under ULV for SRAMs with differential bit lines. Second an unbalanced voltage-sense amplifier is presented for single-ended reading under ULV. Both circuits exploit the benefit of 28nm FDSOI and back biasing technique to improve SAs' performances, namely the delay. Both ultra-wide voltage-range SAs achieve satisfying operation down to 280mV power supply. Simulation results are presented regarding a 1K×32 L1 cache test chip to be fabricated in 28FDSOI technology.
{"title":"280mV sense amplifier designed in 28nm UTBB FD-SOI technology using back-biasing control","authors":"A. Feki, D. Turgis, Jean-Christophe Lafont, B. Allard","doi":"10.1109/S3S.2013.6716525","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716525","url":null,"abstract":"Sub-threshold operation of circuits becomes more and more attractive due to the ultra-low power consumption. Static Random Access Memory (SRAM) faces an important limitation in read access time that prevents high frequency operation and the possible applications. The read access time under ultra-low voltage (ULV) operation is mainly dictated by the read current of the SRAM bit cell and the bit line effective capacitance. The full swing sensing is a practical approach to circumvent the poor performances of sense amplifiers (SA) under ULV operation. This paper details first the optimization of a differential voltage-sense amplifier under ULV for SRAMs with differential bit lines. Second an unbalanced voltage-sense amplifier is presented for single-ended reading under ULV. Both circuits exploit the benefit of 28nm FDSOI and back biasing technique to improve SAs' performances, namely the delay. Both ultra-wide voltage-range SAs achieve satisfying operation down to 280mV power supply. Simulation results are presented regarding a 1K×32 L1 cache test chip to be fabricated in 28FDSOI technology.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129469293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716551
I. Ben Akkez, C. Fenouillet-Béranger, A. Cros, F. Balestra, G. Ghibaudo
In this work, we study the effect of the back biasing on the effective mobility in Ultra-Thin Box Fully Depleted SOI devices. Thanks to the carrier mobility extraction on large N & PMOS transistors, for thin (GO1) and thick gate oxide (GO2), the important role of the surface roughness and effective field in the mobility reduction is highlighted. Moreover, for the first time these electrical results have been corroborated by Poisson equation coupled with Hansch's quantum simulations.
{"title":"Evidence of mobility enhancement due to back biasing in UTBOX FDSOI high-k metal gate technology","authors":"I. Ben Akkez, C. Fenouillet-Béranger, A. Cros, F. Balestra, G. Ghibaudo","doi":"10.1109/S3S.2013.6716551","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716551","url":null,"abstract":"In this work, we study the effect of the back biasing on the effective mobility in Ultra-Thin Box Fully Depleted SOI devices. Thanks to the carrier mobility extraction on large N & PMOS transistors, for thin (GO1) and thick gate oxide (GO2), the important role of the surface roughness and effective field in the mobility reduction is highlighted. Moreover, for the first time these electrical results have been corroborated by Poisson equation coupled with Hansch's quantum simulations.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130021099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716578
F. Abouzeid, S. Clerc, B. Pelloux-Prayer, P. Roche
This work presents an ultra-low voltage SRAM read frequency boost circuit developed in 65nm to cover the lack of reliable sense amplifiers. This circuit enables full swing read speed-up and bitline leakage compensation from 1.2V to 0.42V. Embedded in a 65nm 32kb 10T SRAM, it offers 10% frequency gain and 10-to-90% leakage energy reduction from nominal to ultra-low voltage supply.
{"title":"0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm","authors":"F. Abouzeid, S. Clerc, B. Pelloux-Prayer, P. Roche","doi":"10.1109/S3S.2013.6716578","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716578","url":null,"abstract":"This work presents an ultra-low voltage SRAM read frequency boost circuit developed in 65nm to cover the lack of reliable sense amplifiers. This circuit enables full swing read speed-up and bitline leakage compensation from 1.2V to 0.42V. Embedded in a 65nm 32kb 10T SRAM, it offers 10% frequency gain and 10-to-90% leakage energy reduction from nominal to ultra-low voltage supply.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"65 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130312215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716537
A. Asenov
In this paper we will present recent advances in the simulation of statistical variability and reliability in advanced CMOS devices and circuits.
在本文中，我们将介绍先进CMOS器件和电路中统计变异性和可靠性模拟的最新进展。
{"title":"Simulation of statistical variability in nanometer scale CMOS devices","authors":"A. Asenov","doi":"10.1109/S3S.2013.6716537","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716537","url":null,"abstract":"In this paper we will present recent advances in the simulation of statistical variability and reliability in advanced CMOS devices and circuits.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716577
A. Banerjee, B. Calhoun
Operating both logic and memory at subthreshold supply voltages reduces energy dissipation for portable medical devices where battery life is critical. In this paper, we propose a 9T half-select-free subthreshold bitcell that has 2.05X lower mean read energy, 12.39% lower mean write energy, and 28% lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.
{"title":"An ultra low energy 9T half-select-free subthreshold SRAM bitcell","authors":"A. Banerjee, B. Calhoun","doi":"10.1109/S3S.2013.6716577","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716577","url":null,"abstract":"Operating both logic and memory at subthreshold supply voltages reduces energy dissipation for portable medical devices where battery life is critical. In this paper, we propose a 9T half-select-free subthreshold bitcell that has 2.05X lower mean read energy, 12.39% lower mean write energy, and 28% lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124899429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716559
A. Henning, B. Rajendran, B. Cronquist, Z. Or-Bach
A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.
{"title":"Thermal considerations for monolithic integration of three-dimensional integrated circuits","authors":"A. Henning, B. Rajendran, B. Cronquist, Z. Or-Bach","doi":"10.1109/S3S.2013.6716559","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716559","url":null,"abstract":"A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115074958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716563
K. Endo, Y. Ishikawa, Y. Liu, T. Matsukawa, S. O'Uchi, J. Tsukada, S. Migita, W. Mizubayashi, Y. Morita, H. Ota, H. Yamauchi, M. Masahara
We have successfully demonstrated a Vth controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin).
{"title":"Analysis of Vth flexibility in ultrathin-BOX SOI FinFETs","authors":"K. Endo, Y. Ishikawa, Y. Liu, T. Matsukawa, S. O'Uchi, J. Tsukada, S. Migita, W. Mizubayashi, Y. Morita, H. Ota, H. Yamauchi, M. Masahara","doi":"10.1109/S3S.2013.6716563","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716563","url":null,"abstract":"We have successfully demonstrated a V<sub>th</sub> controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate. It is revealed that the V<sub>th</sub> of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the V<sub>th</sub> controllability in terms of the size dependence such as the gate length (L<sub>G</sub>) and the fin width (T<sub>Fin</sub>).","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716582
F. Assaderaghi
MEMS (Micro-Electro-Mechanical Systems) have been developed over the past 40 years with ink jet, pressure sensor and accelerometers driving the technology. The last decade has particularly witnessed a tremendous commercial success of MEMS, addressing a plethora of functions such as screen orientation, gesture recognition, timing, voice input and location-based services. This success is the result of continually making these transducers including gyroscopes, accelerometers, resonators, microphones, and magnetometers smaller, lower power, more manufacturable, lower cost, more robust, and more functionally integrated. These characteristics, in turn, have come about by MEMS developers applying and extending the process technology used for fabrication of microelectronics. In fact, the wafer level batch processing has been the foundation of low-cost high-volume manufacturing of MEMS. Although a wide variety of materials are used in building MEMS, silicon has become the dominant choice due to its several useful properties. Single crystalline silicon (SCS) is particularly an excellent structural material for MEMS. SOI and Engineered SOI (ESOI) provide simple and elegant ways of creating transducers from SCS.
{"title":"SOI and Engineered-SOI, ideal platforms for building MEMS","authors":"F. Assaderaghi","doi":"10.1109/S3S.2013.6716582","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716582","url":null,"abstract":"MEMS (Micro-Electro-Mechanical Systems) have been developed over the past 40 years with ink jet, pressure sensor and accelerometers driving the technology. The last decade has particularly witnessed a tremendous commercial success of MEMS, addressing a plethora of functions such as screen orientation, gesture recognition, timing, voice input and location-based services. This success is the result of continually making these transducers including gyroscopes, accelerometers, resonators, microphones, and magnetometers smaller, lower power, more manufacturable, lower cost, more robust, and more functionally integrated. These characteristics, in turn, have come about by MEMS developers applying and extending the process technology used for fabrication of microelectronics. In fact, the wafer level batch processing has been the foundation of low-cost high-volume manufacturing of MEMS. Although a wide variety of materials are used in building MEMS, silicon has become the dominant choice due to its several useful properties. Single crystalline silicon (SCS) is particularly an excellent structural material for MEMS. SOI and Engineered SOI (ESOI) provide simple and elegant ways of creating transducers from SCS.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：