Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716545
Alexander E. Shapiro, E. Friedman
Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The feasibility of NTC technology with MOS Current Mode Logic (MCML) based on a 14 nm FinFET process node is examined in this paper. A 32 bit Kogge Stone adder is chosen as a demonstration vehicle for simulation and feasibility analysis. MCML yields enhanced power efficiency when operated with a 100% activity factor above 1 GHz as compared to CMOS. Standard CMOS does not achieve frequencies above 9 GHz without a dramatic increase in power consumption. MCML is most efficient beyond 9 GHz over a wide range of activity factors. MCML also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.
{"title":"Performance characteristics of 14 nm near threshold MCML circuits","authors":"Alexander E. Shapiro, E. Friedman","doi":"10.1109/S3S.2013.6716545","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716545","url":null,"abstract":"Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The feasibility of NTC technology with MOS Current Mode Logic (MCML) based on a 14 nm FinFET process node is examined in this paper. A 32 bit Kogge Stone adder is chosen as a demonstration vehicle for simulation and feasibility analysis. MCML yields enhanced power efficiency when operated with a 100% activity factor above 1 GHz as compared to CMOS. Standard CMOS does not achieve frequencies above 9 GHz without a dramatic increase in power consumption. MCML is most efficient beyond 9 GHz over a wide range of activity factors. MCML also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122941922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716532
S. Samal, Kiyoung Kim, Youngchan Kim, Taesung Kim, Hyuk-Jae Lee, Taewhan Kim, S. Lim
Digital circuits used in sensor networks require longer battery life and do not demand a fast frequency of operation. Sub-threshold circuits for such applications are an attractive option. Three dimensional ICs (3DICs) on the other hand is an emerging technology which helps in miniaturization and reduction in interconnects, resulting in power saving and performance improvement. Several works on sub-threshold circuits and TSV based 3DICs have been studied independently but none have studied the impact of 3D stacking of sub-threshold circuits. We design and study an ultra-low power 2-tier 3D sub-threshold implementation of H.264 intra frame encoder that encodes video frames. The encoder consumes 0.73μW power at 16.13 KHz clock frequency for a typical application of encoding a Common Image Format (CIF) frame. The motivation is to assess the feasibility of the use of extreme low power video encoders in image sensor based sensor networks. Low power operation is highly beneficial to such unattended sensor networks by extending their battery life. Sub-threshold design helps us in this respect while 3D stacking minimizes footprint area, helps in off-chip to on-chip memory integration and improves timing performance.
{"title":"Ultra low power 2-tier 3D stacked sub-threshold H.264 intra frame encoder","authors":"S. Samal, Kiyoung Kim, Youngchan Kim, Taesung Kim, Hyuk-Jae Lee, Taewhan Kim, S. Lim","doi":"10.1109/S3S.2013.6716532","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716532","url":null,"abstract":"Digital circuits used in sensor networks require longer battery life and do not demand a fast frequency of operation. Sub-threshold circuits for such applications are an attractive option. Three dimensional ICs (3DICs) on the other hand is an emerging technology which helps in miniaturization and reduction in interconnects, resulting in power saving and performance improvement. Several works on sub-threshold circuits and TSV based 3DICs have been studied independently but none have studied the impact of 3D stacking of sub-threshold circuits. We design and study an ultra-low power 2-tier 3D sub-threshold implementation of H.264 intra frame encoder that encodes video frames. The encoder consumes 0.73μW power at 16.13 KHz clock frequency for a typical application of encoding a Common Image Format (CIF) frame. The motivation is to assess the feasibility of the use of extreme low power video encoders in image sensor based sensor networks. Low power operation is highly beneficial to such unattended sensor networks by extending their battery life. Sub-threshold design helps us in this respect while 3D stacking minimizes footprint area, helps in off-chip to on-chip memory integration and improves timing performance.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125611085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716558
N. Daix, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa, J. Fompeyrine
Ultra-thin-body on buried oxide (UTBB) InGaAs are promising layers for the next generation of transistors. One way to fabricate InGaAs layer on Si or SiGe substrates is the direct wafer bonding technique with ion implantation and thermal splitting. We have investigated the bonding energy of two possible candidates for the buried oxide (BOX), Al2O3 and SiO2, between room temperature and 450°C. Then we have compared the properties of InAlAs, InP and InGaAs buffers for the implantation and splitting processes.
{"title":"Thermal stability of ultra-thin InGaAs-on-insulator substrates","authors":"N. Daix, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa, J. Fompeyrine","doi":"10.1109/S3S.2013.6716558","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716558","url":null,"abstract":"Ultra-thin-body on buried oxide (UTBB) InGaAs are promising layers for the next generation of transistors. One way to fabricate InGaAs layer on Si or SiGe substrates is the direct wafer bonding technique with ion implantation and thermal splitting. We have investigated the bonding energy of two possible candidates for the buried oxide (BOX), Al2O3 and SiO2, between room temperature and 450°C. Then we have compared the properties of InAlAs, InP and InGaAs buffers for the implantation and splitting processes.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125653190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716585
S. Makovejev, B. K. Esfeh, F. Andrieu, J. Raskin, D. Flandre, V. Kilchytska
Global variability of UTBB MOSFETs in subthresh-old and off regimes is analyzed. Variability of the off-state drain current, subthreshold slope, DIBL, gate leakage current, threshold voltage and their correlations are considered. It is demonstrated that subthreshold drain current variability is not only dependent on the threshold voltage variability, but the effective body factor (incorporating short-channel effects) must also be taken into account.
{"title":"Global variability of UTBB MOSFET in subthreshold","authors":"S. Makovejev, B. K. Esfeh, F. Andrieu, J. Raskin, D. Flandre, V. Kilchytska","doi":"10.1109/S3S.2013.6716585","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716585","url":null,"abstract":"Global variability of UTBB MOSFETs in subthresh-old and off regimes is analyzed. Variability of the off-state drain current, subthreshold slope, DIBL, gate leakage current, threshold voltage and their correlations are considered. It is demonstrated that subthreshold drain current variability is not only dependent on the threshold voltage variability, but the effective body factor (incorporating short-channel effects) must also be taken into account.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":" 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132041301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716562
Meenatchi Jagasivamani, M. Bajura, M. Fritze
With the increased focus on power efficiency, there is a push towards lowering the supply voltage and operating the design in the sub-threshold regime. While this is good for lowering the active power, it makes certain circuits more susceptible to single-event effects due to poor Ioff/Ion ratio. The 28-T mirror adder is a key building block for many arithmetic and digital signal processing systems. Yet, the mirror full adder is vulnerable to failure in sub-threshold operation due to its long chain of transistors in series and xor-parallel configuration. By replacing the transistors in the vulnerable configuration with low-Vt transistors, we are able to strengthen the circuit for sub-threshold operation. In this paper, we look at the effect of a dual-Vt version of the basic mirror adder circuit in the 65nm technology node.
{"title":"Dual threshold voltage adder for robust sub-Vt operation in 65nm technology","authors":"Meenatchi Jagasivamani, M. Bajura, M. Fritze","doi":"10.1109/S3S.2013.6716562","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716562","url":null,"abstract":"With the increased focus on power efficiency, there is a push towards lowering the supply voltage and operating the design in the sub-threshold regime. While this is good for lowering the active power, it makes certain circuits more susceptible to single-event effects due to poor Ioff/Ion ratio. The 28-T mirror adder is a key building block for many arithmetic and digital signal processing systems. Yet, the mirror full adder is vulnerable to failure in sub-threshold operation due to its long chain of transistors in series and xor-parallel configuration. By replacing the transistors in the vulnerable configuration with low-Vt transistors, we are able to strengthen the circuit for sub-threshold operation. In this paper, we look at the effect of a dual-Vt version of the basic mirror adder circuit in the 65nm technology node.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114654099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716544
Jia Yao, V. Agrawal
Dual threshold voltage (Vth) design is a common method for reducing leakage power in above-threshold circuits. This research shows that it is also effective in reducing energy per cycle of sub-threshold circuits. We first study the single-Vth design theoretically and by simulations, and find that the energy per cycle is independent of threshold voltage. However, in a dual-Vth design, the energy per cycle depends on both threshold voltage and supply voltage. We propose a framework to further reduce energy per cycle below what is possible with a single Vth. Given a nominal value for Vth, we determine an optimal supply voltage Vdd and an optimal higher Vth. Application to a 32-bit ripple carry adder shows energy saving of 29% over the single-Vth lowest energy.
{"title":"Dual-threshold design of sub-threshold circuits","authors":"Jia Yao, V. Agrawal","doi":"10.1109/S3S.2013.6716544","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716544","url":null,"abstract":"Dual threshold voltage (V<sub>th</sub>) design is a common method for reducing leakage power in above-threshold circuits. This research shows that it is also effective in reducing energy per cycle of sub-threshold circuits. We first study the single-V<sub>th</sub> design theoretically and by simulations, and find that the energy per cycle is independent of threshold voltage. However, in a dual-V<sub>th</sub> design, the energy per cycle depends on both threshold voltage and supply voltage. We propose a framework to further reduce energy per cycle below what is possible with a single V<sub>th</sub>. Given a nominal value for V<sub>th</sub>, we determine an optimal supply voltage V<sub>dd</sub> and an optimal higher V<sub>th</sub>. Application to a 32-bit ripple carry adder shows energy saving of 29% over the single-V<sub>th</sub> lowest energy.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123878521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716550
Takayuki Mori, J. Ida
Ultra Low Power (ULP) LSI's require the steep subthreshold slope (SS) MOSFET. However, the theoretical SS limit of the conventional MOSFET is 60mV/dec at the room temperature. Recently, devices which have the less than 60mV/dec SS, such as the Tunnel FET (TFET) and the Impact Ionization MOS (I-MOS), have been studied. In addition to those, the steep SS MOSFET's using the Floating-Body (FB) SOI have been proposed. In this work, we report our finding of the FB and the Body-Tied (BT) SOI MOSFET with the super steep SS (<; 1mV/Dec) characteristics with the 0.15um SOI. We also discuss the possibility of it as a switching device for the ultra low voltage application, where we consider that the three points are the issues to improve; reducing the operation voltage, increasing Ion/Ioff ratios which also pay attention keeping the low Ioff, controlling hysteresis characteristics.
超低功耗(ULP) LSI需要陡的亚阈值斜率(SS) MOSFET。然而，在室温下，传统MOSFET的理论SS极限为60mV/dec。近年来，人们研究了功率小于60mV/dec的器件，如隧道场效应管(TFET)和冲击电离MOS (I-MOS)。此外，还提出了采用浮体(FB) SOI的陡坡SS MOSFET。在这项工作中，我们报告了我们的发现FB和体系(BT) SOI MOSFET具有超陡SS (<;1mV/Dec)特性与0.15um SOI。我们还讨论了它作为超低电压应用的开关器件的可能性，其中我们认为这三点是有待改进的问题;降低工作电压，提高离子/开关比，同时注意保持低开关，控制迟滞特性。
{"title":"Possibility of SOI based super steep subthreshold slope MOSFET for ultra low voltage application","authors":"Takayuki Mori, J. Ida","doi":"10.1109/S3S.2013.6716550","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716550","url":null,"abstract":"Ultra Low Power (ULP) LSI's require the steep subthreshold slope (SS) MOSFET. However, the theoretical SS limit of the conventional MOSFET is 60mV/dec at the room temperature. Recently, devices which have the less than 60mV/dec SS, such as the Tunnel FET (TFET) and the Impact Ionization MOS (I-MOS), have been studied. In addition to those, the steep SS MOSFET's using the Floating-Body (FB) SOI have been proposed. In this work, we report our finding of the FB and the Body-Tied (BT) SOI MOSFET with the super steep SS (<; 1mV/Dec) characteristics with the 0.15um SOI. We also discuss the possibility of it as a switching device for the ultra low voltage application, where we consider that the three points are the issues to improve; reducing the operation voltage, increasing Ion/Ioff ratios which also pay attention keeping the low Ioff, controlling hysteresis characteristics.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716567
Jinyong Oh, Seung-min Lee, Jong-Tea Park, M. Triplett, Dong Yu, M. Islam
For the first time, herein we demonstrate gate-all-around field-effect-transistors having a horizontally suspended nanowire channel. The suspended nanowires were grown using the vapor-liquid-solid technique. The gate-all-around field-effect-transistor exhibited a p-type accumulation mode with desirable performance. To study properties of the connection between the nanowire channels and electrodes, measurements of surface photocurrent and temperature dependent current-voltage between source and drain electrodes were carried out. The results including an energy band diagram are discussed in this paper.
{"title":"Demonstration of gate-all-around FETs based on suspended CVD-grown silicon nanowires","authors":"Jinyong Oh, Seung-min Lee, Jong-Tea Park, M. Triplett, Dong Yu, M. Islam","doi":"10.1109/S3S.2013.6716567","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716567","url":null,"abstract":"For the first time, herein we demonstrate gate-all-around field-effect-transistors having a horizontally suspended nanowire channel. The suspended nanowires were grown using the vapor-liquid-solid technique. The gate-all-around field-effect-transistor exhibited a p-type accumulation mode with desirable performance. To study properties of the connection between the nanowire channels and electrodes, measurements of surface photocurrent and temperature dependent current-voltage between source and drain electrodes were carried out. The results including an energy band diagram are discussed in this paper.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"747 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716560
X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph
SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].
{"title":"Concurrent design analysis of A 8500V ESD-protected SP10T switch in SOI CMOS","authors":"X. S. Wang, Xin Wang, Z. Dong, Fei Lu, Li Wang, R. Ma, Chen Zhang, Albert Z. H. Wang, C. Yue, Dawn Wang, A. Joseph","doi":"10.1109/S3S.2013.6716560","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716560","url":null,"abstract":"SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"540 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124535968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716535
P. Hurwitz, S. Chaudry, V. Blaschke, M. Racanelli
In the last few years, RF SOI has become the technology of choice for RF switches (RFSW) in wireless front-end modules, displacing GaAs pHEMT. More recently RF SOI has also been deployed to switch capacitor banks in antenna tuning applications and is now being discussed as the right technology for integration of tunable power-amplifiers, promising a path to a single-chip front-end module. In this paper we review the latest advancements in RF SOI foundry technology with focus on key figures of merit such as Ron × Coff, switch branch power handling, and linearity. In addition to these process-driven metrics, we will describe attributes of the compact models and design environment that allow fast and accurate simulation of small signal and large signal RFSW performance to create the most advanced and highly integrated products.
{"title":"Foundry SOI technology for wireless front end modules","authors":"P. Hurwitz, S. Chaudry, V. Blaschke, M. Racanelli","doi":"10.1109/S3S.2013.6716535","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716535","url":null,"abstract":"In the last few years, RF SOI has become the technology of choice for RF switches (RFSW) in wireless front-end modules, displacing GaAs pHEMT. More recently RF SOI has also been deployed to switch capacitor banks in antenna tuning applications and is now being discussed as the right technology for integration of tunable power-amplifiers, promising a path to a single-chip front-end module. In this paper we review the latest advancements in RF SOI foundry technology with focus on key figures of merit such as Ron × Coff, switch branch power handling, and linearity. In addition to these process-driven metrics, we will describe attributes of the compact models and design environment that allow fast and accurate simulation of small signal and large signal RFSW performance to create the most advanced and highly integrated products.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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