Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716530
M. Gaillardin, M. Raine, P. Paillet, M. Martinez, C. Marcandella, S. Girard, O. Duhamel, N. Richard, F. Andrieu, S. Barraud, O. Faynot
The SOI technology has already demonstrated intrinsic resistance to transient radiation effects due to the dielectric isolation provided by the buried oxide. But this special feature raises questions about their Total Ionizing Dose (TID) sensitivity, particularly in Fully Depleted (FD) SOI and multiple-gate devices. This paper thus gives an overview of recent advances in radiation effects on innovative SOI devices. Both TID and Single-Event Effects (SEE) in Extra Thin SOI (ETSOI) and FinFET devices are reviewed as well as upcoming challenges to mitigate radiation effects in nanometer scale SOI technologies.
{"title":"Radiation effects in advanced SOI devices: New insights into Total Ionizing Dose and Single-Event Effects","authors":"M. Gaillardin, M. Raine, P. Paillet, M. Martinez, C. Marcandella, S. Girard, O. Duhamel, N. Richard, F. Andrieu, S. Barraud, O. Faynot","doi":"10.1109/S3S.2013.6716530","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716530","url":null,"abstract":"The SOI technology has already demonstrated intrinsic resistance to transient radiation effects due to the dielectric isolation provided by the buried oxide. But this special feature raises questions about their Total Ionizing Dose (TID) sensitivity, particularly in Fully Depleted (FD) SOI and multiple-gate devices. This paper thus gives an overview of recent advances in radiation effects on innovative SOI devices. Both TID and Single-Event Effects (SEE) in Extra Thin SOI (ETSOI) and FinFET devices are reviewed as well as upcoming challenges to mitigate radiation effects in nanometer scale SOI technologies.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124899755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716534
James P. Young, D. Ripley, P. Lehtola
Envelope Tracking (ET) power amplifiers (PA) have been developed for next generation mobile handsets and tablets to improve efficiency. The ET PA provides improved system efficiency at the highest output power levels but does require performance trade-offs which must be considered. This paper will discuss the ET system performance, compare PA technologies and will provide some of the system performance tradeoffs when implementing the ET PA.
{"title":"Envelope Tracking power amplifier optimization for mobile applications","authors":"James P. Young, D. Ripley, P. Lehtola","doi":"10.1109/S3S.2013.6716534","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716534","url":null,"abstract":"Envelope Tracking (ET) power amplifiers (PA) have been developed for next generation mobile handsets and tablets to improve efficiency. The ET PA provides improved system efficiency at the highest output power levels but does require performance trade-offs which must be considered. This paper will discuss the ET system performance, compare PA technologies and will provide some of the system performance tradeoffs when implementing the ET PA.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124984572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716571
J. Nam, W. Jung, J. Shim, T. Ito, Y. Nishi, J. Park, K. Saraswat
A CMOS compatible technique for fabricating germanium (Ge) on insulator (GOI) structure that is locally implemented on silicon (Si) substrate is demonstrated. On a (100) crystalline Si substrate, silicon dioxide (SiO2) is thermally grown. Then growth window for Ge is defined by locally etching down the SiO2 to reveal the Si surface. Ge is grown epitaxially with multiple steps of high temperature hydrogen (H2) annealing. After growing Ge crystals fill the growth window, the growth proceeds laterally and, finally coalesces with the neighbouring Ge growth window. Thus crystalline Ge sitting on SiO2 is achieved. Chemical mechanical polishing (CMP) is used to planarize the surface, and wet etching is done to control the GOI film thickness.
{"title":"Germanium on insulator (GOI) structure locally grown on silicon using hetero epitaxial lateral overgrowth","authors":"J. Nam, W. Jung, J. Shim, T. Ito, Y. Nishi, J. Park, K. Saraswat","doi":"10.1109/S3S.2013.6716571","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716571","url":null,"abstract":"A CMOS compatible technique for fabricating germanium (Ge) on insulator (GOI) structure that is locally implemented on silicon (Si) substrate is demonstrated. On a (100) crystalline Si substrate, silicon dioxide (SiO2) is thermally grown. Then growth window for Ge is defined by locally etching down the SiO2 to reveal the Si surface. Ge is grown epitaxially with multiple steps of high temperature hydrogen (H2) annealing. After growing Ge crystals fill the growth window, the growth proceeds laterally and, finally coalesces with the neighbouring Ge growth window. Thus crystalline Ge sitting on SiO2 is achieved. Chemical mechanical polishing (CMP) is used to planarize the surface, and wet etching is done to control the GOI film thickness.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716581
S. Takagi, S. Kim, M. Yokoyama, W. Kim, R. Zhang, M. Takenaka
MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime [1, 2]. From this viewpoint, attentions have recently been paid to III-V and Ge channels. This is because III-V semiconductors have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass. In addition, ultra-thin body structure is mandatory for MOSFET with future technology nodes for suppressing short channel effects. In this presentation, the critical issues and the present status of ultrathin body III-V/Ge MOSFETs are addressed.
{"title":"Ultra-thin body MOS device technologies using high mobility channel materials","authors":"S. Takagi, S. Kim, M. Yokoyama, W. Kim, R. Zhang, M. Takenaka","doi":"10.1109/S3S.2013.6716581","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716581","url":null,"abstract":"MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime [1, 2]. From this viewpoint, attentions have recently been paid to III-V and Ge channels. This is because III-V semiconductors have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass. In addition, ultra-thin body structure is mandatory for MOSFET with future technology nodes for suppressing short channel effects. In this presentation, the critical issues and the present status of ultrathin body III-V/Ge MOSFETs are addressed.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126440202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716564
G. D. Colletta, Odilon O. Dutra, L. H. C. Ferreira, T. Pimenta
In this paper an ultra-low-power first-order asynchronous sigma-delta modulator (ASDM) for biomedical applications in weak inversion is presented. It combines a Gm-C integrator as a linear filter in addition to a kind of zero biasing continuous time comparator with hysteresis as a non-linear element. The proposed ASDM was successfully simulated in an 130-nm IBM CMOS process. The simulations show a SINAD of 43.48 dB in a frequency bandwidth of 250 Hz for a modulation depth of 70 % with only 500 mV of power supply voltage and just 7.5 nW of power consumption. The typical figure of merit used to evaluate ADC circuits predicts an energy of 0.11 pJ per conversion step, which is suitable for implantable/wearable biomedical applications.
{"title":"An ultra-low-power first-order asynchronous sigma-delta modulator for biomedical applications","authors":"G. D. Colletta, Odilon O. Dutra, L. H. C. Ferreira, T. Pimenta","doi":"10.1109/S3S.2013.6716564","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716564","url":null,"abstract":"In this paper an ultra-low-power first-order asynchronous sigma-delta modulator (ASDM) for biomedical applications in weak inversion is presented. It combines a Gm-C integrator as a linear filter in addition to a kind of zero biasing continuous time comparator with hysteresis as a non-linear element. The proposed ASDM was successfully simulated in an 130-nm IBM CMOS process. The simulations show a SINAD of 43.48 dB in a frequency bandwidth of 250 Hz for a modulation depth of 70 % with only 500 mV of power supply voltage and just 7.5 nW of power consumption. The typical figure of merit used to evaluate ADC circuits predicts an energy of 0.11 pJ per conversion step, which is suitable for implantable/wearable biomedical applications.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126510932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/S3S.2013.6716520
A. Khakifirooz, R. Sreenivasan, B. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E. C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S. Mignot, D. Lu, H. He, T. Yamashita, P. Morin, G. Tsutsui, C. Chen, V. Basker, T. Standaert, K. Cheng, T. Levin, B. Nguyen, Tsu-Jae King Liu, D. Guo, H. Bu, K. Rim, B. Doris
Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm.
{"title":"Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs","authors":"A. Khakifirooz, R. Sreenivasan, B. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E. C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S. Mignot, D. Lu, H. He, T. Yamashita, P. Morin, G. Tsutsui, C. Chen, V. Basker, T. Standaert, K. Cheng, T. Levin, B. Nguyen, Tsu-Jae King Liu, D. Guo, H. Bu, K. Rim, B. Doris","doi":"10.1109/S3S.2013.6716520","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716520","url":null,"abstract":"Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"453 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131802201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/S3S.2013.6716527
R. Liao, R. Ahmed, C. Hutchens, R. Rennaker
Recent research trend of passive RFID based sensors has posed stringent low power requirement for energy efficient communication, which can be addressed by sub/near-Vt operation with standard CMOS process. This paper discusses new design challenges under scaled voltages and presents critical building blocks for low power protocol processing. Two supply viltages -0.45V and 0.7V are selected for powering digital and analog circuits which process EPC Gen-2 physical layer data. The design was fabricated in 180nm CMOS process and probe station measurement are reported.
{"title":"Enabling energy efficient protocol processing for passive RFID sensors using sub/near-threshold circuit","authors":"R. Liao, R. Ahmed, C. Hutchens, R. Rennaker","doi":"10.1109/S3S.2013.6716527","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716527","url":null,"abstract":"Recent research trend of passive RFID based sensors has posed stringent low power requirement for energy efficient communication, which can be addressed by sub/near-Vt operation with standard CMOS process. This paper discusses new design challenges under scaled voltages and presents critical building blocks for low power protocol processing. Two supply viltages -0.45V and 0.7V are selected for powering digital and analog circuits which process EPC Gen-2 physical layer data. The design was fabricated in 180nm CMOS process and probe station measurement are reported.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124040779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/S3S.2013.6716522
M. de Souza, R. T. Doria, E. Simoen, J. Martino, C. Claeys, M. Pavanello
This work presented an experimental study of the influence of combining the biaxial strain and 45° substrate rotation on the low-frequency noise of triple gate MuGFETs with different WFin and bias conditions. The results showed a 1/f noise characteristic for the strained and strained rotated devices in linear region, independent of WFin The strained rotated nMuGFET presents a lower LFN for narrow dimensions for practically all VGT condition, meanwhile for wider devices the opposite was found. The substrate rotation of strained MuGFETs is able to reduce the sidewall LFN.
{"title":"Influence of substrate rotation on the low frequency noise of strained triple-gate MuGFETs","authors":"M. de Souza, R. T. Doria, E. Simoen, J. Martino, C. Claeys, M. Pavanello","doi":"10.1109/S3S.2013.6716522","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716522","url":null,"abstract":"This work presented an experimental study of the influence of combining the biaxial strain and 45° substrate rotation on the low-frequency noise of triple gate MuGFETs with different WFin and bias conditions. The results showed a 1/f noise characteristic for the strained and strained rotated devices in linear region, independent of WFin The strained rotated nMuGFET presents a lower LFN for narrow dimensions for practically all VGT condition, meanwhile for wider devices the opposite was found. The substrate rotation of strained MuGFETs is able to reduce the sidewall LFN.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115937345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/S3S.2013.6716539
V. Hu, M. Fan, P. Su, C. Chuang
This paper evaluates the impacts of Transient Voltage Collapse (TVC) Write-Assist on the GeOI and SOI FinFET SRAM cells with global and local random variations. With the TVC Write-Assist, the Write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC Write-Assist pulse width constrained by the data retention failure is smaller in the GeOI FinFET SRAMs at 25°C and becomes comparable at 125°C compared with the SOI FinFET SRAMs.
{"title":"Evaluation of transient voltage collapse write-assist for GeOI and SOI FinFET SRAM cells","authors":"V. Hu, M. Fan, P. Su, C. Chuang","doi":"10.1109/S3S.2013.6716539","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716539","url":null,"abstract":"This paper evaluates the impacts of Transient Voltage Collapse (TVC) Write-Assist on the GeOI and SOI FinFET SRAM cells with global and local random variations. With the TVC Write-Assist, the Write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC Write-Assist pulse width constrained by the data retention failure is smaller in the GeOI FinFET SRAMs at 25°C and becomes comparable at 125°C compared with the SOI FinFET SRAMs.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127554113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/S3S.2013.6716576
N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Oda, S. Kamohara, Y. Yamaguchi, K. Ishibashi, T. Mizutani, T. Hiramoto
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the near- or sub-Vth operation is effective in reducing energy per operation of CMOS circuits, its slow operation speed can miss a chance to be used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ul-tralow-power (ULP) electronics because of its small variability and back-bias control. This paper describes our results on the ULV operation of SRAM and ring oscillator (RO) circuits and shows the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating at ~0.4 V are expected to be implemented in many applications such as the internet of things.
{"title":"Vmin=0.4 V LSIs are the real with silicon-on-thin-buried-oxide (SOTB) — How is the application with \"Perpetuum-Mobile\" micro-controller with SOTB?","authors":"N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Oda, S. Kamohara, Y. Yamaguchi, K. Ishibashi, T. Mizutani, T. Hiramoto","doi":"10.1109/S3S.2013.6716576","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716576","url":null,"abstract":"Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the near- or sub-Vth operation is effective in reducing energy per operation of CMOS circuits, its slow operation speed can miss a chance to be used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ul-tralow-power (ULP) electronics because of its small variability and back-bias control. This paper describes our results on the ULV operation of SRAM and ring oscillator (RO) circuits and shows the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating at ~0.4 V are expected to be implemented in many applications such as the internet of things.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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