Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716518
J. Cai, T. Ning, C. D'Emic, J. Yau, K. Chan, J. Yoon, K. Jenkins, R. Muralidhar, D. Park
Record-high drive current on the order of 3-5mA/μm is demonstrated in lateral silicon bipolar transistors on SOI. This is achieved by scaling quasi-neutral base width to below 10nm. The heavily doped collector enables the transistor to operate in high level injection regime without the detrimental base push-out effect. Measured cut-off frequency is the highest for a lateral bipolar and has a broad peak, confirming its immunity to base push-out. Functional complementary bipolar ring oscillator operating in the full saturation region is reported for the first time. The salient features of CMOS-compatible process and design, high current drive capability and low voltage bipolar logic present exciting opportunities for lateral SOI bipolar to complement CMOS.
{"title":"SOI lateral bipolar transistor with drive current >3mA/μm","authors":"J. Cai, T. Ning, C. D'Emic, J. Yau, K. Chan, J. Yoon, K. Jenkins, R. Muralidhar, D. Park","doi":"10.1109/S3S.2013.6716518","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716518","url":null,"abstract":"Record-high drive current on the order of 3-5mA/μm is demonstrated in lateral silicon bipolar transistors on SOI. This is achieved by scaling quasi-neutral base width to below 10nm. The heavily doped collector enables the transistor to operate in high level injection regime without the detrimental base push-out effect. Measured cut-off frequency is the highest for a lateral bipolar and has a broad peak, confirming its immunity to base push-out. Functional complementary bipolar ring oscillator operating in the full saturation region is reported for the first time. The salient features of CMOS-compatible process and design, high current drive capability and low voltage bipolar logic present exciting opportunities for lateral SOI bipolar to complement CMOS.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126806984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716523
R. Coquand, M. Jaud, O. Rozeau, A. Idrissi-Eloudrhiri, S. Martinie, F. Triozon, N. Pons, S. Barraud, S. Monfray, F. Boeuf, G. Ghibaudo, O. Faynot
This study highlights the behavior of triple gate SOI transistors on thin BOx. Simulated in 3D TCAD, TriGate and FinFET structures are evaluated with scaled EOT of 0.82nm, proposed for 10nm technology node. Due to a good compromise of channel control by the gate and back-biasing through ultra-thin BOx, TriGate FETs can combine excellent electrostatics with sufficient body-factor (BF), unlike FinFETs. To be fully efficient, a multi-Vt strategy by back-biasing technique on TriGate needs no BOx recess and ultra-thin BOx of 10nm. In these conditions and at gate length L=15nm, back-biasing on TriGate could allow ×1.3 ION and /16 IOFF performance.
{"title":"Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices","authors":"R. Coquand, M. Jaud, O. Rozeau, A. Idrissi-Eloudrhiri, S. Martinie, F. Triozon, N. Pons, S. Barraud, S. Monfray, F. Boeuf, G. Ghibaudo, O. Faynot","doi":"10.1109/S3S.2013.6716523","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716523","url":null,"abstract":"This study highlights the behavior of triple gate SOI transistors on thin BOx. Simulated in 3D TCAD, TriGate and FinFET structures are evaluated with scaled EOT of 0.82nm, proposed for 10nm technology node. Due to a good compromise of channel control by the gate and back-biasing through ultra-thin BOx, TriGate FETs can combine excellent electrostatics with sufficient body-factor (BF), unlike FinFETs. To be fully efficient, a multi-Vt strategy by back-biasing technique on TriGate needs no BOx recess and ultra-thin BOx of 10nm. In these conditions and at gate length L=15nm, back-biasing on TriGate could allow ×1.3 ION and /16 IOFF performance.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129237323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716524
P. Mercier, Saurav Bandropadhyay, A. Chandrakasan
This paper presents subthreshold leakage management techniques to enable the design of a 2.4 GHz RF transmitter with ultra-low average power. Careful device size optimizations and judicious use of power gating devices shows that leakage power of the radio can be reduced by upwards of 4000X. When operating at a duty-cycled average data rate of 1 b/s, the implemented transmitter consumes 78 pW.
{"title":"Enabling Sub-nW RF circuits through subthreshold leakage management","authors":"P. Mercier, Saurav Bandropadhyay, A. Chandrakasan","doi":"10.1109/S3S.2013.6716524","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716524","url":null,"abstract":"This paper presents subthreshold leakage management techniques to enable the design of a 2.4 GHz RF transmitter with ultra-low average power. Careful device size optimizations and judicious use of power gating devices shows that leakage power of the radio can be reduced by upwards of 4000X. When operating at a duty-cycled average data rate of 1 b/s, the implemented transmitter consumes 78 pW.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"5 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114179980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716546
L. Grenouillet, Q. Liu, R. Wacquez, P. Morin, N. Loubet, D. Cooper, A. Pofelski, W. Weng, F. Bauman, M. Gribelyuk, Y. Wang, B. De Salvo, J. Gimbert, K. Cheng, Y. Le Tiec, D. Chanemougame, E. Augendre, S. Maitrejean, A. Khakifirooz, J. Kuss, R. Schulz, C. Janicki, B. Lherron, S. Guillaumet, O. Rozeau, F. Chafik, J. Bataillon, T. Wu, W. Kleemeier, M. Celik, O. Faynot, R. Sampson, B. Doris, M. Vinet
UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.
{"title":"UTBB FDSOI scaling enablers for the 10nm node","authors":"L. Grenouillet, Q. Liu, R. Wacquez, P. Morin, N. Loubet, D. Cooper, A. Pofelski, W. Weng, F. Bauman, M. Gribelyuk, Y. Wang, B. De Salvo, J. Gimbert, K. Cheng, Y. Le Tiec, D. Chanemougame, E. Augendre, S. Maitrejean, A. Khakifirooz, J. Kuss, R. Schulz, C. Janicki, B. Lherron, S. Guillaumet, O. Rozeau, F. Chafik, J. Bataillon, T. Wu, W. Kleemeier, M. Celik, O. Faynot, R. Sampson, B. Doris, M. Vinet","doi":"10.1109/S3S.2013.6716546","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716546","url":null,"abstract":"UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716572
Y. Liu, T. Nabatame, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow, M. Masahara
In this paper, as a further study, we fabricated charge trapping type SOI-FinFET flash memories with different blocking layers of Al2O3 and SiO2, and comparatively investigate their electrical characteristics.
{"title":"Charge trapping type FinFET flash memory with Al2O3 blocking layer","authors":"Y. Liu, T. Nabatame, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow, M. Masahara","doi":"10.1109/S3S.2013.6716572","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716572","url":null,"abstract":"In this paper, as a further study, we fabricated charge trapping type SOI-FinFET flash memories with different blocking layers of Al<sub>2</sub>O<sub>3</sub> and SiO<sub>2</sub>, and comparatively investigate their electrical characteristics.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133494706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716547
R. Thewes, G. Enders, F. Hofmann, W. Hoenlein, J. Vollrath, R. Ferrant, P. Flatresse, B. Pelloux-Prayer, F. Allain, G. Reimbold, C. Mazure
The fluctuations of linear and saturation mode threshold voltage of FDSOI transistors are strongly correlated. They show negligible dependence on the backgate voltage even under large backgate biasing variations. Drain current variation is also highly correlated with the threshold voltage. A calculated matching constant normalized to oxide thickness reveals excellent values of around 1 mV μm / nm.
{"title":"Matching behavior of analog FDSOI n-MOS-transistors under large backgate voltage swing operating conditions","authors":"R. Thewes, G. Enders, F. Hofmann, W. Hoenlein, J. Vollrath, R. Ferrant, P. Flatresse, B. Pelloux-Prayer, F. Allain, G. Reimbold, C. Mazure","doi":"10.1109/S3S.2013.6716547","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716547","url":null,"abstract":"The fluctuations of linear and saturation mode threshold voltage of FDSOI transistors are strongly correlated. They show negligible dependence on the backgate voltage even under large backgate biasing variations. Drain current variation is also highly correlated with the threshold voltage. A calculated matching constant normalized to oxide thickness reveals excellent values of around 1 mV μm / nm.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"17 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133553050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716538
R. Lerner, D. Gaebler, K. Schottmann, S. Hering
The integration of various new optical and high voltage devices into an existing trench isolated 650 V BCD process on thick SOI wafers with a minimum of additional processing effort is reported. The trench isolation together with the thickness of the SOI wafer allows the construction of isolated photodiodes with excellent response even for red and infrared wavelengths. Furthermore the thick SOI material enables the integration of vertical high voltage devices like NPN bipolar transistors. Together with a special collector design the SOI topology allows the integration of IGBT devices which can be tuned by design measures only between on-state and switching performance.
将各种新的光学和高压器件集成到现有的沟槽隔离650 V BCD工艺中，并在厚SOI晶圆上进行最小的额外处理工作。沟槽隔离以及SOI晶圆的厚度允许构建隔离的光电二极管，即使对红色和红外波长也具有出色的响应。此外，厚SOI材料可以集成垂直高压器件，如NPN双极晶体管。与特殊的集电极设计一起，SOI拓扑允许集成IGBT器件，这些器件可以通过设计措施仅在导通状态和开关性能之间进行调整。
{"title":"A trench isolated thick SOI process as platform for various electrical and optical integrated devices","authors":"R. Lerner, D. Gaebler, K. Schottmann, S. Hering","doi":"10.1109/S3S.2013.6716538","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716538","url":null,"abstract":"The integration of various new optical and high voltage devices into an existing trench isolated 650 V BCD process on thick SOI wafers with a minimum of additional processing effort is reported. The trench isolation together with the thickness of the SOI wafer allows the construction of isolated photodiodes with excellent response even for red and infrared wavelengths. Furthermore the thick SOI material enables the integration of vertical high voltage devices like NPN bipolar transistors. Together with a special collector design the SOI topology allows the integration of IGBT devices which can be tuned by design measures only between on-state and switching performance.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130889053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716579
L. Atias, A. Teman, A. Fish
In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.
{"title":"A 13T radiation hardened SRAM bitcell for low-voltage operation","authors":"L. Atias, A. Teman, A. Fish","doi":"10.1109/S3S.2013.6716579","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716579","url":null,"abstract":"In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132786945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716557
T. Sasaki, T. Endoh
This paper presents the gate length scaling of the Vertical MOSFET (VMOS) with high-k dielectrics for beyond 20nm CMOS technology in comparison with Double Gate MOSFET (DG) at the same Drain Induced Barrier Lowering (DIBL). The VMOS can significantly suppresses DIBL within 11mV/V caused by fringing electric field through thicker designed high-k dielectrics (EOT=1.0nm). Moreover, the VMOS can be designed by shorter gate length from 5.4 to 19nm as using higher gate dielectric constant from k=10 to k=60.
{"title":"Gate length scaling of high-k vertical MOSFET toward 20nm CMOS technology and beyond","authors":"T. Sasaki, T. Endoh","doi":"10.1109/S3S.2013.6716557","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716557","url":null,"abstract":"This paper presents the gate length scaling of the Vertical MOSFET (VMOS) with high-k dielectrics for beyond 20nm CMOS technology in comparison with Double Gate MOSFET (DG) at the same Drain Induced Barrier Lowering (DIBL). The VMOS can significantly suppresses DIBL within 11mV/V caused by fringing electric field through thicker designed high-k dielectrics (EOT=1.0nm). Moreover, the VMOS can be designed by shorter gate length from 5.4 to 19nm as using higher gate dielectric constant from k=10 to k=60.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133523066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716531
Yanqing Zhang, B. Calhoun
This paper presents an ultra low power (ULP) solution to hold time closure for subthreshold circuits across PVT variation and mismatch using a two-phase, latch based timing method. We show that compared to conventional hold buffering, our solution saves up to 37% (at 6σ yield) in energy per operation and allows for post tapeout hold time correction. Replacing registers with latches also permits time borrowing, which we show can save up to 47% (6σ yield) when used for setup time closure.
{"title":"Hold time closure for subthreshold circuits using a two-phase, latch based timing method","authors":"Yanqing Zhang, B. Calhoun","doi":"10.1109/S3S.2013.6716531","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716531","url":null,"abstract":"This paper presents an ultra low power (ULP) solution to hold time closure for subthreshold circuits across PVT variation and mismatch using a two-phase, latch based timing method. We show that compared to conventional hold buffering, our solution saves up to 37% (at 6σ yield) in energy per operation and allows for post tapeout hold time correction. Replacing registers with latches also permits time borrowing, which we show can save up to 47% (6σ yield) when used for setup time closure.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122363039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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