Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716513
T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka
InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.
{"title":"3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS","authors":"T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka","doi":"10.1109/S3S.2013.6716513","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716513","url":null,"abstract":"InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126706909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716556
Odilon O. Dutra, Gustavo D. Colleta, L. H. C. Ferreira, T. Pimenta
This work describes a current mode implementation of Izhikevich neuron model implemented with halo implanted devices 130 nm structured within matrices of order m × n capable of substantially increasing output impedance of such devices while also improving mismatch. The proposed neuron was successfully simulated in 130 nm IBM CMOS process as the dynamical translinear circuit topology adopted generates the 20 patterns defined in Izhikevich model as other similar works while improving several aspects as the low supplied voltage used 250 mV.
这项工作描述了一种Izhikevich神经元模型的当前模式实现，该模型采用了在m × n阶矩阵内结构的130 nm的晕植入器件，能够大大增加此类器件的输出阻抗，同时也改善了失配。所提出的神经元在130 nm IBM CMOS工艺中成功仿真，所采用的动态跨线性电路拓扑产生了Izhikevich模型中定义的20种模式，并在250 mV的低电源电压下改进了几个方面。
{"title":"A sub-threshold halo implanted MOS implementation of Izhikevich neuron model","authors":"Odilon O. Dutra, Gustavo D. Colleta, L. H. C. Ferreira, T. Pimenta","doi":"10.1109/S3S.2013.6716556","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716556","url":null,"abstract":"This work describes a current mode implementation of Izhikevich neuron model implemented with halo implanted devices 130 nm structured within matrices of order m × n capable of substantially increasing output impedance of such devices while also improving mismatch. The proposed neuron was successfully simulated in 130 nm IBM CMOS process as the dynamical translinear circuit topology adopted generates the 20 patterns defined in Izhikevich model as other similar works while improving several aspects as the low supplied voltage used 250 mV.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121329233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716541
H. Koike, Chao Ma, M. Hioki, Y. Ogasahara, Takashi Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa
Flex Power FPGA uses body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. Low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption, one of the most serious issues in the modern FPGA, can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (Silicon On Thin BOX) device, which is renowned for its excellent Vt controllability. For the first time, SOTB version of the Flex Power FPGA test chip has been fabricated, and its functional test and performance evaluation have been performed successfully. In this paper, overview of this SOTB version test chip and its evaluation results are reported.
Flex Power FPGA采用体偏置技术在FPGA中实现细粒度阈值电压(Vt)可编程性。低vt状态只能分配给映射在FPGA上的应用设计关键路径上的器件电路，从而大幅降低现代FPGA中最严重的问题之一——静态泄漏功耗。Flex Power FPGA是SOTB (Silicon On Thin BOX)器件的重要应用目标，该器件以其出色的Vt可控性而闻名。首次制作了SOTB版本的Flex Power FPGA测试芯片，并成功进行了功能测试和性能评估。本文介绍了该SOTB版本测试芯片的概况和测试结果。
{"title":"The first SOTB implementation of Flex Power FPGA","authors":"H. Koike, Chao Ma, M. Hioki, Y. Ogasahara, Takashi Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa","doi":"10.1109/S3S.2013.6716541","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716541","url":null,"abstract":"Flex Power FPGA uses body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. Low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption, one of the most serious issues in the modern FPGA, can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (Silicon On Thin BOX) device, which is renowned for its excellent Vt controllability. For the first time, SOTB version of the Flex Power FPGA test chip has been fabricated, and its functional test and performance evaluation have been performed successfully. In this paper, overview of this SOTB version test chip and its evaluation results are reported.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127815271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716515
P. Batra, D. LaTulipe, S. Skordas, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He, Deepal Wehella Gamage, J. Golz, Wei Lin, T. Vo, D. Priyadarshini, A. Hubbard, Kristian Cauffman, B. Peethala, J. Barth, T. Kirihata, T. Graves-abe, N. Robson, S. Iyer
For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.
{"title":"Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology","authors":"P. Batra, D. LaTulipe, S. Skordas, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He, Deepal Wehella Gamage, J. Golz, Wei Lin, T. Vo, D. Priyadarshini, A. Hubbard, Kristian Cauffman, B. Peethala, J. Barth, T. Kirihata, T. Graves-abe, N. Robson, S. Iyer","doi":"10.1109/S3S.2013.6716515","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716515","url":null,"abstract":"For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124012036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716553
G. de Streel, D. Bol
Short-channel effects and variability in bulk technologies limit the interest of CMOS technology scaling for ultra-low-voltage (ULV) logic below 65nm because of the resulting penalty in the energy efficiency. FDSOI has already been predicted to be a good candidate to keep an excellent energy efficiency while increasing speed at ULV. In this paper, we confirm this result by synthesis results of microcontrollers at 0.35V. We show that the use of a mix of overdrive forward back biasing (FBB) voltages in 28nm FDSOI further improves the energy efficiency. Compare to bulk 65nm CMOS, we were able to reduce the energy per cycle by 64% or increase the frequency of operation by 7x while maintaining energy per operation below 3μW/MHz over a wide frequency range.
{"title":"Scaling perspectives of ULV microcontroller cores to 28nm UTBB FDSOI CMOS","authors":"G. de Streel, D. Bol","doi":"10.1109/S3S.2013.6716553","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716553","url":null,"abstract":"Short-channel effects and variability in bulk technologies limit the interest of CMOS technology scaling for ultra-low-voltage (ULV) logic below 65nm because of the resulting penalty in the energy efficiency. FDSOI has already been predicted to be a good candidate to keep an excellent energy efficiency while increasing speed at ULV. In this paper, we confirm this result by synthesis results of microcontrollers at 0.35V. We show that the use of a mix of overdrive forward back biasing (FBB) voltages in 28nm FDSOI further improves the energy efficiency. Compare to bulk 65nm CMOS, we were able to reduce the energy per cycle by 64% or increase the frequency of operation by 7x while maintaining energy per operation below 3μW/MHz over a wide frequency range.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121242768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716565
Afik Vaknin, O. Yona, A. Teman
Power supply scaling is one the most common and efficient approaches for achieving low-power operation, as both static and dynamic power consumption are aggressively reduced. Ultra-low power systems are often targeted at low-voltage operation, near or below the device threshold voltage (VT). However, the design of such systems must overcome the inherent reduction of noise margins associated with lowering the supply, and in particular, the depleted noise margins of standard SRAM circuits. The two-port 8T SRAM bitcell has been a popular choice for the implementation of low-voltage embedded memories, due to its decoupled read buffer that solves much of the read margin limitation of the standard 6T SRAM cell [1]. However, the 8T circuit is still limited by write margin, and in addition, does not support half-select operations, which are a requirement of many systems. Another disadvantage of the 6T and 8T circuits is that in standby, they present several transistors with relatively high leakage paths through them, leading to significant static power dissipation. In this paper, we propose a novel Double-Feedback SRAM (DF-SRAM) bitcell with improved write margins for low-voltage operation, reduced leakage for ultra-low power consumption, and improved half-select support.
{"title":"A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation","authors":"Afik Vaknin, O. Yona, A. Teman","doi":"10.1109/S3S.2013.6716565","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716565","url":null,"abstract":"Power supply scaling is one the most common and efficient approaches for achieving low-power operation, as both static and dynamic power consumption are aggressively reduced. Ultra-low power systems are often targeted at low-voltage operation, near or below the device threshold voltage (VT). However, the design of such systems must overcome the inherent reduction of noise margins associated with lowering the supply, and in particular, the depleted noise margins of standard SRAM circuits. The two-port 8T SRAM bitcell has been a popular choice for the implementation of low-voltage embedded memories, due to its decoupled read buffer that solves much of the read margin limitation of the standard 6T SRAM cell [1]. However, the 8T circuit is still limited by write margin, and in addition, does not support half-select operations, which are a requirement of many systems. Another disadvantage of the 6T and 8T circuits is that in standby, they present several transistors with relatively high leakage paths through them, leading to significant static power dissipation. In this paper, we propose a novel Double-Feedback SRAM (DF-SRAM) bitcell with improved write margins for low-voltage operation, reduced leakage for ultra-low power consumption, and improved half-select support.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128429264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716542
J. Le Coz, B. Pelloux-Prayer, B. Giraud, F. Giner, P. Flatresse
Ultra-Thin Body and Box (UTBB) Fully Depleted Silicon-On-Insulator (FD-SOI) Technology has become mainstream in the industry with the objective to serve a wide spectrum of mobile multimedia products [1]. Transistors (fig 1) are fabricated in a 7nm thin layer of silicon sitting (Tsi) over a 25nm buried oxide (Tbox). Thanks to its better electrostatic control [2]; UTBB FD-SOI technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. However, looking for a steady increase in performance for a voltage supply value constantly lowered with the evolution of technologies, BULK or FD-SOI, involves a decrease in the threshold voltage (Vt) and leads to an increase of the stand-by leakage current, requiring the implementation of a leakage current reduction technique.
{"title":"DTMOS power switch in 28 nm UTBB FD-SOI technology","authors":"J. Le Coz, B. Pelloux-Prayer, B. Giraud, F. Giner, P. Flatresse","doi":"10.1109/S3S.2013.6716542","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716542","url":null,"abstract":"Ultra-Thin Body and Box (UTBB) Fully Depleted Silicon-On-Insulator (FD-SOI) Technology has become mainstream in the industry with the objective to serve a wide spectrum of mobile multimedia products [1]. Transistors (fig 1) are fabricated in a 7nm thin layer of silicon sitting (Tsi) over a 25nm buried oxide (Tbox). Thanks to its better electrostatic control [2]; UTBB FD-SOI technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. However, looking for a steady increase in performance for a voltage supply value constantly lowered with the evolution of technologies, BULK or FD-SOI, involves a decrease in the threshold voltage (Vt) and leads to an increase of the stand-by leakage current, requiring the implementation of a leakage current reduction technique.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125767803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716543
E. Boufouss, P. Gérard, P. Simon, L. Francis, D. Flandre
A CMOS voltage reference circuit robust under harsh environments such as high temperature and high radiation total dose is presented. To achieve ultra-low-power and harsh environment operation, the voltage reference circuit is designed in a suitable 130 nm Silicon-on-Insulator technology and is optimized to work in sub-threshold regime of the transistors. The design simulations have been performed over all temperature ranges and process corners and with custom model parameters, including shifts in mobilities and threshold voltages caused by radiation effects. The measurements demonstrate a maximum drift of the mean reference voltage (1.5 V) lower than 5% at 1.5 Mrad (Si) total dose radiation. The typical power dissipation up to 200 °C is less than 75 μW at 2.5 V supply voltage. The total occupied area including pad-ring is less than 0.09 mm2.
{"title":"High temperature and radiation hard CMOS SOI sub-threshold voltage reference","authors":"E. Boufouss, P. Gérard, P. Simon, L. Francis, D. Flandre","doi":"10.1109/S3S.2013.6716543","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716543","url":null,"abstract":"A CMOS voltage reference circuit robust under harsh environments such as high temperature and high radiation total dose is presented. To achieve ultra-low-power and harsh environment operation, the voltage reference circuit is designed in a suitable 130 nm Silicon-on-Insulator technology and is optimized to work in sub-threshold regime of the transistors. The design simulations have been performed over all temperature ranges and process corners and with custom model parameters, including shifts in mobilities and threshold voltages caused by radiation effects. The measurements demonstrate a maximum drift of the mean reference voltage (1.5 V) lower than 5% at 1.5 Mrad (Si) total dose radiation. The typical power dissipation up to 200 °C is less than 75 μW at 2.5 V supply voltage. The total occupied area including pad-ring is less than 0.09 mm2.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131906848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716574
T. Imamoto, T. Endoh
Excellent thermal characteristics of the bulk vertical-channel bipor junction transistor (BJT) type 1T-DRAM compared to the SOI planar type with 20nm generation. The bulk vertical type can operate with the low increase of lattice temperature (ΔTLmax) of 26K and high enough read current margin of 1.8μA/cell, while the SOI planar type shows large ΔTLmax value of 58K.
{"title":"Suppression of self-heating effect employing bulk vertical-channel bipolar junction transistor (BJT) type capacitorless 1T-DRAM cell","authors":"T. Imamoto, T. Endoh","doi":"10.1109/S3S.2013.6716574","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716574","url":null,"abstract":"Excellent thermal characteristics of the bulk vertical-channel bipor junction transistor (BJT) type 1T-DRAM compared to the SOI planar type with 20nm generation. The bulk vertical type can operate with the low increase of lattice temperature (ΔT<sub>L</sub><sup>max</sup>) of 26K and high enough read current margin of 1.8μA/cell, while the SOI planar type shows large ΔT<sub>L</sub><sup>max</sup> value of 58K.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125757993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/S3S.2013.6716512
Z. Or-Bach
Three approaches to obtain monolithic 3D logic ICs are presented in this paper. RCAT - Process the high temperature on a generic structure prior to layer transfer (LT), and finish with cold processes; i.e., etch & depositions. Gate Replacement (Gate Last HKMG) - Process the high temperature on a repeating structure prior to LT, and finish with `gate replacement' cold processes. Laser Annealing - Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat. These approaches utilize well-known and manufacturing-friendly materials, process steps and device structures.
{"title":"Practical process flows for monolithic 3D","authors":"Z. Or-Bach","doi":"10.1109/S3S.2013.6716512","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716512","url":null,"abstract":"Three approaches to obtain monolithic 3D logic ICs are presented in this paper. RCAT - Process the high temperature on a generic structure prior to layer transfer (LT), and finish with cold processes; i.e., etch & depositions. Gate Replacement (Gate Last HKMG) - Process the high temperature on a repeating structure prior to LT, and finish with `gate replacement' cold processes. Laser Annealing - Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat. These approaches utilize well-known and manufacturing-friendly materials, process steps and device structures.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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