Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003291
C. Heitzinger, S. Selberherr
The formation and dissolution of Silicon self-interstitial clusters is linked to the phenomenon of TED (transient enhanced diffusion) which in turn has gained importance in the manufacturing of semiconductor devices. Based on theoretical considerations and measurements of the number of self-interstitial clusters during a thermal step we were interested in finding a suitable model for the formation and dissolution of self-interstitial clusters and extracting corresponding model parameters for two different technologies (i.e., material parameter sets). In order to automate the inverse modeling part a general optimization framework was used. Additional to solving this problem the same setup can solve a wide range of inverse modeling problems occurring in the domain of process simulation. Finally the results are discussed and compared with a previous model.
{"title":"A calibrated model for silicon self-interstitial cluster formation and dissolution","authors":"C. Heitzinger, S. Selberherr","doi":"10.1109/MIEL.2002.1003291","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003291","url":null,"abstract":"The formation and dissolution of Silicon self-interstitial clusters is linked to the phenomenon of TED (transient enhanced diffusion) which in turn has gained importance in the manufacturing of semiconductor devices. Based on theoretical considerations and measurements of the number of self-interstitial clusters during a thermal step we were interested in finding a suitable model for the formation and dissolution of self-interstitial clusters and extracting corresponding model parameters for two different technologies (i.e., material parameter sets). In order to automate the inverse modeling part a general optimization framework was used. Additional to solving this problem the same setup can solve a wide range of inverse modeling problems occurring in the domain of process simulation. Finally the results are discussed and compared with a previous model.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130025168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003359
N. Stojadinovic, S. Djoric-Veljkovic, I. Manic, V. Davidovic, S. Golubovic
The effects of pre-irradiation positive gate bias stress on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift and mobility reduction in stressed devices have been observed, clearly demonstrating inapplicability of gate bias stressing for radiation hardening of power VDMOSFETs.
{"title":"Effects of positive gate bias stress on radiation response in power VDMOSFETs","authors":"N. Stojadinovic, S. Djoric-Veljkovic, I. Manic, V. Davidovic, S. Golubovic","doi":"10.1109/MIEL.2002.1003359","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003359","url":null,"abstract":"The effects of pre-irradiation positive gate bias stress on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift and mobility reduction in stressed devices have been observed, clearly demonstrating inapplicability of gate bias stressing for radiation hardening of power VDMOSFETs.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115002269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003353
A. Sudnitson
The design of mixed synchronous/asynchronous digital systems presents several challenges to the designer. Not the least of these is demand of functional partitioning of initial descriptions at different levels of design process. In this work we propose partitioning technique of state-based descriptions at register-transfer level targeting the network of synchronous units which are interacting asynchronically. This paper is based on the observation that during the operation of a digital system, there are conditions such that the states of data processing sub-units do not change for some period of time.
{"title":"An approach to synthesis of mixed synchronous/asynchronous digital devices","authors":"A. Sudnitson","doi":"10.1109/MIEL.2002.1003353","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003353","url":null,"abstract":"The design of mixed synchronous/asynchronous digital systems presents several challenges to the designer. Not the least of these is demand of functional partitioning of initial descriptions at different levels of design process. In this work we propose partitioning technique of state-based descriptions at register-transfer level targeting the network of synchronous units which are interacting asynchronically. This paper is based on the observation that during the operation of a digital system, there are conditions such that the states of data processing sub-units do not change for some period of time.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132125418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003164
N. Nenadovic, V. Cuoco, S. Theeuwen, L. Nanver, H. Jos, J. Slotboom
A novel SOI vertical DMOS transistor on glass for RF power applications is proposed. The device has the same advantages as conventional LDMOS transistors over bipolar transistors with respect to the linearity and efficiency for the high-power, high-frequency applications and adds the advantages of silicon-on-anything technology for the integration with high quality passive components. The gate oxide degradation due to hot carrier generation is inherently eliminated. The metalization on the wafer back includes copper electroplating. A thick copper layer on the wafer back serves as an excellent heat spreader and heat sink. Moreover, it can be used to avoid debiasing due to voltage drops over the metalization. The device performance has been investigated using DC and AC MEDICI simulations and the "Smoothie" database model for FET devices. A device with a breakdown of more than 80 V, an f/sub Tmax/ of 8 GHz, a maximum current of more than 10/sup -4/ A//spl mu/m at V/sub DS/=26 V and an R/sub ON/ of 4m/spl Omega/cm/sup 2/ is demonstrated.
{"title":"A novel vertical DMOS transistor in SOA technology for RF-power applications","authors":"N. Nenadovic, V. Cuoco, S. Theeuwen, L. Nanver, H. Jos, J. Slotboom","doi":"10.1109/MIEL.2002.1003164","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003164","url":null,"abstract":"A novel SOI vertical DMOS transistor on glass for RF power applications is proposed. The device has the same advantages as conventional LDMOS transistors over bipolar transistors with respect to the linearity and efficiency for the high-power, high-frequency applications and adds the advantages of silicon-on-anything technology for the integration with high quality passive components. The gate oxide degradation due to hot carrier generation is inherently eliminated. The metalization on the wafer back includes copper electroplating. A thick copper layer on the wafer back serves as an excellent heat spreader and heat sink. Moreover, it can be used to avoid debiasing due to voltage drops over the metalization. The device performance has been investigated using DC and AC MEDICI simulations and the \"Smoothie\" database model for FET devices. A device with a breakdown of more than 80 V, an f/sub Tmax/ of 8 GHz, a maximum current of more than 10/sup -4/ A//spl mu/m at V/sub DS/=26 V and an R/sub ON/ of 4m/spl Omega/cm/sup 2/ is demonstrated.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003348
E.D. Manolov, A. Popov, N. Tchamov
The classic track-and-hold (T&H) circuits based on a diode-bridge feature known drawbacks: low-input impedance, limited slew-rate (SR) and input voltage swing, high-power consumption. To overcome those problems in this paper is proposed and analyzed a new T&H architecture. Tic diodes of the classic diode-bridge are replaced by transistors connected as emitter followers. Two buffers of unity-gain split up the bootstrap loop. PSPICE simulations with real transistor parameters demonstrate the advantages of the new circuit. The T&H waveforms of 5 MHz and 35 MHz input 2 V swing signal, sampled at 80 MHz, are shown. The results of slew-rate higher than 1400 V//spl mu/S, and power saving of above 10-20 times, compared with the conventional circuit, are obtained.
{"title":"An improved bridge track-and-hold circuit","authors":"E.D. Manolov, A. Popov, N. Tchamov","doi":"10.1109/MIEL.2002.1003348","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003348","url":null,"abstract":"The classic track-and-hold (T&H) circuits based on a diode-bridge feature known drawbacks: low-input impedance, limited slew-rate (SR) and input voltage swing, high-power consumption. To overcome those problems in this paper is proposed and analyzed a new T&H architecture. Tic diodes of the classic diode-bridge are replaced by transistors connected as emitter followers. Two buffers of unity-gain split up the bootstrap loop. PSPICE simulations with real transistor parameters demonstrate the advantages of the new circuit. The T&H waveforms of 5 MHz and 35 MHz input 2 V swing signal, sampled at 80 MHz, are shown. The results of slew-rate higher than 1400 V//spl mu/S, and power saving of above 10-20 times, compared with the conventional circuit, are obtained.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132967174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003169
G. Pope, P. Mawby
In this paper we report on Schottky diodes fabricated in 4H-SiC. The diodes fabricated utilized a three metal layer at the Schottky interface and a two metal layer at the back ohmic contact. Results are compared to diodes fabricated previously using a single metal layer at both Schottky and ohmic interfaces. Comparison shows an improvement in barrier height consistency, breakdown voltage and reverse leakage current. Boron implantation was used to increase reverse breakdown via an edge termination. Breakdown voltages in excess of the measurement equipment maximum of 1000 V were achieved by 40% of the fabricated diodes post implantation.
{"title":"Improved 4H-silicon carbide Schottky diodes using multiple metal alloy contacts","authors":"G. Pope, P. Mawby","doi":"10.1109/MIEL.2002.1003169","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003169","url":null,"abstract":"In this paper we report on Schottky diodes fabricated in 4H-SiC. The diodes fabricated utilized a three metal layer at the Schottky interface and a two metal layer at the back ohmic contact. Results are compared to diodes fabricated previously using a single metal layer at both Schottky and ohmic interfaces. Comparison shows an improvement in barrier height consistency, breakdown voltage and reverse leakage current. Boron implantation was used to increase reverse breakdown via an edge termination. Breakdown voltages in excess of the measurement equipment maximum of 1000 V were achieved by 40% of the fabricated diodes post implantation.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116601465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003163
S. Krishnan, E. M. Sankara Narayanan, Y.Z. Xu, F. Clough, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán
A novel high performance dual gated, glass compatible polycrystalline silicon HVTFT with blocking voltage in excess of 300 V is demonstrated. This device shows an order of magnitude improvement in the on-state performance in comparison to its offset drain (DG-OD) counterpart. The significantly enhanced performance of this dual gate device is due to an offset region doped through slots of reducing dimensions from the source (control gate) to the drain (sub-gate).
{"title":"Novel dual gate high voltage TFT with variable doping slot","authors":"S. Krishnan, E. M. Sankara Narayanan, Y.Z. Xu, F. Clough, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán","doi":"10.1109/MIEL.2002.1003163","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003163","url":null,"abstract":"A novel high performance dual gated, glass compatible polycrystalline silicon HVTFT with blocking voltage in excess of 300 V is demonstrated. This device shows an order of magnitude improvement in the on-state performance in comparison to its offset drain (DG-OD) counterpart. The significantly enhanced performance of this dual gate device is due to an offset region doped through slots of reducing dimensions from the source (control gate) to the drain (sub-gate).","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128875043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003308
R. García, M. Estrada, A. Cerdeira, L. Reséndiz
Reports low temperature polysilicon layers obtained by plasma enhanced crystallization performed in the same PECVD system where the a-Si:H layers are deposited. We analyze the effects of phosphorous concentration in the layer, hydrogen dilution of silane, temperature of the hydrogen plasma process and annealing temperature on the crystallization time, surface texture and resistivity of the layers. Layers were characterized electrically, by X-ray diffractometry and by atomic force microscopy. The characteristics of the polycrystalline films are discussed and compared with those of polycrystalline layers obtained by other methods.
{"title":"Process parameters affecting plasma enhanced crystallization of a-Si:H using a PECVD equipment [TFTs]","authors":"R. García, M. Estrada, A. Cerdeira, L. Reséndiz","doi":"10.1109/MIEL.2002.1003308","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003308","url":null,"abstract":"Reports low temperature polysilicon layers obtained by plasma enhanced crystallization performed in the same PECVD system where the a-Si:H layers are deposited. We analyze the effects of phosphorous concentration in the layer, hydrogen dilution of silane, temperature of the hydrogen plasma process and annealing temperature on the crystallization time, surface texture and resistivity of the layers. Layers were characterized electrically, by X-ray diffractometry and by atomic force microscopy. The characteristics of the polycrystalline films are discussed and compared with those of polycrystalline layers obtained by other methods.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127819212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003196
Z. Jakšić, Z. Djuric, O. Jakšić, V. Jovic, Z. Djinovic
We present a theoretical and experimental consideration of magnetoconcentration-based long-wavelength infrared photodetectors with nonequilibrium Auger-process suppression, designed for room-temperature operation. Our analysis includes the design, modeling and optimization of the detectors, their experimental fabrication and characterization. We used two narrow-bandgap direct semiconductors for our devices, indium antimonide (InSb) and mercury cadmium telluride (HgCdTe). We investigated all of the main properties of our detectors, including current-voltage characteristics, sensitivity, spectral noise, specific detectivity (D*) and response time. In our calculations we used our generalized expression for the absorption coefficient of HgCdTe that takes into account the influence of non-quantizing magnetic fields. Our experiments included more than a hundred magnetoconcentration devices. Thermal noise was decreased, specific detectivity increased and overall performance improved in most of our photodetectors.
{"title":"Ambient-temperature operation of nonequilibrium magnetoconcentration infrared detectors in InSb and HgCdTe","authors":"Z. Jakšić, Z. Djuric, O. Jakšić, V. Jovic, Z. Djinovic","doi":"10.1109/MIEL.2002.1003196","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003196","url":null,"abstract":"We present a theoretical and experimental consideration of magnetoconcentration-based long-wavelength infrared photodetectors with nonequilibrium Auger-process suppression, designed for room-temperature operation. Our analysis includes the design, modeling and optimization of the detectors, their experimental fabrication and characterization. We used two narrow-bandgap direct semiconductors for our devices, indium antimonide (InSb) and mercury cadmium telluride (HgCdTe). We investigated all of the main properties of our detectors, including current-voltage characteristics, sensitivity, spectral noise, specific detectivity (D*) and response time. In our calculations we used our generalized expression for the absorption coefficient of HgCdTe that takes into account the influence of non-quantizing magnetic fields. Our experiments included more than a hundred magnetoconcentration devices. Thermal noise was decreased, specific detectivity increased and overall performance improved in most of our photodetectors.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130427281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003332
E. Popovici, P. Fitzpatrick
This paper presents methods for improving the performance of a Reed-Solomon codec (encoder/decoder) so that it matches the requirements of high throughput/low power of an optical communication system. It is shown that by a careful selection of the underlying Galois field arithmetic architectures, and of the algorithms for finding the error locations and error values, the performance can be improved substantially over current techniques. We show that the symbol-parallel Fitzpatrick algorithm for solving the key equation uses 30% fewer multipliers than Berlekamp-Massey type architectures, thus achieving a cost reduction for the entire codec. The implementations are synthesised for Xilinx FPGAs and LSI lca 300 k array-of-gates technologies.
{"title":"Reed-Solomon codecs for optical communications","authors":"E. Popovici, P. Fitzpatrick","doi":"10.1109/MIEL.2002.1003332","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003332","url":null,"abstract":"This paper presents methods for improving the performance of a Reed-Solomon codec (encoder/decoder) so that it matches the requirements of high throughput/low power of an optical communication system. It is shown that by a careful selection of the underlying Galois field arithmetic architectures, and of the algorithms for finding the error locations and error values, the performance can be improved substantially over current techniques. We show that the symbol-parallel Fitzpatrick algorithm for solving the key equation uses 30% fewer multipliers than Berlekamp-Massey type architectures, thus achieving a cost reduction for the entire codec. The implementations are synthesised for Xilinx FPGAs and LSI lca 300 k array-of-gates technologies.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129823840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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