Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003302
L. Mao, Heqiu Zhang, Changhua Tan, Mingzhen Xu
Tunneling currents through ultrathin SiO/sub 2/ films have been observed to have small oscillatory components at high electric fields. In this article, a relation between the well known reflection coefficient and transmission coefficient of electron tunneling through a barrier and the amplitude of Fowler-Nordheim tunneling current oscillations is obtained based on the principle of quantum mechanics. A simple relation describing the factors affecting the amplitude of quantum oscillations is obtained based on the reflection coefficient and the transmission coefficient. It is found that the simple relation agrees well with the numerical results based on numerical calculations. A linear relation between the logarithmic attenuation of the oscillation amplitude and variable parameters such as barrier height, oxide thickness and the kinetic energy of incident electrons is observed. The results show that the oscillation amplitude attenuation can be accurately and simply described by this analytical solution.
{"title":"A simple theory to determine the attenuation amplitudes of quantum oscillations","authors":"L. Mao, Heqiu Zhang, Changhua Tan, Mingzhen Xu","doi":"10.1109/MIEL.2002.1003302","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003302","url":null,"abstract":"Tunneling currents through ultrathin SiO/sub 2/ films have been observed to have small oscillatory components at high electric fields. In this article, a relation between the well known reflection coefficient and transmission coefficient of electron tunneling through a barrier and the amplitude of Fowler-Nordheim tunneling current oscillations is obtained based on the principle of quantum mechanics. A simple relation describing the factors affecting the amplitude of quantum oscillations is obtained based on the reflection coefficient and the transmission coefficient. It is found that the simple relation agrees well with the numerical results based on numerical calculations. A linear relation between the logarithmic attenuation of the oscillation amplitude and variable parameters such as barrier height, oxide thickness and the kinetic energy of incident electrons is observed. The results show that the oscillation amplitude attenuation can be accurately and simply described by this analytical solution.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129561895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003366
D. Trémouilles, G. Bertrand, M. Bafleur, Felix Beaudoin, P. Perdu, N. Guitard, L. Lescouzères
The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and the shrinkage of their dimensions. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology.
{"title":"TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology","authors":"D. Trémouilles, G. Bertrand, M. Bafleur, Felix Beaudoin, P. Perdu, N. Guitard, L. Lescouzères","doi":"10.1109/MIEL.2002.1003366","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003366","url":null,"abstract":"The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and the shrinkage of their dimensions. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129946856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003329
S. Coric, I. Latinovic, A. Pavasovic
FPGA hardware implementation of three neurons is described, and their performances compared, mainly in the domain of speed and complexity.
描述了三种神经元的FPGA硬件实现，并比较了它们的性能，主要是在速度和复杂度方面。
{"title":"Design, implementation and comparison of three general-purpose neurons","authors":"S. Coric, I. Latinovic, A. Pavasovic","doi":"10.1109/MIEL.2002.1003329","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003329","url":null,"abstract":"FPGA hardware implementation of three neurons is described, and their performances compared, mainly in the domain of speed and complexity.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128644294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003144
P. Spirito, G. Breglio, V. d’Alessandro, N. Rinaldi
The phenomenon of the thermal instability presented by some high current power MOS has been intensively investigated, both by experimental means and by numerical simulations. An analytical expression for the positive temperature coefficient of the Drain current has been developed and a model for the thermal instability in transient operation has been proposed. The results explain the main causes of the thermal instability and give some rules to evaluate the possible failure occurrence for a given device.
{"title":"Thermal instabilities in high current power MOS devices: experimental evidence, electro-thermal simulations and analytical modeling","authors":"P. Spirito, G. Breglio, V. d’Alessandro, N. Rinaldi","doi":"10.1109/MIEL.2002.1003144","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003144","url":null,"abstract":"The phenomenon of the thermal instability presented by some high current power MOS has been intensively investigated, both by experimental means and by numerical simulations. An analytical expression for the positive temperature coefficient of the Drain current has been developed and a model for the thermal instability in transient operation has been proposed. The results explain the main causes of the thermal instability and give some rules to evaluate the possible failure occurrence for a given device.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129248651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003350
I. Milentijevic, I. Nikolic, V. Ciric, O. Vojinovic, T. Tokic
This paper describes the application of folding technique to the Bit-Plane systolic FIR filter Architecture (BPA). We present the transformation of original DFG (Data Flow Graph) that enables the application of folding technique and the synthesis of fully pipelined folded architecture. The array is restricted for the factor in, where in represents the coefficient length. The number of basic cells in target architecture is reduced to the number of basic cells in one plane of source architecture. Also, the total number of latches corresponds to the number of latches in one plane of the BPA. The hardware restriction is paid by decreasing of throughput for slightly more than in times.
{"title":"Synthesis of folded fully pipelined bit-plane architecture","authors":"I. Milentijevic, I. Nikolic, V. Ciric, O. Vojinovic, T. Tokic","doi":"10.1109/MIEL.2002.1003350","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003350","url":null,"abstract":"This paper describes the application of folding technique to the Bit-Plane systolic FIR filter Architecture (BPA). We present the transformation of original DFG (Data Flow Graph) that enables the application of folding technique and the synthesis of fully pipelined folded architecture. The array is restricted for the factor in, where in represents the coefficient length. The number of basic cells in target architecture is reduced to the number of basic cells in one plane of source architecture. Also, the total number of latches corresponds to the number of latches in one plane of the BPA. The hardware restriction is paid by decreasing of throughput for slightly more than in times.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126845726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003368
M. Pecovska-Gjorgjevich, N. Novkovski, E. Atanassova
Stress-induced leakage currents in thin Ta/sub 2/O/sub 5/ films were investigated after short term (6 s) and long term (2720 s) constant current stress at both gate polarities for different levels of injected current. Leakage currents were increasing and decreasing depending of the amount of injected charge, i.e. whether the U-t curve was at first, second or third stage of evaluation. The conduction mechanism was also investigated and the conclusion is that conductivity obeys Poole-Frenkel mechanism for fresh structures and modified Poole-Frenkel for stressed ones.
{"title":"Stress-induced leakage currents in thin Ta/sub 2/O/sub 5/ films","authors":"M. Pecovska-Gjorgjevich, N. Novkovski, E. Atanassova","doi":"10.1109/MIEL.2002.1003368","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003368","url":null,"abstract":"Stress-induced leakage currents in thin Ta/sub 2/O/sub 5/ films were investigated after short term (6 s) and long term (2720 s) constant current stress at both gate polarities for different levels of injected current. Leakage currents were increasing and decreasing depending of the amount of injected charge, i.e. whether the U-t curve was at first, second or third stage of evaluation. The conduction mechanism was also investigated and the conclusion is that conductivity obeys Poole-Frenkel mechanism for fresh structures and modified Poole-Frenkel for stressed ones.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129029730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003355
I. Vasiltsov, B. Mandziy, A. Bench
In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in choosing of the special area in the chip during mapping procedure at the packaging level. Usage of such approach allows for the designer to obtain a more optimal topology solution, and thus will increase the reliability of designed devices.
{"title":"Approach to solve the reliability problem at packaging level in the matrix VLSI","authors":"I. Vasiltsov, B. Mandziy, A. Bench","doi":"10.1109/MIEL.2002.1003355","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003355","url":null,"abstract":"In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in choosing of the special area in the chip during mapping procedure at the packaging level. Usage of such approach allows for the designer to obtain a more optimal topology solution, and thus will increase the reliability of designed devices.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121202927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003203
V. Grimalsky, J. Escobedo-Alatorre, M. Tecpoyotl-Torres, S. Koshevaya
This report deals with the non-linear effects on space charge waves (with phase velocity equal to the electron drift velocity) in GaAs semiconductors. If an external electric field is applied, at the critical field value E/sub crit/, the mobility changes its sign and becomes negative, as a result, there are obtained nonlinear and linear instabilities of the interactions at fields E/spl ges/E/sub crit/. Under these conditions, the electron velocity is a function of the electric field given by E=E/sub 0/+E/spl tilde/, where E/sub o/ is the constant part and E/spl tilde/ is the variable part. The simulation of the nonlinear interaction of space charge waves in the GaAs semiconductor is made considering both the Maxwell's equations and the velocity function.
{"title":"Non-linear interaction of space charge waves in GaAs semiconductor","authors":"V. Grimalsky, J. Escobedo-Alatorre, M. Tecpoyotl-Torres, S. Koshevaya","doi":"10.1109/MIEL.2002.1003203","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003203","url":null,"abstract":"This report deals with the non-linear effects on space charge waves (with phase velocity equal to the electron drift velocity) in GaAs semiconductors. If an external electric field is applied, at the critical field value E/sub crit/, the mobility changes its sign and becomes negative, as a result, there are obtained nonlinear and linear instabilities of the interactions at fields E/spl ges/E/sub crit/. Under these conditions, the electron velocity is a function of the electric field given by E=E/sub 0/+E/spl tilde/, where E/sub o/ is the constant part and E/spl tilde/ is the variable part. The simulation of the nonlinear interaction of space charge waves in the GaAs semiconductor is made considering both the Maxwell's equations and the velocity function.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114228081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003299
N. Jankovic, T. Pesic, J. Karamarković
A compact 1D non-quasi-static BJT model (NQS BJT) based on the analog behavioral modeling capabilities of the SPICE simulator is described. The NQS BJT model parameters are derived directly from the physical device structure. A momentum relaxation time parameter is also included as equivalent inductivity, yielding more accurate prediction of unity gain frequency and phase characteristics. The efficiency of the novel NQS model is demonstrated by comparison with the standard Gummel-Poon model and experimental results.
{"title":"1D physically based non-quasi-static analog behavioral BJT model for SPICE","authors":"N. Jankovic, T. Pesic, J. Karamarković","doi":"10.1109/MIEL.2002.1003299","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003299","url":null,"abstract":"A compact 1D non-quasi-static BJT model (NQS BJT) based on the analog behavioral modeling capabilities of the SPICE simulator is described. The NQS BJT model parameters are derived directly from the physical device structure. A momentum relaxation time parameter is also included as equivalent inductivity, yielding more accurate prediction of unity gain frequency and phase characteristics. The efficiency of the novel NQS model is demonstrated by comparison with the standard Gummel-Poon model and experimental results.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130106322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003370
J. Sikula, L. Štourač
The noise spectroscopy in time and frequency domain is used to give information on single carrier trapping and charge carrier transport in MOSFETs, quantum dots, conducting film resistors, capacitors and single crystals. Defects in the vicinity of the p-n junction and MOS channel create 1/f noise, burst noise or RTS noise. The sources of fluctuation are quantum transitions of carriers between localised states and energy bands, carrier number and mobility. Noise reliability indicators are used to assess the device quality and reliability.
{"title":"Noise spectroscopy of semiconductor materials and devices","authors":"J. Sikula, L. Štourač","doi":"10.1109/MIEL.2002.1003370","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003370","url":null,"abstract":"The noise spectroscopy in time and frequency domain is used to give information on single carrier trapping and charge carrier transport in MOSFETs, quantum dots, conducting film resistors, capacitors and single crystals. Defects in the vicinity of the p-n junction and MOS channel create 1/f noise, burst noise or RTS noise. The sources of fluctuation are quantum transitions of carriers between localised states and energy bands, carrier number and mobility. Noise reliability indicators are used to assess the device quality and reliability.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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