Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003343
D. M. Maksimovi, V. Litovski
We propose an original method for timing simulation within a VHDL logic simulator framework. This method enables standard VHDL simulator to evaluate the longest path delays to all the signals in the circuit with only one run of the logic simulator. Timing simulation is performed at simulation time t=0 at the cost of a negligible increase of CPU time needed for the simulation. Results of the timing simulation of the ISCAS'85 benchmark circuits with a VHDL simulator are presented that prove that the proposed method is extremely efficient and appropriate for interactive use in the early phases of the design process where timing analysis needs to be repeated as the circuit design is optimized or refined.
{"title":"Timing simulation with VHDL simulators","authors":"D. M. Maksimovi, V. Litovski","doi":"10.1109/MIEL.2002.1003343","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003343","url":null,"abstract":"We propose an original method for timing simulation within a VHDL logic simulator framework. This method enables standard VHDL simulator to evaluate the longest path delays to all the signals in the circuit with only one run of the logic simulator. Timing simulation is performed at simulation time t=0 at the cost of a negligible increase of CPU time needed for the simulation. Results of the timing simulation of the ISCAS'85 benchmark circuits with a VHDL simulator are presented that prove that the proposed method is extremely efficient and appropriate for interactive use in the early phases of the design process where timing analysis needs to be repeated as the circuit design is optimized or refined.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116865604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003371
Z. Chobola, A. Ibrahim, Z. Růžička
Low frequency capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements were performed on monocrystalline silicon solar cells with a 100 cm/sup 2/ area. The deep level transient spectroscopy (DLTS) technique is a good technique for detecting the majority carrier traps by thermal emission and emission of carriers at deep energy levels which are located in the space charge region (SCR) of a p-n junction or Schottky barrier. The space charge region is essentially depleted of mobile carriers and hence is very much like the bulk insulators.
{"title":"C-V and DLTS as characterization tools for silicon solar cells","authors":"Z. Chobola, A. Ibrahim, Z. Růžička","doi":"10.1109/MIEL.2002.1003371","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003371","url":null,"abstract":"Low frequency capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements were performed on monocrystalline silicon solar cells with a 100 cm/sup 2/ area. The deep level transient spectroscopy (DLTS) technique is a good technique for detecting the majority carrier traps by thermal emission and emission of carriers at deep energy levels which are located in the space charge region (SCR) of a p-n junction or Schottky barrier. The space charge region is essentially depleted of mobile carriers and hence is very much like the bulk insulators.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126966233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003142
E. M. Sankara Narayanan, N. Moguilnaia, K. Vershinin, M. Sweet, S. Hardikar, L. Ngwendson, O. Spulber, M. M. De Souza
Power microelectronics plays a pivotal role in many of the consumer and industrial applications today. With increase in demand for energy savings and efficient systems, the requirements for rapid advancement in MOS controlled power semiconductor device concepts and technologies is becoming more crucial than ever before. This puts a considerable pressure on industries to be innovative and competitive at the device, technology, manufacturing and marketing levels. The aim of this paper is to explore these aspects.
{"title":"Innovation and competition: are they crucial in power semiconductor industry? A market perspective","authors":"E. M. Sankara Narayanan, N. Moguilnaia, K. Vershinin, M. Sweet, S. Hardikar, L. Ngwendson, O. Spulber, M. M. De Souza","doi":"10.1109/MIEL.2002.1003142","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003142","url":null,"abstract":"Power microelectronics plays a pivotal role in many of the consumer and industrial applications today. With increase in demand for energy savings and efficient systems, the requirements for rapid advancement in MOS controlled power semiconductor device concepts and technologies is becoming more crucial than ever before. This puts a considerable pressure on industries to be innovative and competitive at the device, technology, manufacturing and marketing levels. The aim of this paper is to explore these aspects.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121653478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003354
E. Fomina, A. Keevallik, A. Sudnitson
The synthesis of circuits with reduced power consumption has grown more and more important over the last years. In this paper, we address the problem of reduction of power dissipation using dynamic power management techniques. The problem of low power synthesis corresponds to an optimal decomposition of a finite state machine reduced to choice of partitions on the set of states of prototype machine. For evaluation of the networks, the informational modeling based on entropy measure is considered. It enables one to enhance the decomposition partition search for low power synthesis.
{"title":"Low power synthesis based on information theoretic measures","authors":"E. Fomina, A. Keevallik, A. Sudnitson","doi":"10.1109/MIEL.2002.1003354","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003354","url":null,"abstract":"The synthesis of circuits with reduced power consumption has grown more and more important over the last years. In this paper, we address the problem of reduction of power dissipation using dynamic power management techniques. The problem of low power synthesis corresponds to an optimal decomposition of a finite state machine reduced to choice of partitions on the set of states of prototype machine. For evaluation of the networks, the informational modeling based on entropy measure is considered. It enables one to enhance the decomposition partition search for low power synthesis.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122747946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003324
V.M. Tousi, F. Sahandi, M. Atarodi, M. Shojaei
A single-chip Integrated circuit of 3.3 V/1 W class-D high fidelity and high efficiency audio power amplifier is presented in this paper. The design has been done using a 3.3 V/0.25 /spl mu/m CMOS process. The maximum output power is 1 W before the amplifier saturates. The THD+N at 0.5 W output power is below 0.03% and efficiency is better than 90% thanks to the careful design of the output stage. The dynamic range is more than 100 dB suitable for high fidelity audio applications. A single-loop single-bit third order sigma-delta modulator is used to generate the PWM signal from input audio signal. The PWM signal is then filtered at the output with a second order low pass filter external to the chip to regenerate the input signal.
{"title":"A 3.3 V/1 W class D audio power amplifier with 103 dB DR and 90% efficiency","authors":"V.M. Tousi, F. Sahandi, M. Atarodi, M. Shojaei","doi":"10.1109/MIEL.2002.1003324","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003324","url":null,"abstract":"A single-chip Integrated circuit of 3.3 V/1 W class-D high fidelity and high efficiency audio power amplifier is presented in this paper. The design has been done using a 3.3 V/0.25 /spl mu/m CMOS process. The maximum output power is 1 W before the amplifier saturates. The THD+N at 0.5 W output power is below 0.03% and efficiency is better than 90% thanks to the careful design of the output stage. The dynamic range is more than 100 dB suitable for high fidelity audio applications. A single-loop single-bit third order sigma-delta modulator is used to generate the PWM signal from input audio signal. The PWM signal is then filtered at the output with a second order low pass filter external to the chip to regenerate the input signal.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121525897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003212
B. Radojcic, R. Ramović, O. Aleksic
Describes the results of parallel thermal analysis of hybrid and SMT modules. 2D thermal model is presented in brief Theoretical analysis, modelling and simulation of temperature distribution were done for the realized hybrid module (containing thick film and chip components). Simulations of temperature distribution in the realized hybrid module were done taking into account the larger thermal power sources. The experimental part (3D model) is based on thermal measurements of the realized hybrid and SMT modules, using a matrix of flip-chip sensors. Thermal measurements were done at different ambient temperatures and different hybrid and SMT module power values. The obtained simulation and experimental results for the hybrid module are graphically presented. Also, experimental results obtained for the SMT and hybrid module at different ambient temperatures and power loads were compared and analyzed.
{"title":"Parallel thermal analysis of hybrid and SMT modules using 2D and 3D models","authors":"B. Radojcic, R. Ramović, O. Aleksic","doi":"10.1109/MIEL.2002.1003212","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003212","url":null,"abstract":"Describes the results of parallel thermal analysis of hybrid and SMT modules. 2D thermal model is presented in brief Theoretical analysis, modelling and simulation of temperature distribution were done for the realized hybrid module (containing thick film and chip components). Simulations of temperature distribution in the realized hybrid module were done taking into account the larger thermal power sources. The experimental part (3D model) is based on thermal measurements of the realized hybrid and SMT modules, using a matrix of flip-chip sensors. Thermal measurements were done at different ambient temperatures and different hybrid and SMT module power values. The obtained simulation and experimental results for the hybrid module are graphically presented. Also, experimental results obtained for the SMT and hybrid module at different ambient temperatures and power loads were compared and analyzed.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125064754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003141
K. Shenai
The electric power generated from various sources (oil, gas, fossil fuels, nuclear sources, etc.) flows through long transmission lines and is eventually tapped by various loads from the electric utility grids. The same electric power flows through a host of electronic appliances, including those that power the Internet. In every electronic device, wired or wireless, semiconductor microchips are present and consume a significant amount of this electric energy. The cost, performance and reliability of this "PowerNet" are of paramount importance in this century since they ultimately decide the quality of information and life. This paper will discuss the current status and emerging trends in key semiconductor power electronic switching devices used in the PowerNet at various stages of power conditioning.
{"title":"Semiconductor technologies for powering micro chips in the information age: from source to load","authors":"K. Shenai","doi":"10.1109/MIEL.2002.1003141","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003141","url":null,"abstract":"The electric power generated from various sources (oil, gas, fossil fuels, nuclear sources, etc.) flows through long transmission lines and is eventually tapped by various loads from the electric utility grids. The same electric power flows through a host of electronic appliances, including those that power the Internet. In every electronic device, wired or wireless, semiconductor microchips are present and consume a significant amount of this electric energy. The cost, performance and reliability of this \"PowerNet\" are of paramount importance in this century since they ultimately decide the quality of information and life. This paper will discuss the current status and emerging trends in key semiconductor power electronic switching devices used in the PowerNet at various stages of power conditioning.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003199
S. Koshevaya, V. Grimalsky, I. Moroz, A. Torres-Jácome, O. Pustynik, M. Tecpoyotl-Torres
A modulator on the base of a surface oriented p-i-n structure in an oversize waveguide is researched theoretically and experimentally. It uses a matrix surface oriented structure with "deep" contacts which is like a window in oversize waveguides of the millimeter frequency range. This modulator is also the electrically controlled lens of the microwave branch.
{"title":"Modulator on the base of surface oriented integrated p-i-n structure in the oversize waveguide","authors":"S. Koshevaya, V. Grimalsky, I. Moroz, A. Torres-Jácome, O. Pustynik, M. Tecpoyotl-Torres","doi":"10.1109/MIEL.2002.1003199","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003199","url":null,"abstract":"A modulator on the base of a surface oriented p-i-n structure in an oversize waveguide is researched theoretically and experimentally. It uses a matrix surface oriented structure with \"deep\" contacts which is like a window in oversize waveguides of the millimeter frequency range. This modulator is also the electrically controlled lens of the microwave branch.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123217832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003364
Vladislav Vashchenko, Peter J. Hopper
A 2D simulation approach that takes into account the 3D effects of electro-thermal instability during ESD operation, has been presented. The method is used to provide physical evaluation of a safe operation regime of ESD protection structures and circuits. First results of ESD stress induced hot spot formation using 3D simulation have been presented for the case of a simplified snapback n-MOS device.
{"title":"Simulation of Si-Ge BiCMOS ESD structures operation including spatial current instability mode","authors":"Vladislav Vashchenko, Peter J. Hopper","doi":"10.1109/MIEL.2002.1003364","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003364","url":null,"abstract":"A 2D simulation approach that takes into account the 3D effects of electro-thermal instability during ESD operation, has been presented. The method is used to provide physical evaluation of a safe operation regime of ESD protection structures and circuits. First results of ESD stress induced hot spot formation using 3D simulation have been presented for the case of a simplified snapback n-MOS device.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/MIEL.2002.1003333
R. Ubar, J. Raik, E. Ivask, M. Brik
A new method for mixed level fault simulation of Data-Paths in Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gateand RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.
{"title":"Mixed-level defect simulation in data-paths of digital systems","authors":"R. Ubar, J. Raik, E. Ivask, M. Brik","doi":"10.1109/MIEL.2002.1003333","DOIUrl":"https://doi.org/10.1109/MIEL.2002.1003333","url":null,"abstract":"A new method for mixed level fault simulation of Data-Paths in Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gateand RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128259645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：