Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783054
M. Manik, E. Gramatová
The paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. The developed algorithms are based on the symmetric diagnostics model at system level. Effectiveness and complexity of the implemented algorithms were evaluated by experiments over several regular computing architectures (hypercube, torus, 2-dimensional grid). The achieved results were compared to existing diagnostics algorithms at system level.
{"title":"Efficient diagnostics algorithms for regular computing structures","authors":"M. Manik, E. Gramatová","doi":"10.1109/DDECS.2011.5783054","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783054","url":null,"abstract":"The paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. The developed algorithms are based on the symmetric diagnostics model at system level. Effectiveness and complexity of the implemented algorithms were evaluated by experiments over several regular computing architectures (hypercube, torus, 2-dimensional grid). The achieved results were compared to existing diagnostics algorithms at system level.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123350576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783051
Michal Lukaszewicz, T. Borejko, W. Pleskacz
A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 55 ppm/°C temperature coefficient over range of −40 °C to 125 °C. Reference current susceptibility to process parameters variation is ±3 %. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than −127 dB and −103 dB, respectively.
{"title":"A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations","authors":"Michal Lukaszewicz, T. Borejko, W. Pleskacz","doi":"10.1109/DDECS.2011.5783051","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783051","url":null,"abstract":"A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 55 ppm/°C temperature coefficient over range of −40 °C to 125 °C. Reference current susceptibility to process parameters variation is ±3 %. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than −127 dB and −103 dB, respectively.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123525004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783104
J. Matoušek, Pavol Korcek
This paper presents an architecture of a hardware network packet generator designed for the COMBOv2 cards using the NetCOPE development platform. The packet generator internal structure allows synthetic IPv4 and IPv6 network packet creation as well as the real network packet transmission. Based on COMBOv2 add-on interface card, the generator is able to transmit packets at speed of 2×10 Gbit/s or 4×1 Gbit/s. Synthetic data are created using high quality pseudo-random number generator. If desired, previously captured network packets can be transmitted back to the network with exactly the same time drift as were captured. This is accomplished by extremely precise timestamps, which can be generated by the Timestamp Module included in the NetCOPE platform.
{"title":"Precise IPv4/IPv6 packet generator based on NetCOPE platform","authors":"J. Matoušek, Pavol Korcek","doi":"10.1109/DDECS.2011.5783104","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783104","url":null,"abstract":"This paper presents an architecture of a hardware network packet generator designed for the COMBOv2 cards using the NetCOPE development platform. The packet generator internal structure allows synthetic IPv4 and IPv6 network packet creation as well as the real network packet transmission. Based on COMBOv2 add-on interface card, the generator is able to transmit packets at speed of 2×10 Gbit/s or 4×1 Gbit/s. Synthetic data are created using high quality pseudo-random number generator. If desired, previously captured network packets can be transmitted back to the network with exactly the same time drift as were captured. This is accomplished by extremely precise timestamps, which can be generated by the Timestamp Module included in the NetCOPE platform.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"133 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128686351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783079
Hans Kristian Otnes Berge, Amir Hasanbegovic, S. Aunet
Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation based on 2-input nand, 2-input nor and invert functions. For room temperature and a supply voltage of 150mV, the simulated delays for the 12T and 24T implementations were 16.2 µs and 18.5 µs, respectively. The mean static power consumption figures were for the same conditions 2.6pW and 7.4pW, for the 12T and 24T implementations respectively. Switching energy was also simulated for a 150mV supply voltage. The switching energy for the 12T version of the Muller C-element was almost 44% lower compared to the 24T implementation. We also report delay, power and energy for a supply voltage of 300mV.
{"title":"Muller C-elements based on minority-3 functions for ultra low voltage supplies","authors":"Hans Kristian Otnes Berge, Amir Hasanbegovic, S. Aunet","doi":"10.1109/DDECS.2011.5783079","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783079","url":null,"abstract":"Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation based on 2-input nand, 2-input nor and invert functions. For room temperature and a supply voltage of 150mV, the simulated delays for the 12T and 24T implementations were 16.2 µs and 18.5 µs, respectively. The mean static power consumption figures were for the same conditions 2.6pW and 7.4pW, for the 12T and 24T implementations respectively. Switching energy was also simulated for a 150mV supply voltage. The switching energy for the 12T version of the Muller C-element was almost 44% lower compared to the 24T implementation. We also report delay, power and energy for a supply voltage of 300mV.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783088
Carmen Garcia, A. Rubio
In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon nanotubes (CNTs). The goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and its potential capability to be a promising alternative to Si-CMOS technology. The impact of the carbon nanotube diameter variations as well as the presence of metallic carbon nanotubes in the transistor are analyzed (device level). This variability model is used to make a comparison between Si-MOSFET and CNFET Static Random Access Memory (SRAM) 6T cells (circuit level).
{"title":"Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario","authors":"Carmen Garcia, A. Rubio","doi":"10.1109/DDECS.2011.5783088","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783088","url":null,"abstract":"In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon nanotubes (CNTs). The goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and its potential capability to be a promising alternative to Si-CMOS technology. The impact of the carbon nanotube diameter variations as well as the presence of metallic carbon nanotubes in the transistor are analyzed (device level). This variability model is used to make a comparison between Si-MOSFET and CNFET Static Random Access Memory (SRAM) 6T cells (circuit level).","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783049
F. Chouard, S. More, M. Fulde, D. Schmitt-Landsiedel
An assessment on analog circuit reliability for an advanced 32nm high-κ metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. Thereupon a general approach to consider device aging for analog circuit reliability is proposed.
{"title":"An analog perspective on device reliability in 32nm high-κ metal gate technology","authors":"F. Chouard, S. More, M. Fulde, D. Schmitt-Landsiedel","doi":"10.1109/DDECS.2011.5783049","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783049","url":null,"abstract":"An assessment on analog circuit reliability for an advanced 32nm high-κ metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. Thereupon a general approach to consider device aging for analog circuit reliability is proposed.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"122 S163","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132904975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783036
K. Einwich
The SystemC AMS extensions standard was published nearly one year ago. The industrial adoption has been started. The tutorial will give a comprehensive overview about the motivation, the language and her usage for different application domains like telecommunication and automotive.
{"title":"Introduction to the SystemC AMS extension standard","authors":"K. Einwich","doi":"10.1109/DDECS.2011.5783036","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783036","url":null,"abstract":"The SystemC AMS extensions standard was published nearly one year ago. The industrial adoption has been started. The tutorial will give a comprehensive overview about the motivation, the language and her usage for different application domains like telecommunication and automotive.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124313350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783077
Hagen Sämrow, C. Cornelius, Philipp Gorski, J. Salzmann, Andreas Tockhorn, D. Timmermann
Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.
{"title":"Functional enhancements of TMR for power efficient and error resilient ASIC designs","authors":"Hagen Sämrow, C. Cornelius, Philipp Gorski, J. Salzmann, Andreas Tockhorn, D. Timmermann","doi":"10.1109/DDECS.2011.5783077","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783077","url":null,"abstract":"Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130954940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783045
Xuan-Tu Tran, Van-Huan Tran
In this paper, we present a low cost Forward Transform and Quantization (FTQ) implementation for H.264/AVC encoders in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4∶2∶0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755µm2 (approximate 15KGates), with the 130nm TSMC CMOS technology.
{"title":"Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders","authors":"Xuan-Tu Tran, Van-Huan Tran","doi":"10.1109/DDECS.2011.5783045","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783045","url":null,"abstract":"In this paper, we present a low cost Forward Transform and Quantization (FTQ) implementation for H.264/AVC encoders in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4∶2∶0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755µm2 (approximate 15KGates), with the 130nm TSMC CMOS technology.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115979898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783044
Sumit Adhikari, Muhammad Farooq, Jan Haase, C. Grimm
Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. The new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (ΣΔ) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, kBT/CS noise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain nonlinearity, slew rate, leakage and saturation effect). The ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a ΣΔ ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.
{"title":"High performance adaptive sensor interface design through model based estimation of analog non-idealities","authors":"Sumit Adhikari, Muhammad Farooq, Jan Haase, C. Grimm","doi":"10.1109/DDECS.2011.5783044","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783044","url":null,"abstract":"Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. The new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (ΣΔ) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, kBT/CS noise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain nonlinearity, slew rate, leakage and saturation effect). The ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a ΣΔ ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128661501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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