Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044922
D. Cartasegna, P. Malcovati, L. Crespi, Kyehyung Lee, Lakshmi Murukutla, A. Baschirotto
Class-D amplifiers exhibit high efficiency in spite of their simple implementation and, therefore, they are often used in portable devices with typical THD performance of the order of −65 dB. Presently, the possibility of using class-D amplifiers in applications requiring better THD (THD < −85 dB) is being investigated, in consideration of their possible application in huge markets (like high-performance audio). For this reason, the THD performance of conventional class-D structures is not enough and new topologies have to be analyzed and implemented. In this paper, high-order class-D structures have been investigated to achieve the target THD performance. Among them, we selected a 3rd-order fully-differential class-D amplifier, which has been implemented in a 0.18-μm CMOS technology, starting from a previously available 1st-order class-D structure. The measurements on the realized 3rd-order device show a THD ≈ −91 dB with −1 dBFS input signal, about 30 dB better than the 1st-order structure.
{"title":"An audio 91-dB THD third-order fully-differential class-D amplifier","authors":"D. Cartasegna, P. Malcovati, L. Crespi, Kyehyung Lee, Lakshmi Murukutla, A. Baschirotto","doi":"10.1109/ESSCIRC.2011.6044922","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044922","url":null,"abstract":"Class-D amplifiers exhibit high efficiency in spite of their simple implementation and, therefore, they are often used in portable devices with typical THD performance of the order of −65 dB. Presently, the possibility of using class-D amplifiers in applications requiring better THD (THD < −85 dB) is being investigated, in consideration of their possible application in huge markets (like high-performance audio). For this reason, the THD performance of conventional class-D structures is not enough and new topologies have to be analyzed and implemented. In this paper, high-order class-D structures have been investigated to achieve the target THD performance. Among them, we selected a 3rd-order fully-differential class-D amplifier, which has been implemented in a 0.18-μm CMOS technology, starting from a previously available 1st-order class-D structure. The measurements on the realized 3rd-order device show a THD ≈ −91 dB with −1 dBFS input signal, about 30 dB better than the 1st-order structure.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127222288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045001
Q. Khan, Sachin Rao, Damian Swank, A. Rao, W. McIntyre, Sarvesh Bang, P. Hanumolu
A digitally controlled Buck-Boost converter uses a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output over a 3.3V-to-5.5V input voltage range. The proposed architecture does not use either a high resolution digital pulse width modulator or an analog to digital converter. Fabricated in a 500nm CMOS process, the prototype achieves a peak efficiency of 92% at 500mA load current. The use of a smaller inductor and no external compensation capacitor makes the proposed solution highly cost effective.
{"title":"A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control","authors":"Q. Khan, Sachin Rao, Damian Swank, A. Rao, W. McIntyre, Sarvesh Bang, P. Hanumolu","doi":"10.1109/ESSCIRC.2011.6045001","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045001","url":null,"abstract":"A digitally controlled Buck-Boost converter uses a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output over a 3.3V-to-5.5V input voltage range. The proposed architecture does not use either a high resolution digital pulse width modulator or an analog to digital converter. Fabricated in a 500nm CMOS process, the prototype achieves a peak efficiency of 92% at 500mA load current. The use of a smaller inductor and no external compensation capacitor makes the proposed solution highly cost effective.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123165255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045000
Weiwei Xu, Ye Li, Zhiliang Hong, D. Killat, H. Schleifer
Specified for one output channel 1V to 4V, the second one 1.8V to 4V and the last one 0V to −1.8V, a prototype of single-inductor multiple-bipolar-output (SIMBO) DC-DC converter performed on 0.25-μm CMOS mixed signal process is presented. Fully-adaptive feedback matrix in pulse-width modulation (PWM) control to suppress cross regulation and constant-voltage-ripple pulse-frequency modulation (PFM) control to achieve fair light-load ripple for various conversion mode and wide-range conversion ratio are proposed. This converter can automatically switch between PWM and PFM control. The peak conversion efficiency is close to 90%.
{"title":"A single-inductor multiple-bipolar-output (SIMBO) converter with fully-adaptive feedback matrix and improved light-load ripple","authors":"Weiwei Xu, Ye Li, Zhiliang Hong, D. Killat, H. Schleifer","doi":"10.1109/ESSCIRC.2011.6045000","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045000","url":null,"abstract":"Specified for one output channel 1V to 4V, the second one 1.8V to 4V and the last one 0V to −1.8V, a prototype of single-inductor multiple-bipolar-output (SIMBO) DC-DC converter performed on 0.25-μm CMOS mixed signal process is presented. Fully-adaptive feedback matrix in pulse-width modulation (PWM) control to suppress cross regulation and constant-voltage-ripple pulse-frequency modulation (PFM) control to achieve fair light-load ripple for various conversion mode and wide-range conversion ratio are proposed. This converter can automatically switch between PWM and PFM control. The peak conversion efficiency is close to 90%.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123856798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044241
L. Fulbert, J. Fédéli
Silicon photonics has generated an outstanding interest for optical communications and for inter and intra-chip interconnects in electronic systems. High performance generic building blocks that can be used for a broad range of applications have already been demonstrated such as waveguides, I/O couplers, laser sources by III-V/Si heterogeneous integration, fast silicon modulators and germanium photodetectors. The paper will also review the different scenarios for integrating photonic functions with an electronic circuit, as well as the associated design, test and packaging challenges.
{"title":"Photonics — Electronics integration on CMOS","authors":"L. Fulbert, J. Fédéli","doi":"10.1109/ESSDERC.2011.6044241","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044241","url":null,"abstract":"Silicon photonics has generated an outstanding interest for optical communications and for inter and intra-chip interconnects in electronic systems. High performance generic building blocks that can be used for a broad range of applications have already been demonstrated such as waveguides, I/O couplers, laser sources by III-V/Si heterogeneous integration, fast silicon modulators and germanium photodetectors. The paper will also review the different scenarios for integrating photonic functions with an electronic circuit, as well as the associated design, test and packaging challenges.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122072384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045008
Dai Zhang, Ameya Bhide, A. Alvandpour
This paper describes an ultra-low-power SAR ADC in 0.13-μm CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-μm CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.
{"title":"A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices","authors":"Dai Zhang, Ameya Bhide, A. Alvandpour","doi":"10.1109/ESSCIRC.2011.6045008","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045008","url":null,"abstract":"This paper describes an ultra-low-power SAR ADC in 0.13-μm CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-μm CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117016967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044926
C. Niclass, M. Soga, H. Matsubara, S. Kato
This paper introduces a high-performance optical depth sensor in a 0.18μm CMOS technology. At the core of the sensor, macro pixels consisting of 6×2 single-photon detectors enable accurate and selective time-of-flight measurements by taking advantage of temporal and spatial correlations of photons. An array of 32 high-throughput time-to-digital converters allows for the digitization of time-of-flight data with a resolution of 208ps within a range of 853ns, thus resolving distances up to 128 meters. Quantitative characterization of the chip sensor is reported. Depth map data acquired in a real-world situation illustrates the effectiveness of the approach in a road traffic environment.
{"title":"A 100m-range 10-frame/s 340×96-pixel time-of-flight depth sensor in 0.18μm CMOS","authors":"C. Niclass, M. Soga, H. Matsubara, S. Kato","doi":"10.1109/ESSCIRC.2011.6044926","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044926","url":null,"abstract":"This paper introduces a high-performance optical depth sensor in a 0.18μm CMOS technology. At the core of the sensor, macro pixels consisting of 6×2 single-photon detectors enable accurate and selective time-of-flight measurements by taking advantage of temporal and spatial correlations of photons. An array of 32 high-throughput time-to-digital converters allows for the digitization of time-of-flight data with a resolution of 208ps within a range of 853ns, thus resolving distances up to 128 meters. Quantitative characterization of the chip sensor is reported. Depth map data acquired in a real-world situation illustrates the effectiveness of the approach in a road traffic environment.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115495826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044944
Jong‐Wook Lee, D. H. Vo, Sang-Hoon Hong, Quoc-Hung Huynh
We present a fully-integrated compact (1.1 mm2) target device for Near Field Communication (NFC). The design of the key analog part of the tag IC is presented, which includes a robust demodulator for 10% ASK envelope detection, a high-quality random number generator, an adaptive RF limiter, and a low power clock generator. A 128 bit advanced encryption standard (AES) with new cyclic key generation is used for secure data encryption and decryption. An on-chip 4Kb EEPROM is used to support the AES operation. The tag chip is fabricated in a 1-poly 6-metal low-power (LP) 0.18 μm CMOS process with a CoSi2-Schottky diode and EEPROM process.
{"title":"A fully integrated high security NFC target IC using 0.18 μm CMOS process","authors":"Jong‐Wook Lee, D. H. Vo, Sang-Hoon Hong, Quoc-Hung Huynh","doi":"10.1109/ESSCIRC.2011.6044944","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044944","url":null,"abstract":"We present a fully-integrated compact (1.1 mm2) target device for Near Field Communication (NFC). The design of the key analog part of the tag IC is presented, which includes a robust demodulator for 10% ASK envelope detection, a high-quality random number generator, an adaptive RF limiter, and a low power clock generator. A 128 bit advanced encryption standard (AES) with new cyclic key generation is used for secure data encryption and decryption. An on-chip 4Kb EEPROM is used to support the AES operation. The tag chip is fabricated in a 1-poly 6-metal low-power (LP) 0.18 μm CMOS process with a CoSi2-Schottky diode and EEPROM process.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129840761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044987
Tzu-Chi Huang, W. Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Y. Peng, F. Hsueh
This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.
{"title":"55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter","authors":"Tzu-Chi Huang, W. Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Y. Peng, F. Hsueh","doi":"10.1109/ESSCIRC.2011.6044987","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044987","url":null,"abstract":"This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044947
K. Abdelhalim, R. Genov
A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915MHz OOK/FSK closed-loop wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54dB of gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5μV and a CMRR of 78dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters that enable precise separation of various bands in the neural spectrum. The 915MHz FSK/OOK transmitter offers data rates up to 1.5Mbps with a maximum output power of 0dBm. The 4×3mm chip fabricated in a 0.13μm CMOS process dissipates 5.03mW from a 1.2V supply.
{"title":"915-MHz wireless 64-channel neural recording SoC with programmable mixed-signal FIR filters","authors":"K. Abdelhalim, R. Genov","doi":"10.1109/ESSCIRC.2011.6044947","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044947","url":null,"abstract":"A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915MHz OOK/FSK closed-loop wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54dB of gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5μV and a CMRR of 78dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters that enable precise separation of various bands in the neural spectrum. The 915MHz FSK/OOK transmitter offers data rates up to 1.5Mbps with a maximum output power of 0dBm. The 4×3mm chip fabricated in a 0.13μm CMOS process dissipates 5.03mW from a 1.2V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117249072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044982
U. Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, U. Seng-Pan, R. Martins
This paper reports a 7-bit 300-MS/s subranging ADC fabricated in standard 65nm CMOS, which utilizes embedded reference and gain loss error calibration techniques. A shared passive capacitive DAC array performs the input sampling in quantization mode and reference generation in calibration mode, providing a linear, accurate and compact calibration implementation. As a consequence of the developed calibration techniques, uniform-sized dynamic comparators are employed to reduce the process-mismatch variation and nonlinearity error, when compared with the conventional structures. The ADC achieves peak SNDR of 40.5dB at 300MS/s and 39dB at 400MS/s, with ERBW of 300MHz and 350MHz, respectively. The power consumption is 2.3mW only from 1.2-V supply at 300MS/s.
{"title":"A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration","authors":"U. Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/ESSCIRC.2011.6044982","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044982","url":null,"abstract":"This paper reports a 7-bit 300-MS/s subranging ADC fabricated in standard 65nm CMOS, which utilizes embedded reference and gain loss error calibration techniques. A shared passive capacitive DAC array performs the input sampling in quantization mode and reference generation in calibration mode, providing a linear, accurate and compact calibration implementation. As a consequence of the developed calibration techniques, uniform-sized dynamic comparators are employed to reduce the process-mismatch variation and nonlinearity error, when compared with the conventional structures. The ADC achieves peak SNDR of 40.5dB at 300MS/s and 39dB at 400MS/s, with ERBW of 300MHz and 350MHz, respectively. The power consumption is 2.3mW only from 1.2-V supply at 300MS/s.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127756002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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