In high speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on- chip methodology to measure jitter in time domain, with resolutions up to 0.1 ps.
{"title":"On Chip Jitter Measurement through a High Accuracy TDC","authors":"A. Garg, P. Dubey","doi":"10.1109/ISQED.2008.68","DOIUrl":"https://doi.org/10.1109/ISQED.2008.68","url":null,"abstract":"In high speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on- chip methodology to measure jitter in time domain, with resolutions up to 0.1 ps.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121260113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as compared to SPICE. The regions where ground coupling and source/drain coupling dominate are described based on this model. The impact of multiple parameters such as the rise time, number of switching gates, decoupling capacitance, and parasitic inductance on the dominant noise coupling mechanism is investigated. The dominance of ground coupling in large scale circuits, as generally assumed, is shown to be invalid if sufficient decoupling capacitance is used or the circuit exhibits a low parasitic inductance such as a flip-chip package. The efficacy of several noise reduction techniques is discussed based on the application of the dominant noise analysis model.
{"title":"Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates","authors":"E. Salman, E. Friedman, R. Secareanu, O. Hartin","doi":"10.1109/ISQED.2008.55","DOIUrl":"https://doi.org/10.1109/ISQED.2008.55","url":null,"abstract":"The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as compared to SPICE. The regions where ground coupling and source/drain coupling dominate are described based on this model. The impact of multiple parameters such as the rise time, number of switching gates, decoupling capacitance, and parasitic inductance on the dominant noise coupling mechanism is investigated. The dominance of ground coupling in large scale circuits, as generally assumed, is shown to be invalid if sufficient decoupling capacitance is used or the circuit exhibits a low parasitic inductance such as a flip-chip package. The efficacy of several noise reduction techniques is discussed based on the application of the dominant noise analysis model.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117303612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yiran Chen, Xiaobin Wang, Hai Helen Li, Harry Liu, D. Dimitrov
We proposed a combined magnetic and circuit level technique to explore the design methodology of Spin-Torque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling junction (MTJ), which is based upon measured spin torque induced magnetization switching behavior, is also proposed. The response of CMOS circuitry is characterized by SPICE and used as the input of our MTJ model to simulate the dynamic behavior of SPRAM cell. By using this technique, we explored the design margin of SPRAM cell with one-transistor-one-MTJ (ITU) structure. Simulation results show that our technique can significantly reduce the design pessimism, compared to conventional SRPAM cell model.
{"title":"Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)","authors":"Yiran Chen, Xiaobin Wang, Hai Helen Li, Harry Liu, D. Dimitrov","doi":"10.1109/ISQED.2008.140","DOIUrl":"https://doi.org/10.1109/ISQED.2008.140","url":null,"abstract":"We proposed a combined magnetic and circuit level technique to explore the design methodology of Spin-Torque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling junction (MTJ), which is based upon measured spin torque induced magnetization switching behavior, is also proposed. The response of CMOS circuitry is characterized by SPICE and used as the input of our MTJ model to simulate the dynamic behavior of SPRAM cell. By using this technique, we explored the design margin of SPRAM cell with one-transistor-one-MTJ (ITU) structure. Simulation results show that our technique can significantly reduce the design pessimism, compared to conventional SRPAM cell model.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128620832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new charge pump circuit to minimize the current mismatch. By connecting a common-gate and a common-source amplifier as the feedback voltage regulator, the highly matched charge pump currents are accomplished. Additionally, the proposed circuit has wide output voltage swing, which ensures its good performance under very low power supply.
{"title":"High Output Resistance and Wide Swing Voltage Charge Pump Circuit","authors":"T. Xia, S. Wyatt","doi":"10.1109/ISQED.2008.60","DOIUrl":"https://doi.org/10.1109/ISQED.2008.60","url":null,"abstract":"This paper presents a new charge pump circuit to minimize the current mismatch. By connecting a common-gate and a common-source amplifier as the feedback voltage regulator, the highly matched charge pump currents are accomplished. Additionally, the proposed circuit has wide output voltage swing, which ensures its good performance under very low power supply.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131303491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to weaknesses in circuit synthesis methods used in today's CAD tools, the opportunities created by modern microelectronic technology cannot effectively be exploited. This paper considers the issues and requirements of circuit synthesis for the nano CMOS technologies, and discusses our new circuit synthesis technology that satisfies these requirements. The new technology considerably differs from all other known synthesis methods and overcomes their main weaknesses. The experimental results demonstrate that it produces very fast, compact and low-power circuits. The new technology has however many more major advantages that are discussed in the paper.
{"title":"High-Quality Circuit Synthesis for Modern Technologies","authors":"L. Józwiak, A. Chojnacki, A. Slusarczyk","doi":"10.1109/ISQED.2008.37","DOIUrl":"https://doi.org/10.1109/ISQED.2008.37","url":null,"abstract":"Due to weaknesses in circuit synthesis methods used in today's CAD tools, the opportunities created by modern microelectronic technology cannot effectively be exploited. This paper considers the issues and requirements of circuit synthesis for the nano CMOS technologies, and discusses our new circuit synthesis technology that satisfies these requirements. The new technology considerably differs from all other known synthesis methods and overcomes their main weaknesses. The experimental results demonstrate that it produces very fast, compact and low-power circuits. The new technology has however many more major advantages that are discussed in the paper.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123437404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As process geometries are shrinking, width of the metal layer is continuously decreasing, height of the layer and wire lengths are increasing, thereby increasing the effect of coupling capacitances. Coupling induced crosstalk may induce unwanted noise on coupled signal nets resulting in functional failure and performance degradation and becomes a significant limitation in achieving first pass silicon success. At the same time the complexity of noise analysis has significantly increased due to factors such as driver weakening, IR drop, power network switching, voltage scaling and variations in manufacturing processes. Therefore validating the capabilities and verifying the analysis of a crosstalk analysis tool for current and future process nodes is very critical for efficient and accurate signoff analysis. The modeling of the cell itself needs to be accurate and comprehensive. The objective of the paper is to share the methodology and challenges involved in crosstalk noise analysis and how the composite current source (CCS) based crosstalk noise analysis capability of primetime SI would help us achieve many of our goals.
{"title":"Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation","authors":"C. R. Venugopal, Prasanth Soraiyur, J. Rao","doi":"10.1109/ISQED.2008.170","DOIUrl":"https://doi.org/10.1109/ISQED.2008.170","url":null,"abstract":"As process geometries are shrinking, width of the metal layer is continuously decreasing, height of the layer and wire lengths are increasing, thereby increasing the effect of coupling capacitances. Coupling induced crosstalk may induce unwanted noise on coupled signal nets resulting in functional failure and performance degradation and becomes a significant limitation in achieving first pass silicon success. At the same time the complexity of noise analysis has significantly increased due to factors such as driver weakening, IR drop, power network switching, voltage scaling and variations in manufacturing processes. Therefore validating the capabilities and verifying the analysis of a crosstalk analysis tool for current and future process nodes is very critical for efficient and accurate signoff analysis. The modeling of the cell itself needs to be accurate and comprehensive. The objective of the paper is to share the methodology and challenges involved in crosstalk noise analysis and how the composite current source (CCS) based crosstalk noise analysis capability of primetime SI would help us achieve many of our goals.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126515733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Symbolic simulation-based approach is viable for the sequential equivalence checking (SEC) of SLM-vs.-RTL. However, it can't avoid the storage explosion introduced by the explosion of the BDD sizes for large designs. For scalability, we introduce two kinds of decomposition techniques: One is the equivalence checking oriented program slicing; the other is the hierarchical insertion of logic cut- points. And a 2D decomposition SEC method of SLM-vs.-RTL is presented. "2D decomposition" means decomposition in the space dimension and the time dimension. The verification model is only built for the program slices of a single output variable for each time, which limits the usage of memory. During checking the equivalence of the program slices, the logic cutpoints are inserted to split the verification model of the program slices in the time dimension, which controls the storage explosion further. The promising experimental results demonstrate the benefits brought by our 2D decomposition method.
{"title":"2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions","authors":"Dan Zhu, Tun Li, Yang Guo, Sikun Li","doi":"10.1109/ISQED.2008.58","DOIUrl":"https://doi.org/10.1109/ISQED.2008.58","url":null,"abstract":"Symbolic simulation-based approach is viable for the sequential equivalence checking (SEC) of SLM-vs.-RTL. However, it can't avoid the storage explosion introduced by the explosion of the BDD sizes for large designs. For scalability, we introduce two kinds of decomposition techniques: One is the equivalence checking oriented program slicing; the other is the hierarchical insertion of logic cut- points. And a 2D decomposition SEC method of SLM-vs.-RTL is presented. \"2D decomposition\" means decomposition in the space dimension and the time dimension. The verification model is only built for the program slices of a single output variable for each time, which limits the usage of memory. During checking the equivalence of the program slices, the logic cutpoints are inserted to split the verification model of the program slices in the time dimension, which controls the storage explosion further. The promising experimental results demonstrate the benefits brought by our 2D decomposition method.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126740186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In 2006, the leading wireless phone industry has introduced literally hundreds of new, different wireless phones, which have been manufactured in approximately 1 billion units, generating revenue of about $128B. The semiconductor revenue has been about $33B. The ASP is declining, both in the wireless phone and semiconductor industry. In order to fix that, Moore's Law is being inverted: instead of getting twice the transistors for the same cost, the wireless phones industry seeks to obtain the same number of transistors for half the cost. This is making system-on-chip (SoC) no longer a viable solution. System-in-package (SiP) looks much more promising. Lack of EDA solutions - especially the A of automation - has so far slowed down the ramp-up of SiP. In this paper we describe the landscape and present a SiP platform solution which addresses the challenges of simplification, cost reduction, quality and reliability improvement, yet allowing exploiting the most recent advances in IC packaging.
{"title":"System-in-Package Technology: Opportunities and Challenges","authors":"A. Fontanelli","doi":"10.1109/ISQED.2008.63","DOIUrl":"https://doi.org/10.1109/ISQED.2008.63","url":null,"abstract":"In 2006, the leading wireless phone industry has introduced literally hundreds of new, different wireless phones, which have been manufactured in approximately 1 billion units, generating revenue of about $128B. The semiconductor revenue has been about $33B. The ASP is declining, both in the wireless phone and semiconductor industry. In order to fix that, Moore's Law is being inverted: instead of getting twice the transistors for the same cost, the wireless phones industry seeks to obtain the same number of transistors for half the cost. This is making system-on-chip (SoC) no longer a viable solution. System-in-package (SiP) looks much more promising. Lack of EDA solutions - especially the A of automation - has so far slowed down the ramp-up of SiP. In this paper we describe the landscape and present a SiP platform solution which addresses the challenges of simplification, cost reduction, quality and reliability improvement, yet allowing exploiting the most recent advances in IC packaging.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115820401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Global Warming is hot! Climate change is occurring all around us, and the scientific evidence is increasingly overwhelming pointing to man's hand in the phenomena. We are already seeing huge impacts of Climate Change, much faster than anybody predicted, only a few short years ago. What can we do about? How can we slow and even reverse our impact on Climate Change? The key man made contributing factor is carbon emissions, primarily from coal fired power plants. We need to reduce the number of plants that we building, then the number of power plants that we require.The key to this is a reduction in power consumption.There are many everyday actions we can take individually to help. Al Gore states that Global Warming is an engineering problem that will be solved by engineers, addressing the issue as an opportunity, rather than additional cost. We will explore how engineers will impact Climate Change. Low power IC design techniques will play a role in this just as new powerful techniques are coming into vogue.
{"title":"Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The World","authors":"R. Goldman","doi":"10.1109/ISQED.2008.180","DOIUrl":"https://doi.org/10.1109/ISQED.2008.180","url":null,"abstract":"Global Warming is hot! Climate change is occurring all around us, and the scientific evidence is increasingly overwhelming pointing to man's hand in the phenomena. We are already seeing huge impacts of Climate Change, much faster than anybody predicted, only a few short years ago. What can we do about? How can we slow and even reverse our impact on Climate Change? The key man made contributing factor is carbon emissions, primarily from coal fired power plants. We need to reduce the number of plants that we building, then the number of power plants that we require.The key to this is a reduction in power consumption.There are many everyday actions we can take individually to help. Al Gore states that Global Warming is an engineering problem that will be solved by engineers, addressing the issue as an opportunity, rather than additional cost. We will explore how engineers will impact Climate Change. Low power IC design techniques will play a role in this just as new powerful techniques are coming into vogue.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A complete function-based scheme is presented to identify at-speed sequentially untestable path delay faults. We introduce signature variables to implicitly track error propagation through combinational and sequential circuits. The path sensitization test functions are encoded with the signature variables. These encoded test functions allow implicit identification of all propagating transitions corresponding to each individual test function minterm. We then utilize the signature variables during the fault propagation in a way such that the latched error propagates robustly to an observable point irrespective of other latched errors. Results presented on the ISCAS'89 benchmarks show a large number of sequentially untestable path delay faults are identified.
{"title":"Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures","authors":"E. Flanigan, Arkan Abdulrahman, S. Tragoudas","doi":"10.1109/ISQED.2008.76","DOIUrl":"https://doi.org/10.1109/ISQED.2008.76","url":null,"abstract":"A complete function-based scheme is presented to identify at-speed sequentially untestable path delay faults. We introduce signature variables to implicitly track error propagation through combinational and sequential circuits. The path sensitization test functions are encoded with the signature variables. These encoded test functions allow implicit identification of all propagating transitions corresponding to each individual test function minterm. We then utilize the signature variables during the fault propagation in a way such that the latched error propagates robustly to an observable point irrespective of other latched errors. Results presented on the ISCAS'89 benchmarks show a large number of sequentially untestable path delay faults are identified.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115095606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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