With decreasing process nodes and increasing design density, crosstalk analysis is a must for getting design closure in the UDSM era. In addition to this, while crosstalk analysis is complex in itself, the new process nodes are showing increasing variations of process parameters for devices and interconnect. This in turn adds more complexity to crosstalk analysis. Standard techniques of factoring in the effects of process variations (corner-based analysis) is particularly ineffective for crosstalk analysis, so we need to look at techniques of statistical analysis of crosstalk in a manner similar to that used for timing. We look at a basic infrastructure for doing statistical crosstalk analysis - and look at how it can incorporate the effects of variations in cell variations and on aggressor slew. We also look at aggressor window clustering as a technique to reduce pessimism in crosstalk - and see how this technique can be modified to take in the effect of process variations. We lay the theoretical framework for these techniques in this paper, and show the results of a prototype implementation on real designs. We show that using this framework and techniques shows a close correlation with Monte-Carlo simulations.
{"title":"Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping","authors":"Sachin Shrivastava, H. Parameswaran","doi":"10.1109/ISQED.2008.20","DOIUrl":"https://doi.org/10.1109/ISQED.2008.20","url":null,"abstract":"With decreasing process nodes and increasing design density, crosstalk analysis is a must for getting design closure in the UDSM era. In addition to this, while crosstalk analysis is complex in itself, the new process nodes are showing increasing variations of process parameters for devices and interconnect. This in turn adds more complexity to crosstalk analysis. Standard techniques of factoring in the effects of process variations (corner-based analysis) is particularly ineffective for crosstalk analysis, so we need to look at techniques of statistical analysis of crosstalk in a manner similar to that used for timing. We look at a basic infrastructure for doing statistical crosstalk analysis - and look at how it can incorporate the effects of variations in cell variations and on aggressor slew. We also look at aggressor window clustering as a technique to reduce pessimism in crosstalk - and see how this technique can be modified to take in the effect of process variations. We lay the theoretical framework for these techniques in this paper, and show the results of a prototype implementation on real designs. We show that using this framework and techniques shows a close correlation with Monte-Carlo simulations.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"23 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120965407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel design of address pointer for FIFO memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true single-phase clock, and double- edge-triggering clock scheme. The circuit has low power consumption, is immune to circuit racing conditions and suitable for high-speed operations. Techniques to implement clock gating in pointer circuit design for further reducing power consumption are also discussed. The proposed circuit is implemented with a 65 nm CMOS technology and its performance is compared with previous pointer circuits.
{"title":"A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design","authors":"Saravanan Ramamoorthy, Haibo Wang, S. Vrudhula","doi":"10.1109/ISQED.2008.129","DOIUrl":"https://doi.org/10.1109/ISQED.2008.129","url":null,"abstract":"This paper presents a novel design of address pointer for FIFO memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true single-phase clock, and double- edge-triggering clock scheme. The circuit has low power consumption, is immune to circuit racing conditions and suitable for high-speed operations. Techniques to implement clock gating in pointer circuit design for further reducing power consumption are also discussed. The proposed circuit is implemented with a 65 nm CMOS technology and its performance is compared with previous pointer circuits.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130889778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay was optimized from 355 to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also optimized, of which the critical path delay was reduced from 152 to 103 ps which accounts for a 32.23% delay improvement, and delay uncertainty was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay and the power-delay-product were optimized to 632 ps and 84.17 pJ, respectively.
{"title":"Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic","authors":"K. Yelamarthi, C. Chen","doi":"10.1109/ISQED.2008.157","DOIUrl":"https://doi.org/10.1109/ISQED.2008.157","url":null,"abstract":"A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay was optimized from 355 to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also optimized, of which the critical path delay was reduced from 152 to 103 ps which accounts for a 32.23% delay improvement, and delay uncertainty was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay and the power-delay-product were optimized to 632 ps and 84.17 pJ, respectively.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134417259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clock tree analysis and signoff is a key step in the design of any high performance chip. Though simple and intutive metrics like skew have been used to track clock tree quality, they are not sufficient for most practical purposes. Ideally, skew distribution obtained using a SSTA (Statististical Static Timing Analysis) on the clock trees can be used. But in most practical cases, the process information assumed by SSTA is not available. As a result, the signoff of clock skew robustness to variation effects is an often difficult problem to solve. In this work, we propose two metrics that can address this issue. These metrics can be used in three important ways. First, they can be used to determine during CTS whether the clock tree is good enough to go through rest of the backend flow or whether more tuning needs to be done to the clock tree. Second, they can be used to isolate any parts of the clock tree that behaves like a hot spot for clock skew across corners. Third, it can be used as a final signoff metric for clock tree to ensure that the tracking of the delays and skews can be expected to be good across all process points. We provide several experimental results from industry testcases demonstrating the utility of our metrics.
{"title":"Practical Clock Tree Robustness Signoff Metrics","authors":"A. Rajaram, R. Damodaran, A. Rajagopal","doi":"10.1109/ISQED.2008.171","DOIUrl":"https://doi.org/10.1109/ISQED.2008.171","url":null,"abstract":"Clock tree analysis and signoff is a key step in the design of any high performance chip. Though simple and intutive metrics like skew have been used to track clock tree quality, they are not sufficient for most practical purposes. Ideally, skew distribution obtained using a SSTA (Statististical Static Timing Analysis) on the clock trees can be used. But in most practical cases, the process information assumed by SSTA is not available. As a result, the signoff of clock skew robustness to variation effects is an often difficult problem to solve. In this work, we propose two metrics that can address this issue. These metrics can be used in three important ways. First, they can be used to determine during CTS whether the clock tree is good enough to go through rest of the backend flow or whether more tuning needs to be done to the clock tree. Second, they can be used to isolate any parts of the clock tree that behaves like a hot spot for clock skew across corners. Third, it can be used as a final signoff metric for clock tree to ensure that the tracking of the delays and skews can be expected to be good across all process points. We provide several experimental results from industry testcases demonstrating the utility of our metrics.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129822660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance (Ceff) of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variation on the effective capacitance of bus lines and to evaluate the percentage delay reduction due to proposed coding scheme.
{"title":"Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects","authors":"C. Raghunandan, K. S. Sainarayanan, M. Srinivas","doi":"10.1109/ISQED.2008.121","DOIUrl":"https://doi.org/10.1109/ISQED.2008.121","url":null,"abstract":"Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance (Ceff) of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variation on the effective capacitance of bus lines and to evaluate the percentage delay reduction due to proposed coding scheme.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently VLSI IC design is concerned with the large temperature non-uniformity in high power chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which have caused the use of conservative margins in thermal designs. Transient temperature characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time for the chip-level thermal simulations, we have developed a matrix convolution technique, called the Power Blurring (PB) method. Our method renders the temperature profile of a packaged IC with maximum error less than 3% for several case studies done and reduces the computation time by a factor of 100, compared to the simulations done by the industry standard finite element tools.
{"title":"Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages","authors":"Je-Hyoung Park, A. Shakouri, S. Kang","doi":"10.1109/ISQED.2008.95","DOIUrl":"https://doi.org/10.1109/ISQED.2008.95","url":null,"abstract":"Recently VLSI IC design is concerned with the large temperature non-uniformity in high power chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which have caused the use of conservative margins in thermal designs. Transient temperature characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time for the chip-level thermal simulations, we have developed a matrix convolution technique, called the Power Blurring (PB) method. Our method renders the temperature profile of a packaged IC with maximum error less than 3% for several case studies done and reduces the computation time by a factor of 100, compared to the simulations done by the industry standard finite element tools.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114097538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, K. Unlu
Radiation induced soft errors have become an important reliability concern in the sub-nanometer regime. Therefore, it is imperative to devise methods to predict the soft error rates (SER) quickly and accurately in combinational circuits. In this paper, we present a novel technique and a tool to compute the SERs of designs employing hierarchical architectures such as adders and multipliers. The technique uses pre-characterized blocks for current generation and propagation and probability theory to estimate the SER in hierarchical architectures. The analysis results of different hierarchical architectures, based on characterization of basic blocks such as muxes, counters and partial product generators using the new technique, are presented in this paper. The run time for most of the designs were in the order of few minutes and we obtain an average speedup of 14084X times over HSPICE and 12.25X times over a contemporary tool SEAT-LA. We have also demonstrated the scalability of our technique for various hierarchical circuits. Our technique can also be extended to any block based architecture.
{"title":"Hierarchical Soft Error Estimation Tool (HSEET)","authors":"K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, K. Unlu","doi":"10.1109/ISQED.2008.164","DOIUrl":"https://doi.org/10.1109/ISQED.2008.164","url":null,"abstract":"Radiation induced soft errors have become an important reliability concern in the sub-nanometer regime. Therefore, it is imperative to devise methods to predict the soft error rates (SER) quickly and accurately in combinational circuits. In this paper, we present a novel technique and a tool to compute the SERs of designs employing hierarchical architectures such as adders and multipliers. The technique uses pre-characterized blocks for current generation and propagation and probability theory to estimate the SER in hierarchical architectures. The analysis results of different hierarchical architectures, based on characterization of basic blocks such as muxes, counters and partial product generators using the new technique, are presented in this paper. The run time for most of the designs were in the order of few minutes and we obtain an average speedup of 14084X times over HSPICE and 12.25X times over a contemporary tool SEAT-LA. We have also demonstrated the scalability of our technique for various hierarchical circuits. Our technique can also be extended to any block based architecture.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114207788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power dissipation in long interconnects and increasing wire temperatures due to (self) Joule heating are becoming important issues to address in nanometer-scale technologies. While many low-power bus encoding schemes have been proposed, no encoding techniques exist for explicitly reducing temperatures in high-speed on-chip signal buses. In this work, we propose: (1) an interconnect/wire signaling and layout optimization that considers self and inter-wire coupling activities and is tailored to data traffic characteristics; (2) an integer linear programming (ILP) technique to optimize bus energy and; (3) a novel methodology to add thermal constraints to this ILP optimization to reduce not only average but also peak wire temperatures. Our contributions enable a designer to efficiently explore the hottest wire temperature and total bus dynamic energy trade-off space. One such trade-off point yielded a thermally-constrained, energy-optimal encoding scheme that reduced wire temperatures by up to 12.26degC (12.96degC) for data (instruction) buses and significant average energy savings of 14.24% (16.17%) for data (instruction) bus. These results are still much better than energy reductions obtained by previous work.
{"title":"Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses","authors":"Krishnan Sundaresan, N. Mahapatra","doi":"10.1109/ISQED.2008.101","DOIUrl":"https://doi.org/10.1109/ISQED.2008.101","url":null,"abstract":"Power dissipation in long interconnects and increasing wire temperatures due to (self) Joule heating are becoming important issues to address in nanometer-scale technologies. While many low-power bus encoding schemes have been proposed, no encoding techniques exist for explicitly reducing temperatures in high-speed on-chip signal buses. In this work, we propose: (1) an interconnect/wire signaling and layout optimization that considers self and inter-wire coupling activities and is tailored to data traffic characteristics; (2) an integer linear programming (ILP) technique to optimize bus energy and; (3) a novel methodology to add thermal constraints to this ILP optimization to reduce not only average but also peak wire temperatures. Our contributions enable a designer to efficiently explore the hottest wire temperature and total bus dynamic energy trade-off space. One such trade-off point yielded a thermally-constrained, energy-optimal encoding scheme that reduced wire temperatures by up to 12.26degC (12.96degC) for data (instruction) buses and significant average energy savings of 14.24% (16.17%) for data (instruction) bus. These results are still much better than energy reductions obtained by previous work.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121846560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test stimulus and response compaction (scan compression) in scan is increasingly becoming an integral part of today's design-for-test (DFT) methodology for achieving high quality test at lower costs. Current generation integrated circuit's (ICs) are very complex designs that produce a large number of unknown values (Xs) during response capture in scan testing. Response compaction techniques have been shown to be very effective in dealing with any distribution of the Xs while not compromising on the test coverage. However, as the number of scan in pins reduce, the X-tolerance capability of these techniques degrades rapidly. In this paper we discuss interval based response compaction scheme for scan compression architectures. We present an analysis to show that very high X-tolerance can be achieved with a small number of scan-in pins and with no loss of test coverage. We also show that this eventually translates into higher compression ratio and lower test data volume.
{"title":"Interval Based X-Masking for Scan Compression Architectures","authors":"A. Chandra, R. Kapur","doi":"10.1109/ISQED.2008.31","DOIUrl":"https://doi.org/10.1109/ISQED.2008.31","url":null,"abstract":"Test stimulus and response compaction (scan compression) in scan is increasingly becoming an integral part of today's design-for-test (DFT) methodology for achieving high quality test at lower costs. Current generation integrated circuit's (ICs) are very complex designs that produce a large number of unknown values (Xs) during response capture in scan testing. Response compaction techniques have been shown to be very effective in dealing with any distribution of the Xs while not compromising on the test coverage. However, as the number of scan in pins reduce, the X-tolerance capability of these techniques degrades rapidly. In this paper we discuss interval based response compaction scheme for scan compression architectures. We present an analysis to show that very high X-tolerance can be achieved with a small number of scan-in pins and with no loss of test coverage. We also show that this eventually translates into higher compression ratio and lower test data volume.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Khalil, Y. Ismail, M. Khellah, T. Karnik, V. De
This paper explores the modeling of the propagation delay of through silicon vias (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs are very crucial in enabling the analysis and CAD in 3D integrated circuits. In this paper, an analytical model for the propagation delay of the TSV as a function of its physical dimensions is proposed. The presented analytical model is in great agreement with simulations using electromagnetic field solver and lossy transmission line circuit model. Compared to earlier interconnect models, the presented analytical model provides higher accuracy and fidelity in addition to its simplicity. Hence, the presented analytical model is very useful in the analysis of 3D integrated circuits.
{"title":"Analytical Model for the Propagation Delay of Through Silicon Vias","authors":"D. Khalil, Y. Ismail, M. Khellah, T. Karnik, V. De","doi":"10.1109/ISQED.2008.128","DOIUrl":"https://doi.org/10.1109/ISQED.2008.128","url":null,"abstract":"This paper explores the modeling of the propagation delay of through silicon vias (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs are very crucial in enabling the analysis and CAD in 3D integrated circuits. In this paper, an analytical model for the propagation delay of the TSV as a function of its physical dimensions is proposed. The presented analytical model is in great agreement with simulations using electromagnetic field solver and lossy transmission line circuit model. Compared to earlier interconnect models, the presented analytical model provides higher accuracy and fidelity in addition to its simplicity. Hence, the presented analytical model is very useful in the analysis of 3D integrated circuits.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126251249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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