Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103120
M. van Soestbergen, J. Zaal, F. Swartjes, J. Janssen
Laser grooving is used for the singulation of advanced CMOS wafers since it is believed that it exerts lower mechanical stress than traditional blade dicing. The very local heating of wafers, however, might result in high thermal stress around the heat affected zone. In this work we present a model to predict the temperature distribution, material removal, and the resulting stress, in a sandwiched structure of metals and dielectric materials that are commonly found in the back-end of line of semiconductor wafers. Simulation results on realistic three dimensional back-end structures reveal that the presence of metals clearly affects both the ablation depth, and the stress in the material. Experiments showed a similar observation for the ablation depth. The shape of the crater, however, was found to be more uniform than predicted by simulations, which is probably due to the redistribution of molten metal.
{"title":"Laser grooving of semiconductor wafers: Comparing a simplified numerical approach with experiments","authors":"M. van Soestbergen, J. Zaal, F. Swartjes, J. Janssen","doi":"10.1109/EUROSIME.2015.7103120","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103120","url":null,"abstract":"Laser grooving is used for the singulation of advanced CMOS wafers since it is believed that it exerts lower mechanical stress than traditional blade dicing. The very local heating of wafers, however, might result in high thermal stress around the heat affected zone. In this work we present a model to predict the temperature distribution, material removal, and the resulting stress, in a sandwiched structure of metals and dielectric materials that are commonly found in the back-end of line of semiconductor wafers. Simulation results on realistic three dimensional back-end structures reveal that the presence of metals clearly affects both the ablation depth, and the stress in the material. Experiments showed a similar observation for the ablation depth. The shape of the crater, however, was found to be more uniform than predicted by simulations, which is probably due to the redistribution of molten metal.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131297643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103123
K. Weide-Zaage, J. Kludt, M. Ackermann, V. Hein, M. Erstling
For mixed signal applications it is necessary to have metallization which are able to carry high currents. Also the on chip integration leads to special requirements on the metallization concerning their robustness. A common method for the determination of interconnect lifetime is described in JP001A and based on Black's law and the measurement of time to failure, medium stress current density and medium stress temperature. The highly robust metallization presented here, which was developed for higher current and temperature applications shows more complicated shapes than presently used metallization systems with metal line tracks and via. To determine a realistic life time of highly robust metallization the used method is not applicable anymore. A more suitable determination of the variables current density and temperature for AlCu metallization with W-plug can be achieved by simulations. In the metal line layout the most critical locations regarding mass flux are chosen. The results are validated by measurements.
{"title":"Life time characterization for a highly robust metallization","authors":"K. Weide-Zaage, J. Kludt, M. Ackermann, V. Hein, M. Erstling","doi":"10.1109/EUROSIME.2015.7103123","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103123","url":null,"abstract":"For mixed signal applications it is necessary to have metallization which are able to carry high currents. Also the on chip integration leads to special requirements on the metallization concerning their robustness. A common method for the determination of interconnect lifetime is described in JP001A and based on Black's law and the measurement of time to failure, medium stress current density and medium stress temperature. The highly robust metallization presented here, which was developed for higher current and temperature applications shows more complicated shapes than presently used metallization systems with metal line tracks and via. To determine a realistic life time of highly robust metallization the used method is not applicable anymore. A more suitable determination of the variables current density and temperature for AlCu metallization with W-plug can be achieved by simulations. In the metal line layout the most critical locations regarding mass flux are chosen. The results are validated by measurements.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126126984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103104
A. Salahouelhadj, M. Gonzalez, H. Oprins
In this study, Finite Element Modeling (FEM) is used to predict the stress and deformation induced by packaging and temperature hot spots for 3D-IC packages. The studied packages consist of a stack of two Si dies attached with flip chip technology to a laminate in a ball grid array (BGA) configuration. Three packages were considered in this paper: two molded packages with different epoxy mold compounds (EMCs) and one bare die package without EMC. The impact of the bottom die thickness on the stress and package deformation is investigated. The finite element simulation results indicate that thinning the bottom die will cause larger stress and more warpage induced by packaging. Moreover, temperature hot spots cause larger stress and more deformation for thinner bottom dies. Furthermore, the results show that the stress and deformation caused by processing are much higher than those induced by temperature hot spots.
{"title":"Die thickness impact on thermo-mechanical stress in 3D packages","authors":"A. Salahouelhadj, M. Gonzalez, H. Oprins","doi":"10.1109/EUROSIME.2015.7103104","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103104","url":null,"abstract":"In this study, Finite Element Modeling (FEM) is used to predict the stress and deformation induced by packaging and temperature hot spots for 3D-IC packages. The studied packages consist of a stack of two Si dies attached with flip chip technology to a laminate in a ball grid array (BGA) configuration. Three packages were considered in this paper: two molded packages with different epoxy mold compounds (EMCs) and one bare die package without EMC. The impact of the bottom die thickness on the stress and package deformation is investigated. The finite element simulation results indicate that thinning the bottom die will cause larger stress and more warpage induced by packaging. Moreover, temperature hot spots cause larger stress and more deformation for thinner bottom dies. Furthermore, the results show that the stress and deformation caused by processing are much higher than those induced by temperature hot spots.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127336563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103131
A. R. Rezaie Adliv, K. Jansen, L. Ernst
This paper comprises a numerical constitutive model for evaluating residual stresses generated during encapsulation of integrated circuits. Residual stress is a consequence of molding process which can be divided in cure and thermal induced parts. Cure originated stress had been mostly neglected in literature and a special attention had always been given to detection of thermal induced stresses. In this study, both encapsulation resulted stresses are studied independently and a numerical methodology has been developed based on the applied boundary conditions during each stage of molding and the established process dependent mechanical models. A two dimensional numerical model is implemented in a commercially available software package. The numerically predicted stress results are experimentally validated by implementing a piezoresistive stress measuring chip in a transfer molding process.
{"title":"Numerical prediction of residual stresses evolving during packaging of ICs","authors":"A. R. Rezaie Adliv, K. Jansen, L. Ernst","doi":"10.1109/EUROSIME.2015.7103131","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103131","url":null,"abstract":"This paper comprises a numerical constitutive model for evaluating residual stresses generated during encapsulation of integrated circuits. Residual stress is a consequence of molding process which can be divided in cure and thermal induced parts. Cure originated stress had been mostly neglected in literature and a special attention had always been given to detection of thermal induced stresses. In this study, both encapsulation resulted stresses are studied independently and a numerical methodology has been developed based on the applied boundary conditions during each stage of molding and the established process dependent mechanical models. A two dimensional numerical model is implemented in a commercially available software package. The numerically predicted stress results are experimentally validated by implementing a piezoresistive stress measuring chip in a transfer molding process.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130717295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103108
Mian Tao, S. Lee
Large size light-emitting diodes (LED) are frequently used in the application that requires high luminous intensity. Among diverse types of LED chips, the wire-bonding LED chip has become the most common type for its simple and mature manufacturing processes. For the commercial product manufacturing, chip bonding is one of the most critical procedures. Conventional chip bonding uses adhesive filled with thermal conductive particles. As the size of the LED chips is being enlarged, it becomes much more challenging to achieve perfect bonding. Defects may often occur in the bonding layer in practical manufacturing. Previous studies have revealed that defects inside the bonding layer will block the heat flow from the LED junction to the carrier and create non-uniform junction temperature distribution. The ordinary method to measure the junction temperature is the forward voltage method which uses the negative forward voltage-junction temperature characteristic of LEDs. Nevertheless, this standard method could not offer any information about the non-uniformity of junction temperature. As it is well understood that the junction temperature is critical to the performance of an LED device, it is necessary to find out a method to evaluate this non-uniform junction temperature phenomenon. In this study, we prepared several custom-made LED samples with artificial bonding defects to generate non-uniform junction temperature. An improved forward voltage method was developed to detect the junction temperature non-uniformity. The introduced method was experimentally validated.
{"title":"Detection of the non-uniformity of junction temperature in large light-emitting diode using an improved forward voltage method","authors":"Mian Tao, S. Lee","doi":"10.1109/EUROSIME.2015.7103108","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103108","url":null,"abstract":"Large size light-emitting diodes (LED) are frequently used in the application that requires high luminous intensity. Among diverse types of LED chips, the wire-bonding LED chip has become the most common type for its simple and mature manufacturing processes. For the commercial product manufacturing, chip bonding is one of the most critical procedures. Conventional chip bonding uses adhesive filled with thermal conductive particles. As the size of the LED chips is being enlarged, it becomes much more challenging to achieve perfect bonding. Defects may often occur in the bonding layer in practical manufacturing. Previous studies have revealed that defects inside the bonding layer will block the heat flow from the LED junction to the carrier and create non-uniform junction temperature distribution. The ordinary method to measure the junction temperature is the forward voltage method which uses the negative forward voltage-junction temperature characteristic of LEDs. Nevertheless, this standard method could not offer any information about the non-uniformity of junction temperature. As it is well understood that the junction temperature is critical to the performance of an LED device, it is necessary to find out a method to evaluate this non-uniform junction temperature phenomenon. In this study, we prepared several custom-made LED samples with artificial bonding defects to generate non-uniform junction temperature. An improved forward voltage method was developed to detect the junction temperature non-uniformity. The introduced method was experimentally validated.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"25 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103154
Jaemi L. Herzberger, A. Dasgupta, Siddhartha Das
Electrochemical migration across the surface of dielectric cracks in multilayer ceramic capacitors when exposed to humidity or condensed moisture can result in the growth of dendritic filaments, thus causing increased leakage currents or even short circuit failure. This study uses measured empirical data to demonstrate that the growth rate of the dendrite accelerates nonlinearly with time, due to the increased electric field strength and ionic flux that results from the continuously decreasing distance between the anode and the tip of the cathodic dendrite, as the dendrite grows with time. A simple 1D analytic predictive model is developed that incorporates the nonlinear growth kinetics by allowing the separation between the anode and effective cathode to vary with time. The failure time predicted by this model is calibrated with the help of the experimental data, and the dendrite growth kinetics are found to have a close qualitative and quantitative match with the experiments. A comparison is also made to a calibrated fixed-separation linear TTF prediction model in the literature and the comparison shows that the nonlinear model developed in this study produces results that are physically more meaningful than the linear model.
{"title":"Multiphysics study of electrochemical migration in ceramic capacitors","authors":"Jaemi L. Herzberger, A. Dasgupta, Siddhartha Das","doi":"10.1109/EUROSIME.2015.7103154","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103154","url":null,"abstract":"Electrochemical migration across the surface of dielectric cracks in multilayer ceramic capacitors when exposed to humidity or condensed moisture can result in the growth of dendritic filaments, thus causing increased leakage currents or even short circuit failure. This study uses measured empirical data to demonstrate that the growth rate of the dendrite accelerates nonlinearly with time, due to the increased electric field strength and ionic flux that results from the continuously decreasing distance between the anode and the tip of the cathodic dendrite, as the dendrite grows with time. A simple 1D analytic predictive model is developed that incorporates the nonlinear growth kinetics by allowing the separation between the anode and effective cathode to vary with time. The failure time predicted by this model is calibrated with the help of the experimental data, and the dendrite growth kinetics are found to have a close qualitative and quantitative match with the experiments. A comparison is also made to a calibrated fixed-separation linear TTF prediction model in the literature and the comparison shows that the nonlinear model developed in this study produces results that are physically more meaningful than the linear model.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130476895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103085
Bulong Wu, Dae-Suk Kim, B. Han, Alicja Palczynska, P. Gromala
The effects of the outer EMC on the thermal deformation of an automotive electronic control unit (ECU) are studied using moiré interferometry and FEA modeling. Two sets of ECU specimens molded with and without outer EMC are subjected to passive and active thermal conditions, respectively. Two orthogonal in-plane displacement fields on the cross section of specimens are documented at various temperatures using moiré interferometry. The results of passive condition case are used to verify the complex FEA modeling of the units, and the initial material properties are subsequently calibrated. The validity of FEA modeling after calibration is corroborated by the results obtained from the active thermal condition.
{"title":"Thermal deformation analysis of automotive electronic control units subjected to passive and active thermal conditions","authors":"Bulong Wu, Dae-Suk Kim, B. Han, Alicja Palczynska, P. Gromala","doi":"10.1109/EUROSIME.2015.7103085","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103085","url":null,"abstract":"The effects of the outer EMC on the thermal deformation of an automotive electronic control unit (ECU) are studied using moiré interferometry and FEA modeling. Two sets of ECU specimens molded with and without outer EMC are subjected to passive and active thermal conditions, respectively. Two orthogonal in-plane displacement fields on the cross section of specimens are documented at various temperatures using moiré interferometry. The results of passive condition case are used to verify the complex FEA modeling of the units, and the initial material properties are subsequently calibrated. The validity of FEA modeling after calibration is corroborated by the results obtained from the active thermal condition.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130479856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103159
R. Metasch, R. Schwerz, M. Roellig, A. Kabakchiev, B. Métais, R. Ratchev, K. Wolter
The paper presents experimental results on tinbased solder alloys to their mechanical visco-plastic deformation behaviour under systematically investigation of cooling rates and their micro-structural solidification. We developed a novel process to produce solder bulk specimens in a re-melting process under specific cooling rates up to -300 K/min. The paper shows a comparison of SnAg3.5 and SnAg3.8cuO.75 solidified with -20 Klmin and -200 Klmin as well as a SnSbCu alloy solidified with -20 Klmin and -100 K/min. By contrast to a commonly used passive cooling solution the increased cooling rates are closer to an actual industrial soldering process. The metallographic investigation shows significant changes of the micro-structure with increasing grain quantity while their size decreased. The intermetallic sizes are reduced and the surface roughness of the specimens overall decreased with higher cooling rates. The mechanical comparison of the different produced specimens uses an advanced experimental procedure to determine the material properties for a unified visco-plastic constitutive model initially proposed by Chaboche et al. The constitutive model describes the time-dependent material behaviour in the strain range of primary creep under cyclic load and isothermal conditions. This progress is performed in a temperature range between -40°C up to 150 °C, with varying strain rates between lE-3 to lE-6 per second and relaxation steps. The detailed characterization procedure has been presented in [4] and [5]. In two separate chapters the paper explains the advantages of this modelling approach on lifetime prediction using finite-element simulations.
{"title":"Experimental investigation on microstructural influence towards visco-plastic mechanical properties of Sn-based solder alloy for material modelling in finite element simulations","authors":"R. Metasch, R. Schwerz, M. Roellig, A. Kabakchiev, B. Métais, R. Ratchev, K. Wolter","doi":"10.1109/EUROSIME.2015.7103159","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103159","url":null,"abstract":"The paper presents experimental results on tinbased solder alloys to their mechanical visco-plastic deformation behaviour under systematically investigation of cooling rates and their micro-structural solidification. We developed a novel process to produce solder bulk specimens in a re-melting process under specific cooling rates up to -300 K/min. The paper shows a comparison of SnAg3.5 and SnAg3.8cuO.75 solidified with -20 Klmin and -200 Klmin as well as a SnSbCu alloy solidified with -20 Klmin and -100 K/min. By contrast to a commonly used passive cooling solution the increased cooling rates are closer to an actual industrial soldering process. The metallographic investigation shows significant changes of the micro-structure with increasing grain quantity while their size decreased. The intermetallic sizes are reduced and the surface roughness of the specimens overall decreased with higher cooling rates. The mechanical comparison of the different produced specimens uses an advanced experimental procedure to determine the material properties for a unified visco-plastic constitutive model initially proposed by Chaboche et al. The constitutive model describes the time-dependent material behaviour in the strain range of primary creep under cyclic load and isothermal conditions. This progress is performed in a temperature range between -40°C up to 150 °C, with varying strain rates between lE-3 to lE-6 per second and relaxation steps. The detailed characterization procedure has been presented in [4] and [5]. In two separate chapters the paper explains the advantages of this modelling approach on lifetime prediction using finite-element simulations.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131591175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103101
Hung-Te Yang, Yen-Fu Su, K. Chiang
This paper presents the packaging and residual stress effects on three-axis silicon-on-insulator (SOI) micro-electro-mechanical system (MEMS) accelerometer by using finite element method (FEM). The 3D FEM model was established and the resonance frequency was obtained by modal analysis method. This paper also developed a simple compensation model for trimming the offset of capacitance differentiation by measuring resonance frequency. It can be trimmed by adjusting application-specific integrated circuit (ASIC) gain. The capacitance differentiation offset which is caused by packaging effect can be effectively compensated to the standard capacitance differentiation.
{"title":"Research on packaging effects of three-axis SOI MEMS accelerometer","authors":"Hung-Te Yang, Yen-Fu Su, K. Chiang","doi":"10.1109/EUROSIME.2015.7103101","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103101","url":null,"abstract":"This paper presents the packaging and residual stress effects on three-axis silicon-on-insulator (SOI) micro-electro-mechanical system (MEMS) accelerometer by using finite element method (FEM). The 3D FEM model was established and the resonance frequency was obtained by modal analysis method. This paper also developed a simple compensation model for trimming the offset of capacitance differentiation by measuring resonance frequency. It can be trimmed by adjusting application-specific integrated circuit (ASIC) gain. The capacitance differentiation offset which is caused by packaging effect can be effectively compensated to the standard capacitance differentiation.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133415380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：