Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103165
W. V. van Driel, M. Schuld, B. Jacobs, F. Commissaris, J. van der Eyden, B. Hamon
Per today, commercial claims for LED-based products in terms of lumen maintenance are fully based on TM-21 extrapolations using LM80 data. There may be a risk in doing this as TM-21 only relies on the behavior of the average LED degradation, instead of taking into account the degradation of all individual LEDs. A more profound statistical analysis is required to make the step from TM-21 extrapolation to lumen maintenance on product level. This is needed as the commercial claims are used as input for service bids up to periods of 20 to 25 years of operation. This paper describes the different approaches currently available to perform lumen maintenance extrapolations. For that, we have analyzed several LM80 data sets from a statistical point of view.
{"title":"Lumen maintenance predictions for LED packages using LM80 data","authors":"W. V. van Driel, M. Schuld, B. Jacobs, F. Commissaris, J. van der Eyden, B. Hamon","doi":"10.1109/EUROSIME.2015.7103165","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103165","url":null,"abstract":"Per today, commercial claims for LED-based products in terms of lumen maintenance are fully based on TM-21 extrapolations using LM80 data. There may be a risk in doing this as TM-21 only relies on the behavior of the average LED degradation, instead of taking into account the degradation of all individual LEDs. A more profound statistical analysis is required to make the step from TM-21 extrapolation to lumen maintenance on product level. This is needed as the commercial claims are used as input for service bids up to periods of 20 to 25 years of operation. This paper describes the different approaches currently available to perform lumen maintenance extrapolations. For that, we have analyzed several LM80 data sets from a statistical point of view.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117122350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103093
Chia-Chi Tsai, L. Liao, Yen-Fu Su, T. Hung, K. Chiang
A high current load may cause the Joule heating, subsequently raising the chip temperature in a conventional power module. Temperature excursion in power chip may generate thermal stress, induce failure and reduce its reliability. Double-sided power module is a crucial structure to provide another heat dissipation path and efficiently reduce chip temperature. This study estimate the thermal and reliability analysis of double-sided power module by using copper bump as an interconnection under different cooling condition. The connection layout can be designed more flexible by using bump interconnection in double-sided power module. The concept of dummy ball also utilized to reduce the mechanical strain or stress of copper bump and improve its reliability in a power module.
{"title":"Reliability analysis of copper bump interconnection in double-sided power module","authors":"Chia-Chi Tsai, L. Liao, Yen-Fu Su, T. Hung, K. Chiang","doi":"10.1109/EUROSIME.2015.7103093","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103093","url":null,"abstract":"A high current load may cause the Joule heating, subsequently raising the chip temperature in a conventional power module. Temperature excursion in power chip may generate thermal stress, induce failure and reduce its reliability. Double-sided power module is a crucial structure to provide another heat dissipation path and efficiently reduce chip temperature. This study estimate the thermal and reliability analysis of double-sided power module by using copper bump as an interconnection under different cooling condition. The connection layout can be designed more flexible by using bump interconnection in double-sided power module. The concept of dummy ball also utilized to reduce the mechanical strain or stress of copper bump and improve its reliability in a power module.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103096
M. Lofrano, Mario Gonzalez, W. Guo, G. van der Plas
In this work CPI induced mechanical stress for 3D stacks and 3D interposer packages is studied. The stress built during package assembly has been obtained using finite element modeling (FEM). For the package layout and materials properties chosen for this work, the results shown that the stresses induced during the processing of a 3D stacks and 3D interposer configuration are similar when they are assembled in a Flip Chip Ball Grid Array (fcBGA) package. Furthermore, the interconnection between the different silicon dies assured with the use of μbumps were analyzed with different interconnect densities and configurations. Results shown that stress induced around the μbumps increases by increasing the μbump pitch. Different molding configurations for the fcBGA packages were investigated, including high power (exposed die) and low power (embedded dies) packages. The results showed that exposed die packages present lower out of plane deformation due to a reduction of the epoxy mold compound (EMC) thickness. It is very important to accurately calculate the residual stresses that each processing steps of the assembly induced on the die. Mass reflow and thermo compression bonding process assembly have been investigated. Results showed that solder joint reflow is the bottleneck for mass reflow process assembly, high stress in this step indicate that failures can occur. In this work we showed that low CTE laminate is a good alternative to reduce until 60% stress at flip chip reflow step.
{"title":"Chip package interaction: A stress analysis on 3D IC's packages","authors":"M. Lofrano, Mario Gonzalez, W. Guo, G. van der Plas","doi":"10.1109/EUROSIME.2015.7103096","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103096","url":null,"abstract":"In this work CPI induced mechanical stress for 3D stacks and 3D interposer packages is studied. The stress built during package assembly has been obtained using finite element modeling (FEM). For the package layout and materials properties chosen for this work, the results shown that the stresses induced during the processing of a 3D stacks and 3D interposer configuration are similar when they are assembled in a Flip Chip Ball Grid Array (fcBGA) package. Furthermore, the interconnection between the different silicon dies assured with the use of μbumps were analyzed with different interconnect densities and configurations. Results shown that stress induced around the μbumps increases by increasing the μbump pitch. Different molding configurations for the fcBGA packages were investigated, including high power (exposed die) and low power (embedded dies) packages. The results showed that exposed die packages present lower out of plane deformation due to a reduction of the epoxy mold compound (EMC) thickness. It is very important to accurately calculate the residual stresses that each processing steps of the assembly induced on the die. Mass reflow and thermo compression bonding process assembly have been investigated. Results showed that solder joint reflow is the bottleneck for mass reflow process assembly, high stress in this step indicate that failures can occur. In this work we showed that low CTE laminate is a good alternative to reduce until 60% stress at flip chip reflow step.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103135
K. Brinkfeldt, T. Åklint, K. Neumaier, Olaf Zschieschang, Michael Edwards, D. Andersson
In power electronics, more efficient removal of heat from the junction of power devices leads to a higher power rating per die, which in turn leads to fewer die and reduced system volume. Since temperature is a main driver in expected failure modes an increase in cooling capability can also enhance margins of the device reliability.
{"title":"Model verification of heat exchangers in a flow test rig","authors":"K. Brinkfeldt, T. Åklint, K. Neumaier, Olaf Zschieschang, Michael Edwards, D. Andersson","doi":"10.1109/EUROSIME.2015.7103135","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103135","url":null,"abstract":"In power electronics, more efficient removal of heat from the junction of power devices leads to a higher power rating per die, which in turn leads to fewer die and reduced system volume. Since temperature is a main driver in expected failure modes an increase in cooling capability can also enhance margins of the device reliability.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125387937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103115
P. Gaiser, M. Klingler, J. Wilde
Nowadays, the progress in power electronics requires the improvement of the reliability of DBC ceramics. The well-documented phenomenon of conchoidal cracking initiates failures at the metallization-ceramic interface. It is a result of the CTE mismatch between metallization and ceramics. Thermal cycling stresses lead to crack propagation which can consequently lead to failure in power devices due to diminished heat dissipation. In this paper, a novel concept was used in order to analyze the thermo-mechanical stresses in DBC ceramics under passive thermal cycling conditions by combining the Finite Element Method and fracture mechanics. Fracture mechanical parameters such as stress intensity factors and the J-integral were calculated with regard to the variation of the dimple depth, the topology of the etched metal edge and the ceramic thickness. Furthermore, this concept was applied to optimize the edge geometry of the metallization with the criterion of stress reduction at the metal-ceramic interface. The concept to minimize local stresses as a basis for reliability improvement will have to be validated experimentally. By this methodology, improvements in substrate technology for future power electronic assembly are made possible. The principle of this study presented here is the basis for a future lifetime prediction.
{"title":"Fracture mechanical modeling for the stress analysis of DBC ceramics","authors":"P. Gaiser, M. Klingler, J. Wilde","doi":"10.1109/EUROSIME.2015.7103115","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103115","url":null,"abstract":"Nowadays, the progress in power electronics requires the improvement of the reliability of DBC ceramics. The well-documented phenomenon of conchoidal cracking initiates failures at the metallization-ceramic interface. It is a result of the CTE mismatch between metallization and ceramics. Thermal cycling stresses lead to crack propagation which can consequently lead to failure in power devices due to diminished heat dissipation. In this paper, a novel concept was used in order to analyze the thermo-mechanical stresses in DBC ceramics under passive thermal cycling conditions by combining the Finite Element Method and fracture mechanics. Fracture mechanical parameters such as stress intensity factors and the J-integral were calculated with regard to the variation of the dimple depth, the topology of the etched metal edge and the ceramic thickness. Furthermore, this concept was applied to optimize the edge geometry of the metallization with the criterion of stress reduction at the metal-ceramic interface. The concept to minimize local stresses as a basis for reliability improvement will have to be validated experimentally. By this methodology, improvements in substrate technology for future power electronic assembly are made possible. The principle of this study presented here is the basis for a future lifetime prediction.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127613023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103164
R. Hamou, D. N. Wright, Astrid-Sofie B. Vardøy, M. Haupt, S. Helland, H. Kristiansen, M. Taklo
In this study, we explore the thermo-mechanical stress distribution of a chip/substrate BGA interconnect based on metal coated polymer spheres (MPS) of 30 μm diameter. The bonding of the chip to a glass substrate with MPS is obtained by deposition and sintering of a silver nanoparticle suspension that forms a menisci needed for necking and metallic bonding of the MPS towards pads. The stand-off height is determined by the ball diameter, thus the necks and the MPS coating are considered to be the critical parameters of the system. The simulation study is focused on varying the shape and the size of the neck and the MPS coating thickness. The polymer core is modeled as a viscoelastic material using generalized Maxwell model with Prony series. The distribution of the relaxed thermal stress and strain within the MPS coating and necks is analyzed as a function of temperature and the identified critical parameters. Moreover, shear test measurements of single MPS and SEM images of the structures are presented and discussed, in order to expose the feasibility of this new interconnect technology.
{"title":"Analyzing thermo-mechanical reliability of an interconnect based on metal coated polymer spheres (MPS)","authors":"R. Hamou, D. N. Wright, Astrid-Sofie B. Vardøy, M. Haupt, S. Helland, H. Kristiansen, M. Taklo","doi":"10.1109/EUROSIME.2015.7103164","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103164","url":null,"abstract":"In this study, we explore the thermo-mechanical stress distribution of a chip/substrate BGA interconnect based on metal coated polymer spheres (MPS) of 30 μm diameter. The bonding of the chip to a glass substrate with MPS is obtained by deposition and sintering of a silver nanoparticle suspension that forms a menisci needed for necking and metallic bonding of the MPS towards pads. The stand-off height is determined by the ball diameter, thus the necks and the MPS coating are considered to be the critical parameters of the system. The simulation study is focused on varying the shape and the size of the neck and the MPS coating thickness. The polymer core is modeled as a viscoelastic material using generalized Maxwell model with Prony series. The distribution of the relaxed thermal stress and strain within the MPS coating and necks is analyzed as a function of temperature and the identified critical parameters. Moreover, shear test measurements of single MPS and SEM images of the structures are presented and discussed, in order to expose the feasibility of this new interconnect technology.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124386013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103124
Bo Sun, Xuejun Fan, C. Yuan, C. Qian, Guoqi Zhang
The failure of aluminum electrolytic capacitors is considered as one of major failure modes of the LED drivers. This paper propose a degradation model of aluminum electrolytic capacitors considers impacts of operation time and temperature.
{"title":"A degradation model of aluminum electrolytic capacitors for LED drivers","authors":"Bo Sun, Xuejun Fan, C. Yuan, C. Qian, Guoqi Zhang","doi":"10.1109/EUROSIME.2015.7103124","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103124","url":null,"abstract":"The failure of aluminum electrolytic capacitors is considered as one of major failure modes of the LED drivers. This paper propose a degradation model of aluminum electrolytic capacitors considers impacts of operation time and temperature.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103091
A. Grams, Jan Hofer, A. Middendorf, S. Schmitz, O. Wittler, K. Lang
Wire bond degradation is a limiting factor for the lifetime of state of the art power modules. So, there is a need for widely applicable and proven modelling techniques to achieve a reliable design. In this paper, a new crack growth law has been developed and calibrated with experimental data. By defining a failure criterion and optimizing model parameters, good lifetime predictions have been achieved. In addition, further possibilities to use this modelling approach have been proposed, e.g. damage in interconnect layers as sinter silver or solder layers could be considered.
{"title":"A geometry-independent lifetime modelling method for aluminum heavy wire bond joints","authors":"A. Grams, Jan Hofer, A. Middendorf, S. Schmitz, O. Wittler, K. Lang","doi":"10.1109/EUROSIME.2015.7103091","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103091","url":null,"abstract":"Wire bond degradation is a limiting factor for the lifetime of state of the art power modules. So, there is a need for widely applicable and proven modelling techniques to achieve a reliable design. In this paper, a new crack growth law has been developed and calibrated with experimental data. By defining a failure criterion and optimizing model parameters, good lifetime predictions have been achieved. In addition, further possibilities to use this modelling approach have been proposed, e.g. damage in interconnect layers as sinter silver or solder layers could be considered.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126308404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103111
E. Zukowski, T. Kimpel, Daniel Kraetschmer, A. Roessle
Printed circuit boards (PCB) are complex geometrical and functional systems that may be exposed to a combination of external and internal loads. In order to evaluate the dynamic behaviour of PCBs in early stages of the development process, modal finite element (FE) simulations are used. Realistic results for a wide frequency range can only be achieved if all the geometrical features, such as PCB assembly, copper layer thicknesses, prepreg structures, etc. with the appropriate material properties are taken into account. To model a printed circuit board including all details such as glass fiber-epoxy compounds and copper traces is possible, but is found to be very time-consuming. A method to model PCBs was developed taking into account the corresponding functional board layout and assembly. In order to ensure an appropriate representation of the layout-dependent local material properties for FE applications without considering the geometry in full detail, a simplified approach based on general composite theory, domain-specific mixture rules and generalized laminate theory was developed. The analytically calculated material property distributions of the PCB such as local stiffness values and densities can be transferred to the meshed geometry. To verify the developed method by comparison with experimentally achieved results, operational modal analysis (OMA) for a frequency up to 25 kHz was carried out by piezo patch transducer. It can be shown that both simulated mode shapes and natural frequencies of the non-assembled board show a very good agreement with the experimental results.
{"title":"Efficient modeling of printed circuit boards structures for dynamic simulations","authors":"E. Zukowski, T. Kimpel, Daniel Kraetschmer, A. Roessle","doi":"10.1109/EUROSIME.2015.7103111","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103111","url":null,"abstract":"Printed circuit boards (PCB) are complex geometrical and functional systems that may be exposed to a combination of external and internal loads. In order to evaluate the dynamic behaviour of PCBs in early stages of the development process, modal finite element (FE) simulations are used. Realistic results for a wide frequency range can only be achieved if all the geometrical features, such as PCB assembly, copper layer thicknesses, prepreg structures, etc. with the appropriate material properties are taken into account. To model a printed circuit board including all details such as glass fiber-epoxy compounds and copper traces is possible, but is found to be very time-consuming. A method to model PCBs was developed taking into account the corresponding functional board layout and assembly. In order to ensure an appropriate representation of the layout-dependent local material properties for FE applications without considering the geometry in full detail, a simplified approach based on general composite theory, domain-specific mixture rules and generalized laminate theory was developed. The analytically calculated material property distributions of the PCB such as local stiffness values and densities can be transferred to the meshed geometry. To verify the developed method by comparison with experimentally achieved results, operational modal analysis (OMA) for a frequency up to 25 kHz was carried out by piezo patch transducer. It can be shown that both simulated mode shapes and natural frequencies of the non-assembled board show a very good agreement with the experimental results.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130459552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/EUROSIME.2015.7103114
J. Auersperg, D. Breuer, K. Machani, S. Rzepka, B. Michel
With the recent increase in Gold (Au) wire cost; Copper (Cu) wire becomes an attractive way to manage overall package cost. On the other hand, Copper wire bonding introduces much higher mechanical impact to underlying BEoLstructures and actives because of the higher stiffness and lower ductility of Copper compared to Gold. These trends are accompanied by the application of new porous or nano-particle filled materials like low-k and ultra low-k materials for Back-end of line (BEoL) layers of advanced CMOS technologies. As a result, higher delamination and cracking risks in BEoLstructures underneath bonded areas represent an increasing challenge for the thermo-mechanical reliability requirements. To overcome the related reliability issues the authors performed a two level nonlinear FEM-simulation approach. Initially nonlinear axisymmetric modeling and simulation of the copper bonding process are coupled with a spatial simulation model of the whole BeoL and bond pad structure. Cracking and delamination risks are estimated by a surface based cohesive contact approach and the utilization of a crushing foam constitutive material model for ultra low-k materials.
{"title":"FEA study of damage and cracking risks in BEoL structures under copper wirebonding impact","authors":"J. Auersperg, D. Breuer, K. Machani, S. Rzepka, B. Michel","doi":"10.1109/EUROSIME.2015.7103114","DOIUrl":"https://doi.org/10.1109/EUROSIME.2015.7103114","url":null,"abstract":"With the recent increase in Gold (Au) wire cost; Copper (Cu) wire becomes an attractive way to manage overall package cost. On the other hand, Copper wire bonding introduces much higher mechanical impact to underlying BEoLstructures and actives because of the higher stiffness and lower ductility of Copper compared to Gold. These trends are accompanied by the application of new porous or nano-particle filled materials like low-k and ultra low-k materials for Back-end of line (BEoL) layers of advanced CMOS technologies. As a result, higher delamination and cracking risks in BEoLstructures underneath bonded areas represent an increasing challenge for the thermo-mechanical reliability requirements. To overcome the related reliability issues the authors performed a two level nonlinear FEM-simulation approach. Initially nonlinear axisymmetric modeling and simulation of the copper bonding process are coupled with a spatial simulation model of the whole BeoL and bond pad structure. Cracking and delamination risks are estimated by a surface based cohesive contact approach and the utilization of a crushing foam constitutive material model for ultra low-k materials.","PeriodicalId":250897,"journal":{"name":"2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114883778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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