Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250057
I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, H. Smith
In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data-bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.
{"title":"A CAD methodology for the characterization of wide on-chip buses","authors":"I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, H. Smith","doi":"10.1109/EPEP.2003.1250057","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250057","url":null,"abstract":"In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data-bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123528288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250007
Jooyong Kim, D. Neikirk
In this paper, we present the results of microwave measurements of copper/low-k transmission line interconnects. From measured S-parameters, the extracted R, L, and C for copper/low-k transmission lines are presented. In addition, the relative dielectric constant and loss tangent for various dielectric materials (SiO/sub 2/, low-k2 (Novellus Coral low-k dielectric), and low-k1 (JSR Corp. low-k dielectric)) up to 40 GHz are given.
{"title":"Experimental characterization of copper/low-k transmission line interconnects through microwave measurements","authors":"Jooyong Kim, D. Neikirk","doi":"10.1109/EPEP.2003.1250007","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250007","url":null,"abstract":"In this paper, we present the results of microwave measurements of copper/low-k transmission line interconnects. From measured S-parameters, the extracted R, L, and C for copper/low-k transmission lines are presented. In addition, the relative dielectric constant and loss tangent for various dielectric materials (SiO/sub 2/, low-k2 (Novellus Coral low-k dielectric), and low-k1 (JSR Corp. low-k dielectric)) up to 40 GHz are given.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124347132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250059
P. Feldmann
The verification of noise in on-chip global interconnect is performed through simulation of an electrical circuit comprised of a network of coupled transmission lines, terminated by appropriate models for drivers (transmitters) and loads (receivers). The current methodology utilizes linearized models of the terminations, thus requiring only linear circuit simulations. In this study, we show that while a linear noise analysis methodology that relies on the termination model linearization is very efficient and convenient, it may result in significant loss of accuracy and/or in excessively conservative designs. We identify the situations where modeling the nonlinearity of the termination becomes a determining factor in the accuracy of the analysis. We also study the implications of adopting a fully nonlinear analysis methodology, and propose a practical compromise.
{"title":"The necessity and consequences of modeling driver and load nonlinearity in on-chip global interconnect noise verification","authors":"P. Feldmann","doi":"10.1109/EPEP.2003.1250059","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250059","url":null,"abstract":"The verification of noise in on-chip global interconnect is performed through simulation of an electrical circuit comprised of a network of coupled transmission lines, terminated by appropriate models for drivers (transmitters) and loads (receivers). The current methodology utilizes linearized models of the terminations, thus requiring only linear circuit simulations. In this study, we show that while a linear noise analysis methodology that relies on the termination model linearization is very efficient and convenient, it may result in significant loss of accuracy and/or in excessively conservative designs. We identify the situations where modeling the nonlinearity of the termination becomes a determining factor in the accuracy of the analysis. We also study the implications of adopting a fully nonlinear analysis methodology, and propose a practical compromise.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122500294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250037
T. Zhou, G. Katopis
Closed-form formulae are derived for wiring escape from an area array to the standard horizontal ground rules of the package level under consideration. The required layer counts for successful escape based on two strategies are given in this paper. The effects of lines per channel, extra channels at the edges of an area array, different via technologies, and signal pin depopulation are considered in the derivations. The resulting closed-form formulae are also used to a high performance printed wiring board for the estimation of the layers needed. The estimation of the layer count from our formulae agrees with the one achieved empirically in the actual design.
{"title":"Applications of closed-form wiring escape formulae to a high performance printed wiring board","authors":"T. Zhou, G. Katopis","doi":"10.1109/EPEP.2003.1250037","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250037","url":null,"abstract":"Closed-form formulae are derived for wiring escape from an area array to the standard horizontal ground rules of the package level under consideration. The required layer counts for successful escape based on two strategies are given in this paper. The effects of lines per channel, extra channels at the edges of an area array, different via technologies, and signal pin depopulation are considered in the derivations. The resulting closed-form formulae are also used to a high performance printed wiring board for the estimation of the layers needed. The estimation of the layer count from our formulae agrees with the one achieved empirically in the actual design.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122663176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250064
Y. Chu, W. Chew
A surface integral equation (SIE) method based on contact-region modeling is applied for complicated electrically small structures in packaging and interconnect analysis. LF-MLFMA is employed to solve the matrix equation with O(N) computational cost.
{"title":"A surface integral equation method for solving complicated electrically small structures","authors":"Y. Chu, W. Chew","doi":"10.1109/EPEP.2003.1250064","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250064","url":null,"abstract":"A surface integral equation (SIE) method based on contact-region modeling is applied for complicated electrically small structures in packaging and interconnect analysis. LF-MLFMA is employed to solve the matrix equation with O(N) computational cost.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115856339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250058
M. Mazumder, R. Bohnke, A. Husain, D. Grannes, E. Chiprout, Lei Sun, S. Menon, J. Eells, C. Dai
On-chip inductance noise is becoming an increasingly important part of the total noise, particularly for global on-chip interconnects, because of faster transistor speeds and higher drive currents. An efficient pre-layout tool has been developed for accurate analysis of high frequency inductance effects on bus design. Since the return loop for inductance is not known a priori, a novel technique has been developed for fast determination of the inductance extraction window size to include all significant couplings and a sufficient number of power/ground return conductors. In addition, an algorithm has been developed for worst-case vector generation to estimate worst-case peak noise. The tool includes a methodology to determine the impact of power supply noise on bus crosstalk noise. It integrates RLC extraction, netlist generation, automatic worst-case vector generation, transient simulation, optimization, and post-processing of the simulated results to calculate noise, delay, and other signal integrity metrics. We demonstrate its application on optimal bus design by a microprocessor design group.
{"title":"An efficient pre-layout on-chip inductance noise modeling tool for bus design","authors":"M. Mazumder, R. Bohnke, A. Husain, D. Grannes, E. Chiprout, Lei Sun, S. Menon, J. Eells, C. Dai","doi":"10.1109/EPEP.2003.1250058","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250058","url":null,"abstract":"On-chip inductance noise is becoming an increasingly important part of the total noise, particularly for global on-chip interconnects, because of faster transistor speeds and higher drive currents. An efficient pre-layout tool has been developed for accurate analysis of high frequency inductance effects on bus design. Since the return loop for inductance is not known a priori, a novel technique has been developed for fast determination of the inductance extraction window size to include all significant couplings and a sufficient number of power/ground return conductors. In addition, an algorithm has been developed for worst-case vector generation to estimate worst-case peak noise. The tool includes a methodology to determine the impact of power supply noise on bus crosstalk noise. It integrates RLC extraction, netlist generation, automatic worst-case vector generation, transient simulation, optimization, and post-processing of the simulated results to calculate noise, delay, and other signal integrity metrics. We demonstrate its application on optimal bus design by a microprocessor design group.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126892175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250027
J. Pak, Junwoo Lee, Hyungsoo Kim, Joungho Kim
We introduce a modeling and simulation method to predict power/ground plane resonance and edge radiation coupled from the broken return current path of a through-hole signal via, and analyze the coupling and radiation mechanism. The approach is successfully verified with a series of measurements with various plane conditions.
{"title":"Prediction and verification of power/ground plane edge radiation excited by through-hole signal via based on balanced TLM and via coupling model","authors":"J. Pak, Junwoo Lee, Hyungsoo Kim, Joungho Kim","doi":"10.1109/EPEP.2003.1250027","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250027","url":null,"abstract":"We introduce a modeling and simulation method to predict power/ground plane resonance and edge radiation coupled from the broken return current path of a through-hole signal via, and analyze the coupling and radiation mechanism. The approach is successfully verified with a series of measurements with various plane conditions.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121984331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250044
A. Woo, T. Yioultsis, A. Cangellaris
"BestFit" refers to a mathematical methodology used for the direct passive synthesis of SPICE-compatible models of multi-conductor interconnect structures. Given the bandwidth of simulation, the length of the interconnect system, and its per-unit-length, frequency-dependent resistance, inductance, capacitance and conductance matrices, the proposed algorithm synthesizes a compact, multi-port, dispersive, SPICE-compatible model for the interconnect. The resulting model is in terms of a concatenation of a number of non-uniform segments of lumped passive circuit representations of the per-unit-length series impedance and shunt admittance matrices, the lengths of which are obtained as a result of a Pade-Chebyshev approximation of the frequency-dependent input impedance matrix of the multiconductor transmission line system. The synthesized circuit is "optimal" in the sense that highly-accurate responses can be obtained with a number of segments per minimum wavelength barely exceeding the Nyquist limit of 2.
{"title":"BestFit: a SPICE-compatible model for efficient, passive, broadband transmission-line analysis of dispersive interconnects","authors":"A. Woo, T. Yioultsis, A. Cangellaris","doi":"10.1109/EPEP.2003.1250044","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250044","url":null,"abstract":"\"BestFit\" refers to a mathematical methodology used for the direct passive synthesis of SPICE-compatible models of multi-conductor interconnect structures. Given the bandwidth of simulation, the length of the interconnect system, and its per-unit-length, frequency-dependent resistance, inductance, capacitance and conductance matrices, the proposed algorithm synthesizes a compact, multi-port, dispersive, SPICE-compatible model for the interconnect. The resulting model is in terms of a concatenation of a number of non-uniform segments of lumped passive circuit representations of the per-unit-length series impedance and shunt admittance matrices, the lengths of which are obtained as a result of a Pade-Chebyshev approximation of the frequency-dependent input impedance matrix of the multiconductor transmission line system. The synthesized circuit is \"optimal\" in the sense that highly-accurate responses can be obtained with a number of segments per minimum wavelength barely exceeding the Nyquist limit of 2.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123139802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250046
M. Facez Ktata, Hartmut Grabinski, Gabriel G, Helmut
In this paper, we investigate the effects of floating and grounded substrates with different conductivities of 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnections in the frequency range from 1 Hz up to 40 GHz. We show that the frequency dependency of line parameters, especially the inductance and resistance per unit length, depends strongly on whether the substrate is grounded or floating, on the relative position of the ground line with respect to the signal lines, and on the substrate conductivity.
{"title":"When are substrate effects important for on-chip interconnects?","authors":"M. Facez Ktata, Hartmut Grabinski, Gabriel G, Helmut","doi":"10.1109/EPEP.2003.1250046","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250046","url":null,"abstract":"In this paper, we investigate the effects of floating and grounded substrates with different conductivities of 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnections in the frequency range from 1 Hz up to 40 GHz. We show that the frequency dependency of line parameters, especially the inductance and resistance per unit length, depends strongly on whether the substrate is grounded or floating, on the relative position of the ground line with respect to the signal lines, and on the substrate conductivity.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123869863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250010
G. Shiue, R. Wu
The signal propagating along a microstrip line over a slot on the power plane will suffer from composite effects of reflected noise by a discontinuity in the signal return path and ground bounce between power/ground planes. The paper investigates noise reduction by using differential signaling. An efficient 2D FDTD method, together with equivalent circuits for the differential line and the slot, is established and simulations are performed for a three-layer structure to characterize ground bounce coupling.
{"title":"Reduction in reflections and ground bounce for signal line through a split power plane by using differential coupled microstrip lines","authors":"G. Shiue, R. Wu","doi":"10.1109/EPEP.2003.1250010","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250010","url":null,"abstract":"The signal propagating along a microstrip line over a slot on the power plane will suffer from composite effects of reflected noise by a discontinuity in the signal return path and ground bounce between power/ground planes. The paper investigates noise reduction by using differential signaling. An efficient 2D FDTD method, together with equivalent circuits for the differential line and the slot, is established and simulations are performed for a three-layer structure to characterize ground bounce coupling.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125015849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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